www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
FEATURES
DESCRIPTION
D Operates With a 3.3-V Supply
The
SN65HVD10,
SN75HVD10,
SN65HVD11,
SN75HVD11, SN65HVD12, and SN75HVD12 combine a
3-state differential line driver and differential input line
receiver that operate with a single 3.3-V power supply.
They are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and ISO
8482:1993. These differential bus transceivers are
monolithic integrated circuits designed for bidirectional
data communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and active-low
enables respectively, that can be externally connected
together to function as direction control. Very low device
standby supply current can be achieved by disabling the
driver and the receiver.
D Bus-Pin ESD Protection Exceeds 16 kV HBM
D 1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
D Optional Driver Output Transition Times for
Signaling Rates† of 1 Mbps, 10 Mbps and
25 Mbps
D Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
D Bus-Pin Short Circuit Protection From –7 V to
12 V
D Low-Current Standby Mode . . . 1 µA Typical
D Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
D Thermal Shutdown Protection
D Glitch-Free Power-Up and Power-Down
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/ output
(I/O) bus port that is designed to offer minimum loading to
the bus whenever the driver is disabled or VCC = 0. These
parts feature wide positive and negative common-mode
voltage ranges, making them suitable for party-line
applications.
Protection for Hot-Plugging Applications
D OR P PACKAGE
(TOP VIEW)
D SN75176 Footprint
APPLICATIONS
D Digital Motor Control
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
D Utility Meters
LOGIC DIAGRAM
(POSITIVE LOGIC)
D Chassis-to-Chassis Interconnects
D Electronic Security Stations
D Industrial Process Control
D Building Automation
D Point-of-Sale (POS) Terminals and Networks
R
RE
DE
1
2
3
6
4
D
7
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
!"#$%! & '("")% $& ! *(+,'$%! -$%) "!-('%&
'!!"# %! &*)''$%!& *)" %.) %)"#& ! )/$& &%"(#)%& &%$-$"- 0$""$%1
"!-('%! *"!')&&2 -!)& !% )')&&$",1 ',(-) %)&%2 ! $,, *$"$#)%)"&
Copyright 2002−2003, Texas Instruments Incorporated
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
SIGNALING RATE
UNIT LOADS
TA
25 Mbps
1/2
10 Mbps
1/8
SN65HVD11D
SN65HVD11P
VP11
1 Mbps
1/8
SN65HVD12D
SN65HVD12P
VP12
25 Mbps
1/2
SN75HVD10D
SN75HVD10P
VN10
10 Mbps
1/8
1 Mbps
1/8
25 Mbps
1/2
−40°C
−40
C to 85
85°C
C
SOIC MARKING
SOIC(1)
PDIP
SN65HVD10D
SN65HVD10P
VP10
SN75HVD11D
SN75HVD11P
VN11
SN75HVD12D
SN75HVD12P
VN12
SN65HVD10QD
SN65HVD10QP
VP10Q
10 Mbps
1/8
SN65HVD11QD
SN65HVD11QP
(1) The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
VP11Q
−0°C
−0
C to 70
70°C
C
−40°C to 125°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
SN65HVD10, SN75HVD10
SN65HVD11, SN75HVD11
SN65HVD12, SN75HVD12
Supply voltage range, VCC
−0.3 V to 6 V
Voltage range at A or B
−9 V to 14 V
Input voltage range at D, DE, R or RE
−0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
Electrostatic discharge
Human body model(3)
Charged-device model(4)
−50 V to 50 V
A, B and GND
16 kV
All pins
4 kV
All pins Charge
1 kV
Continuous total power dissipation
See Dissipation Rating Table
Junction temperature, TJ
170°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
TA ≤ 25°C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D(2)
D(3)
597 mW
4.97 mW/°C
373 mW
298 mW
100 mW
990 mW
8.26 mW/°C
620 mW
496 mW
165 mW
P
1290 mW
10.75 mW/°C
806 mW
645 mW
215 mW
PACKAGE
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51−3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51−7.
2
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
NOM
MAX UNIT
3
(1)
−7
3.6
V
12
V
V
V
High-level input voltage, VIH
D, DE, RE
2
Low-level input voltage, VIL
D, DE, RE
0
VCC
0.8
−12
12
Differential input voltage, VID (see Figure 7)
Driver
High-level output current, IOH
−60
Receiver
mA
−8
Driver
Low-level output current, IOL
60
Receiver
8
Differential load resistance, RL
54
Differential load capacitance, CL
Signaling rate
V
mA
60
Ω
50
pF
HVD10
25
HVD11
10 Mbps
HVD12
1
Junction temperature, TJ(2)
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.
145
°C
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VIK
|VOD|
TEST CONDITIONS
Input clamp voltage
II = −18 mA
IO = 0
∆|VOD|
Change in magnitude of differential output
voltage
VOC(PP)
VOC(SS)
Peak-to-peak common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage
IOZ
High-impedance output current
Input current
IOS
C(OD)
Short-circuit output current
−7 V ≤ VO ≤ 12 V
Differential output capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
RE at VCC,
Receiver disabled and
D & DE at
driver enabled
VCC, No load
Supply current
1.5
V
1.5
−0.2
0.2
V
mV
1.4
2.5
V
−0.05
0.05
V
See receiver input currents
D
II
ICC
VCC
400
See Figure 3
UNIT
V
2
See Figure 1 and Figure 2
Steady-state common-mode output voltage
MAX
−1.5
RL = 54 Ω, See Figure 1
Vtest = −7 V to 12 V, See Figure 2
Differential output voltage(2)
MIN TYP(1)
DE
−100
0
0
100
−250
250
16
µA
mA
pF
9
15.5
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and
driver disabled (standby)
1
5
µA
RE at 0 V,
D & DE at
VCC, No load
Receiver enabled and
driver enabled
9
15.5
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For TA > 85°C, VCC is ±5%.
3
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
TEST CONDITIONS
tf
tsk(p)
tsk(pp)(2)
tPZH
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL − tPLH|)
Part-to-part skew
Propagation delay time,
high-impedance-to-high-level output
5
8.5
16
HVD11
18
25
40
HVD12
135
200
300
HVD10
5
8.5
16
HVD11
18
25
40
HVD12
135
200
300
3
4.5
10
10
20
30
HVD12
100
170
300
HVD10
3
4.5
10
HVD11
tPZL
Propagation delay time,
high-level-to-high-impedance output
Propagation delay time,
high-impedance-to-low-level output
10
20
30
HVD12
100
170
300
HVD10
1.5
HVD11
2.5
HVD12
7
HVD10
6
HVD11
11
HVD12
100
HVD10
31
HVD11
55
HVD12
300
Propagation delay time,
low-level-to-high-impedance output
RL = 110 Ω, RE at 0 V,
See Figure 5
55
HVD12
300
HVD10
26
HVD11
55
HVD12
300
RL = 110 Ω, RE at 0 V,
See Figure 6
UNIT
ns
ns
ns
ns
ns
ns
ns
25
HVD11
HVD10
tPLZ
RL = 54 Ω, CL = 50 pF,
See Figure 4
HVD11
HVD10
tPHZ
MAX
HVD10
HVD10
tr
MIN TYP(1)
ns
ns
26
HVD11
75
HVD12
400
ns
tPZH
Propagation delay time, standby-to-high-level output
RL = 110 Ω, RE at 3 V,
See Figure 5
6
µs
tPZL
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 6
6
µs
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
IO = −8 mA
VIT−
Negative-going input threshold
voltage
IO = 8 mA
Vhys
VIK
Hysteresis voltage (VIT+ − VIT−)
VOH
VOL
High-level output voltage
IOZ
High-impedance-state output current
Enable-input clamp voltage
Low-level output voltage
Bus input current
II = −18 mA
VID = 200 mV,
VID = −200 mV,
VO = 0 or VCC
VA or VB = −7 V
VA or VB = −7 V,
VA or VB = 12 V
VA or VB = 12 V,
VA or VB = −7 V
VA or VB = −7 V,
IIH
IIL
High-level input current, RE
CID
Differential input capacitance
ICC
Low-level input current, RE
Supply current
MAX
UNIT
−0.01
V
−0.2
35
VA or VB = 12 V
VA or VB = 12 V,
II
MIN TYP(1)
mV
−1.5
IOH = −8 mA,
IOL = 8 mA,
See Figure 7
0.4
−1
HVD11, HVD12,
Other input at 0 V
VCC = 0 V
VCC = 0 V
V
See Figure 7
RE at VCC
VCC = 0 V
V
2.4
HVD10,
Other input at 0 V
VCC = 0 V
VIH = 2 V
VIL = 0.8 V
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
RE at 0 V,
Receiver enabled and driver
D & DE at 0 V,
disabled
No load
1
0.05
0.11
0.06
0.13
−0.1
−0.05
−0.05
−0.04
0.5
0.25
0.5
−0.2
−0.4
−0.15
µA
mA
0.2
−0.4
V
mA
−30
0
µA
−30
0
µA
15
pF
4
8
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and driver
disabled (standby)
1
5
µA
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled and driver
enabled
9
15.5
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
5
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
HVD10
12.5
20
25
Propagation delay time, high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time, low-to-high-level output
HVD11
HVD12
30
55
70
ns
30
55
70
ns
tPHL
Propagation delay time, high-to-low-level output
tsk(p)
Pulse skew (|tPHL − tPLH|)
tsk(pp)(2)
Part-to-part skew
tr
tf
Output signal rise time
tPZH(1)
tPZL(1)
Output enable time to high level
tPHZ
tPLZ
tPZH(2)
Output disable time from high level
HVD11
HVD12
VID = −1.5 V to 1.5 V,
CL = 15 pF, See Figure 8
HVD10
1.5
HVD11
4
HVD12
4
HVD10
8
HVD11
15
HVD12
15
CL = 15 pF, See Figure 8
Output signal fall time
1
2
5
1
2
5
ns
ns
ns
ns
15
Output enable time to low level
15
CL = 15 pF, DE at 3 V,
See Figure 9
20
Output disable time from low level
ns
15
Propagation delay time, standby-to-high-level output
6
CL = 15 pF, DE at 0,
µss
See Figure 10
tPZL(2)
Propagation delay time, standby-to-low-level output
6
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER
θJA
Junction−to−ambient thermal resistance(2)
θJB
Junction−to−board thermal resistance
θJC
PD
TA
TEST CONDITIONS
(3)
High−K board , No airflow
D pkg
No airflow(4)
P pkg
Ambient air temperature
TYP
MAX
121
UNITS
°C/W
93
High−K board
D pkg
67
°C/W
See Note (4)
P pkg
57
°C/W
D pkg
41
P pkg
55
Junction−to−case thermal resistance
Device power dissipation
MIN
RL= 60Ω, CL = 50 pF,
DE at VCC RE at 0 V,
Input to D a 50% duty cycle square
wave at indicated signaling rate
High−K board, No airflow
No airflow(4)
°C/W
HVD10
(25 Mbps)
198
233
mW
HVD11
(10 Mbps)
141
176
mW
HVD12
(500 kbps)
133
161
mW
D pkg
−40
116
P pkg
−40
123
°C
TJSD Thermal shutdown junction temperature
165
°C
(1) See Application Information section for an explanation of these parameters.
(2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
6
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
375 Ω ±1%
VCC
IOA
A
DE
VOD
0 or 3 V
B
54 Ω ±1%
A
D
VOD
0 or 3 V
IOB
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
B
VI
375 Ω ±1%
VOB VOA
Figure 2. Driver VOD With Common-Mode
Loading Test Circuit
Figure 1. Driver VOD Test Circuit
and Voltage and Current Definitions
VCC
DE
Input
D
27 Ω ± 1%
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
A
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
A
B
50 Ω
VOD
RL = 54 Ω
± 1%
1.5 V
CL = 50 pF ±20%
VI
CL Includes Fixture
and Instrumentation
Capacitance
tPLH
1.5 V
tPHL
90%
VOD
tr
≈2V
90%
0V
10%
tf
0V
10%
≈ −2 V
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
RL = 110 Ω
± 1%
0.5 V
0V
tPZH
VOH
VO
2.3 V
tPHZ
≈0V
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
7
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3V
A
3V
D
VI
≈3V
VI
S1
1.5 V
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
50 Ω
0V
B
tPZL
tPLZ
≈3V
CL = 50 pF ±20%
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VID
VB
VIC
VA + VB
2
A
IO
R
VA
B
VO
IB
Figure 7. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
1.5 V
0V
B
VO
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
1.5 V
VI
1.5 V
0V
tPLH
VO
tPHL
90% 90%
1.5 V
10%
tr
VOH
1.5 V
10% V
OL
tf
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3V
3V
A
DE
0 V or 3 V
R
D
VO
B
RE
Input
Generator
VI
A
1 kΩ ± 1%
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
1.5 V
0V
tPZH(1)
tPHZ
VOH −0.5 V
VOH
D at 3 V
S1 to B
1.5 V
VO
≈0V
tPZL(1)
tPLZ
≈3V
VO
1.5 V
VOL +0.5 V
D at 0 V
S1 to A
VOL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
9
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3V
A
0 V or 1.5 V
R
B
1.5 V or 0 V
RE
Input
Generator
VI
A
1 kΩ ± 1%
VO
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
0V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL(2)
3V
1.5 V
VO
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
A
RE
R
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
B
D
+
_
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
10
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
Function Tables
DRIVER
INPUT
ENABLE
D
DE
A
B
H
L
X
Open
H
H
L
H
H
L
Z
H
L
H
Z
L
OUTPUTS
RECEIVER
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
VID = VA − VB
VID ≤ −0.2 V
−0.2 V < VID < −0.01 V
−0.01 V ≤ VID
X
Open Circuit
Short Circuit
RE
R
L
L
L
H
L
L
L
?
H
Z
H
H
H = high level; L = low level;
? = indeterminate
Z = high impedance;
X = irrelevant;
11
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
100 kΩ
16 V
R3
R1
R3
Input
Input
16 V
R2
R1
100 kΩ
16 V
A and B Outputs
R2
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
SN65HVD10
SN65HVD11
SN65HVD12
12
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
HVD10 OR HVD12
HVD11
RMS SUPPLY CURRENT
vs
SIGNALING RATE
RMS SUPPLY CURRENT
vs
SIGNALING RATE
70
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
I CC − RMS Supply Current − mA
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
50
VCC = 3 V
VCC = 3.3 V
40
30
0
5
10
15
20
25
30
35
TA = 25°C
RE at VCC
DE at VCC
50
VCC = 3 V
VCC = 3.3 V
40
2.5
Signaling Rate − Mbps
Figure 12
5
7.5
Signaling Rate − Mbps
HVD12
HVD10
RMS SUPPLY CURRENT
vs
SIGNALING RATE
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
TA = 25°C
RE at VCC
DE at VCC
300
RL = 54 Ω
CL = 50 pF
250
VCC = 3.6 V
60
VCC = 3.3 V
50
10
Figure 13
I I − Bus Input Current − µ A
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
30
0
40
RL = 54 Ω
CL = 50 pF
VCC = 3 V
40
TA = 25°C
DE at 0 V
200
150
VCC = 0 V
100
50
VCC = 3.3 V
0
−50
−100
−150
30
100
400
700
Signaling Rate − kbps
Figure 14
1000
−200
−7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
Figure 15
13
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
HVD11 OR HVD12
HIGH-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
150
90
I I − Bus Input Current − µ A
70
TA = 25°C
DE at 0 V
60
50
IOH − High-Level Output Current − mA
80
VCC = 0 V
40
30
20
10
0
VCC = 3.3 V
−10
−20
−30
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
100
50
0
−50
−100
−150
−40
−50
−60
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
−200
−4
−2
0
2
4
VOH − Driver High-Level Output Voltage − V
Figure 16
Figure 17
DRIVER DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT CURRENT
vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE
200
160
140
2.5
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
2.4
VOD − Driver Differential Output − V
I OL − Low-Level Output Current − mA
180
120
100
80
60
40
20
−2
0
2
4
6
VOL − Driver Low-Level Output Voltage − V
Figure 18
14
2.3
VCC = 3.3 V
DE at VCC
D at VCC
2.2
2.1
2.0
1.9
1.8
1.7
1.6
0
−20
−4
6
8
1.5
−40
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 19
85
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
−40
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
I O − Driver Output Current − mA
−35
−30
−25
−20
−15
−10
−5
0
0
0.50
1
1.50
2
2.50
3
3.50
VCC − Supply Voltage − V
Figure 20
15
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
RT
Stub
Device
HVD10
HVD11
HVD12
RT
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible.
Figure 21. Typical Application Circuit
Driver Input
Driver Output
Receiver Input
Receiver Output
Figure 22. HVD12 Input and Output Through 2000 Feet of Cable
An example application for the HVD12 is illustrated in
Figure 21. Two HVD12 transceivers are used to
communicate data through a 2000 foot (600 m) length of
Commscope 5524 category 5e+ twisted pair cable. The
16
bus is terminated at each end by a 100-Ω resistor,
matching the cable characteristic impedance. Figure 22
illustrates operation at a signaling rate of 250 kbps.
www.ti.com
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
THERMAL CHARACTERISTICS OF IC
PACKAGES
qJA (Junction-to-Ambient Thermal Resistance) is
defined as the difference in junction temperature to
ambient temperature divided by the operating power.
qJC (Junction-to-Case Thermal Resistance) is defined
as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted
package up against a copper block cold plate to force heat
to flow from die, through the mold compound into the
copper block.
θJA is not a constant and is a strong function of:
D
D
D
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of
packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB
construction, test chamber volume, sensor locations, and
the thermal characteristics of holding fixtures. θJA is often
misused when it is used to calculate junction temperatures
for other installations.
TI uses two test PCBs as defined by JEDEC
specifications. The low-k board gives average in-use
condition thermal performance, and it consists of a single
copper trace layer 25 mm long and 2-oz thick. The high-k
board gives best case in-use condition, and it consists of
two 1-oz buried power planes with a single copper trace
layer 25 mm long and 2-oz thick. A 4% to 50% difference
in θJA can be measured between these two test cards
θJC is a useful thermal characteristic when a heatsink is
applied to package. It is not a useful characteristic to
predict junction temperature because it provides
pessimistic numbers if the case temperature is measured
in a nonstandard system and junction temperatures are
backed out. It can be used with θJB in 1-dimensional
thermal simulation of a package system.
qJB (Junction-to-Board Thermal Resistance) is defined
as the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the
die) when the PCB is clamped in a cold-plate structure. θJB
is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die
and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and
can be used for simple 1-dimensional network analysis of
package system (see Figure 23).
Figure 23. Thermal Resistance
17
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated