TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 D D D D D D D D D D OR DGN PACKAGE (TOP VIEW) Dual Supervisory Circuits for DSP and Processor-Based Systems Power-On Reset Generator with Fixed Delay Time of 200 ms, no External Capacitor Needed Watchdog Timer Retriggers the RESET Output at SENSEn ≥ VIT+ Temperature-Compensated Voltage Reference Maximum Supply Current of 40 µA Supply Voltage Range . . . 2.7 V to 6 V Defined RESET Output from VDD ≥ 1.1 V MSOP-8 and SO-8 Packages Temperature Range . . . – 40°C to 85°C SENSE1 SENSE2 WDI GND 1 8 2 7 3 6 4 5 VDD MR RESET RESET typical applications Figure 1 lists some of the typical applications for the TPS3305 family, and a schematic diagram for a DSP-based system application. This application uses TI part numbers TPS3305–25, TPS7133, TPS71025, and TMS320VC549. 3.3 V TPS7133 VI 5 V – 10 V VO GND GND VI TPS71025 VO • 2.5 V VDD DSP SENSE 1 External Reset Source MR SENSE 2 TPS3305–25 RESET WDI DVDD CVDD TMS320VC549 RESET • • • • • • • Applications using DSPs, Microcontrollers or Microprocessors Industrial Equipment Programmable Controls Automotive Systems Portable/Battery Powered Equipment Intelligent Instruments Wireless Communication Systems Notebook/Desktop Computers XF GND GND Figure 1. Applications Using the TPS3305 Family description The TPS3305 family is a series of micropower supply voltage supervisors designed for circuit initialization, primarily in DSP and processor-based systems, which require two supply voltages. The product spectrum of the TPS3305 is designed for monitoring two independent supply voltages of 3.3 V/1.8 V, 3.3 V/2.5 V or 3.3 V /5 V. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 description (continued) The various supply voltage supervisors are designed to monitor the nominal supply voltage, as shown in the following supply voltage monitoring table. SUPPLY VOLTAGE MONITORING DEVICE NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) SENSE1 SENSE2 SENSE1 SENSE2 TPS3305-18 3.3 V 1.8 V 2.93 V 1.68 V TPS3305-25 3.3 V 2.5 V 2.93 V 2.25 V TPS3305-33 5V 3.3 V 4.55 V 2.93 V During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remains below the threshold voltage VIT+. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td typ = 200 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage VIT+. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT–, the RESET output becomes active (low) again. The TPS3305-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, tt(out) = 1.6 s, RESET becomes active for the time period td . This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3305-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to become active. In addition to the active-low RESET output, the TPS3305-xx family includes an active-high RESET output. The TPS3305-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages. The TPS3305-xx family is characterized for operation over a temperature range of – 40°C to 85°C. AVAILABLE OPTIONS PACKAGED DEVICES TA –40_C to 85_C SMALL OUTLINE (D) PowerPAD µ-SMALL OUTLINE (DGN) MARKING DGN PACKAGE CHIP FORM (Y) TPS3305-18D TPS3305-18DGN TIAAM TPS3305-18Y TPS3305-25D TPS3305-25DGN TIAAN TPS3305-25Y TPS3305-33D TPS3305-33DGN TIAAO TPS3305-33Y PowerPAD is a trademark of Texas Instruments Incorporated. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 description (continued) FUNCTION/TRUTH TABLES MR SENSE1>VIT1 X† SENSE2>VIT2 X† RESET RESET L L H H 0 0 L H H 0 0 L H H 0 1 L H H 0 1 L H H 1 0 L H H 1 0 L H H 1 1 L H H 1 1 H L † X = Don’t care functional block diagram VDD TPS3305 14 kΩ MR R1 + _ SENSE 1 R2 RESET R3 SENSE 2 R4 RESET Logic + Timer + _ RESET GND Reference Voltage of 1.25 V WDI Transition Detection Oscillator Watchdog Logic + Timer 40 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 timing diagram SENSEn V(nom) VIT– t MR 1 0 t tt(out) WDI 1 t 0 RESET 1 t 0 td td td td RESET Because of WDI RESET Because of SENSE Below VIT– RESET Because of MR RESET Because of SENSE Below VIT– RESET Because of SENSE Below VIT– 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 TPS3305Y chip information These chips, when properly assembled, display characteristics similar to those of the TPS3305. Thermal compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. (4) (3) (2) (1) (1) (8) (2) TPS3305Y (7) (3) (6) (4) (5) 48 CHIP THICKNESS: 10 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS (5) (7) (6) (8) 56 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION GND 4 Ground MR 7 I Manual reset RESET 5 O Active-low reset output RESET 6 O Active-high reset output SENSE1 1 I Sense voltage input 1 SENSE2 2 I Sense voltage input 2 WDI 3 I Watchdog timer input VDD 8 Supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGN 2.14 mW 17.1 mW/°C 1.37 mW 1.11 mW D 725 mW 5.8 mW/°C 464 mW 377 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD 2.7 Input voltage at MR and WDI, VI 0 Input voltage at SENSE1 and SENSE2, VI 0 High-level input voltage at MR and WDI, VIH UNIT 6 V VDD+0.3 (VDD+0.3)VIT/1.25V V 0.7xVDD Low-level input voltage at MR and WDI, VIL Input transition rise and fall rate at MR, ∆t/∆V Operating free-air temperature range, TA 6 MAX –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.3×VDD 50 V ns/V 85 °C TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage Power-up reset voltage (see Note 2) VSENSE1, VSENSE2 VIT IT– IH(AV) Hysteresis at VSENSEn input Average high-level input current WDI IL(AV) IH IL IDD Ci MIN VDD– 0.2V VDD– 0.4V Average low-level input current High level input current High-level Low-level input current TYP MAX V 0.2 VDD ≥ 1.1 V, 0.4 0.4 VDD = 2.7 V to 6 V, TA =–40°C to 85°C V 0.4 IOL = 20 µA VDD = 2.7 V to 6 V, TA = 0°C to 85°C UNIT VDD– 0.4V VDD = 2.7 V to 6 V, IOL = 20 µA VDD = 3.3 V, IOL = 2 mA VDD = 6 V, IOL = 3 mA Negative-going g g g input threshold voltage g (see Note 3) VSENSE1, VSENSE2 Vh hys TEST CONDITIONS VDD = 2.7 V to 6 V, IOH = –20 µA VDD = 3.3 V, IOH = –2 mA VDD = 6 V, IOH = –3 mA 1.64 1.68 1.72 2.20 2.25 2.30 2.86 2.93 3 4.46 4.55 4.64 1.64 1.68 1.73 2.20 2.25 2.32 2.86 2.93 3.02 4.46 4.55 4.67 VIT– = 1.68 V VIT– = 2.25 V 15 VIT– = 2.93 V VIT– = 4.55 V 30 20 V V V mV 40 WDI = VDD = 6 V Time average (dc = 88%) 100 150 WDI = 0 V, VDD = 6 V, Time average (dc = 12%) –15 –20 µA WDI WDI = VDD = 6 V, 120 170 MR MR = 0.7 × VDD, –130 –180 5 8 SENSE1 VDD = 6 V VSENSE1 = VDD = 6 V SENSE2 VSENSE2 = VDD = 6 V WDI WDI = 0 V, MR MR = 0V, SENSEn VSENSE1,2 = 0 V VDD, = 6 V VDD = 6 V Supply current –1 6 9 –120 –170 –430 –600 µA µA 1 40 µA Input capacitance VI = 0 V to VDD 10 pF NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 timing requirements at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER SENSEn tw Pulse width MR WDI TEST CONDITIONS VSENSEnL = VIT– –0.2 V, VSENSEnH = VIT+ +0.2 V VIH = 0.7 0 7 × VDD, VIL = 0 0.3 3 × VDD MIN TYP MAX UNIT 6 µs 100 ns 100 ns switching characteristics at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tt(out) Watchdog time out VI(SENSEn) ≥ VIT+ + 0.2 V, MR ≥ 0.7 × VDD, See timing diagram 1.1 1.6 2.3 s td Delay time VI(SENSEn) ≥ VIT+ + 0.2 V, MR ≥ 0.7 × VDD, See timing diagram 140 200 280 ms tPHL Propagation (delay) time, high-to-low level output MR to RESET, MR to RESET Propagation (delay) time, low-to-high level output MR to RESET, MR to RESET 200 500 ns tPLH tPHL Propagation (delay) time, high-to-low level output SENSEn to RESET, SENSEn to RESET Propagation (delay) time, low-to-high level output SENSEn to RESET, SENSEn to RESET 1 5 µs tPLH 8 VI(SENSEn) ≥ VIT+ +0.2 V, VIH = 0.7 × VDD, VIL = 0.3 × VDD VIH = VIT+ +0.2 V, VIL = VIT IT– –0.2 V, MR ≥ 0.7 × VDD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD SUPPLY CURRENT vs SUPPLY VOLTAGE 1.005 18 VDD = 6 V MR = Open 1.004 16 14 1.003 12 I DD – Supply Current – µ A Normalized Input Threshold Voltage – VIT(TA), VIT(25 °C) TYPICAL CHARACTERISTICS 1.002 1.001 1 0.999 0.998 0.997 TPS3305–33 10 8 6 4 2 0 –2 –4 SENSEn = VDD MR = Open TA = 25°C –6 0.996 0.995 –40 –15 10 35 60 TA – Free-Air Temperature – °C –8 –10 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 85 VDD – Supply Voltage – V Figure 2 Figure 3 INPUT CURRENT vs INPUT VOLTAGE AT MR MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE 100 tw – Minimum Pulse Duration at Vsense – µ s 0 10 VDD = 6 V TA = 25°C I I – Input Current – µ A –100 –200 –300 –400 –500 –600 –700 –800 –900 –1 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VI – Input Voltage at MR – V VDD = 6 V MR = Open 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 1000 SENSE – Threshold Overdrive – mV Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.5 6.5 VDD = 6 V MR = Open 6 VOH – High-Level Output Voltage – V VOH – High-Level Output Voltage – V VDD = 2 V MR = Open 2 1.5 –40°C 1 85°C 0.5 5.5 5 4.5 4 –40°C 3.5 3 85°C 2.5 2 1.5 1 0.5 0 0 0 –0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5 –5.5 –6 IOH – High-Level Output Current – mA 0 –5 Figure 6 Figure 7 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.5 6.5 VDD = 2 V MR = Open 2 1.5 1 VDD = 6 V MR = Open 6 VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V –10 –15 –20 –25 –30 –35 –40 –45 –50 IOH – High-Level Output Current – mA 85°C 0.5 –40°C 5.5 5 4.5 4 3.5 3 85°C 2.5 2 1.5 –40°C 1 0.5 0 0 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 IOL – Low-Level Output Current – mA 1 6 0 0 5 Figure 8 10 10 15 20 25 30 35 40 45 50 55 60 IOL – Low-Level Output Current – mA Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS3305-18, TPS3305-25, TPS3305-33 DUAL PROCESSOR SUPERVISORS SLVS198 – DECEMBER 1998 MECHANICAL DATA DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note D) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-187 PowerPAD is a trademark of Texas Instruments Incorporated. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated