SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 D D D D D D D Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485, and ITU Recommendations V.10 and V.11. Designed to Operate With Pulse Durations as Short as 20 ns Designed for Multipoint Bus Transmission on Long Bus Lines in Noisy Environments Input Sensitivity . . . ± 200 mV Low-Power Consumption . . . 20 mA Max Open-Circuit Fail-Safe Design Pin Compatible With SN75173 and AM26LS32 D OR N PACKAGE (TOP VIEW) 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B description The SN65LBC173 and SN75LBC173 are monolithic quadruple differential line receivers with 3-state outputs. Both are designed to meet the requirements of the ANSI standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485, and ITU Recommendations V.10 and V.11. The devices are optimized for balanced multipoint bus transmission at data rates up to and exceeding 10 million bits per second. The four receivers share two ORed enable inputs, one active when high, the other active when low. Each receiver features high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ± 200 mV over a common-mode input voltage range of 12 V to –7 V. Fail-safe design ensures that if the inputs are open circuited, the output is always high. Both devices are designed using the Texas Instruments proprietary LinBiCMOS technology that provides low power consumption, high switching speeds, and robustness. These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line drivers. The SN65LBC173 and SN75LBC173 are available in the 16-pin DIP (N) and SOIC (D) packages. The SN65LBC173 is characterized over the industrial temperature range of – 40°C to 85°C. The SN75LBC173 is characterized for operation over the commercial temperature range of 0°C to 70°C. FUNCTION TABLE (each receiver) ENABLES G G OUTPUT Y VID ≥ 0.2 V H X X L H H – 0.2 V < VID < 0.2 V H X X L ? ? VID ≤ – 0.2 V H X X L L L X L H Z Open Circuit H X X L H H DIFFERENTIAL INPUTS A–B H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 logic symbol† G G 1A 1B 2A 2B 3A 3B 4A 4B 4 logic diagram (positive logic) ≥1 G 12 G 2 3 1 1A 1Y 1B 6 5 7 2Y 2A 10 11 9 14 13 15 2B 3Y 3A 4Y 3B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4A 4B 4 12 2 1 6 7 10 9 14 15 3 5 11 13 1Y 2Y 3Y 4Y schematics of inputs and outputs EQUIVALENT OF A AND B INPUTS TYPICAL OF ALL OUTPUTS VCC VCC 100 kΩ A Only Receiver 18 kΩ Input Y Output 12 kΩ 1 kΩ 2 VCC 3 kΩ Input 100 kΩ B Only TYPICAL OF G AND G INPUTS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage, VI (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Voltage range at Y, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.5 V Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: SN65LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C SN75LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input. DISSIPATION RATING TABLE PACKAGE D N TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 8.7 mW/°C 9.2 mW/°C 708 mW 736 mW 578 mW 598 mW 1100 mW 1150 mW recommended operating conditions Supply voltage, VCC Common-mode input voltage, VIC MIN NOM MAX UNIT 4.75 5 5.25 V 12 V ±6 V –7 Differential input voltage, VID High-level input voltage, VIH Low-level input voltage, VIL 2 G inputs High-level output current, IOH Low-level output current, IOL free air temperature, temperature TA Operating free-air V 0.8 V –8 mA 16 mA SN65LBC173 – 40 85 SN75LBC173 0 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 °C 3 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT + VIT – Positive-going input threshold voltage Vhys VIK Hysteresis voltage ( VIT + – VIT – ) VOH VOL High-level output voltage IOZ High-impedance-state output current II Negative-going input threshold voltage Enable input clamp voltage Low-level output voltage Bus input current A or B inputs IIH IIL High-level input current IOS Short-circuit output current ICC Supply current Low-level input current MIN IO = – 8 mA IO = 16 mA TYP† MAX 0.2 – 0.2 VID = – 200 mV, VO = 0 V to VCC – 0.9 IOH = – 8 mA IOL = 16 mA 3.5 V V 45 II = – 18 mA VID = 200 mV, UNIT mV – 1.5 4.5 0.3 V V 0.5 V ± 20 µA VIH = 12 V, VIH = 12 V, VCC = 5 V, Other inputs at 0 V 0.7 1 mA VCC = 0 V, Other inputs at 0 V 0.8 1 mA VIH = – 7 V, VIH = – 7 V, VCC = 5 V, Other inputs at 0 V – 0.5 – 0.8 mA VCC = 0 V, Other inputs at 0 V – 0.4 – 0.8 mA ± 20 µA VIH = 5 V VIL = 0 V VO = 0 Outputs enabled, – 80 IO = 0, VID = 5 V – 20 µA – 120 mA 11 20 0.9 1.4 MIN TYP MAX 11 22 30 ns 11 22 30 ns Outputs disabled mA † All typical values are at VCC = 5 V and TA = 25°C. switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C PARAMETER TEST CONDITIONS UNIT tPHL tPLH Propagation delay time, high- to low-level output tPZH tPZL Output enable time to high level See Figure 2 17 30 ns Output enable time to low level See Figure 3 18 30 ns tPHZ tPLZ Output disable time from high level See Figure 2 35 45 ns Output disable time from low level See Figure 3 25 40 ns tsk(p) tt Pulse skew (|tPHL – tPLH|) See Figure 2 0.5 6 ns Transition time See Figure 1 5 10 ns 4 Propagation delay time, low- to high-level output VID = – 1 1.5 5 V to 1 1.5 5 V, V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 See Figure 1 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION Generator (see Note A) 1.5 V 50 Ω Input Output 0V 0V – 1.5 V CL = 15 pF (see Note B) tPLH tPHL VOH 90% Output 1.3 V 10% 1.3 V VOL tt 2V tt VOLTAGE WAVEFORMS TEST CIRCUIT Figure 1. tpd and tt Test Circuit and Voltage Waveforms VCC Output 2 kΩ 1.5 V S1 Input CL = 15 pF (see Note B) 5 kΩ Generator (see Note A) 3V 1.3 V 1.3 V 0V tPHZ tPZH See Note C Output S1 Open 2V 0.5 V 1.3 V 0V VOH S1 Closed ≈ 1.4 V VOLTAGE WAVEFORMS 50 Ω (see Note D) TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. All diodes are 1N916 or equivalent. D. To test the active-low enable G, ground G and apply an inverted input waveform to G. Figure 2. tPHZ and tPZH Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC Output 2 kΩ 1.5 V 3V Input CL = 15 pF (see Note B) 1.3 V 1.3 V 0V 5 kΩ See Note C tPZL tPLZ S2 Open 2V Output Generator (see Note A) S2 Closed ≈ 1.4 V 1.3 V VOL S2 0.5 V 50 Ω (see Note D) VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. All diodes are 1N916 or equivalent. D. To test the active-low enable G, ground G and apply an inverted input waveform to G. Figure 3. tPZL and tPLZ Test Circuit and Voltage Waveforms TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 5.5 4.5 VIC = 12 V VIC = 0 V VIC = – 7 V 2 VIC = 0 V 2.5 VIC = 12 V 3 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 VID – Differential Input Voltage – mV VOH – High-Level Output Voltage – V 3.5 VIC = – 7 V VO – Output Voltage – V 5 VCC = 5 V TA = 25°C 4 VCC = 5.25 V 4.5 4 VCC = 5 V 3.5 VCC = 4.75 V 3 2.5 2 1.5 1 0.5 VID = 0.2 V TA = 25°C 0 0 – 4 – 8 – 12 – 16 – 20 – 24 – 28 – 32 – 36 – 40 IOH – High-Level Output Current – mA Figure 5 Figure 4 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs FREQUENCY LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 14 660 VOL – Low-Level Output Voltage – mV 600 540 I CC – Average Supply Current – mA TA = 25°C VCC = 5 V VID = 200 mV 480 420 360 300 240 180 120 TA = 25°C VCC = 5 V 12 10 8 6 4 2 60 0 10 K 0 0 3 6 9 12 15 18 21 24 27 30 100 K 10 M 2M 100 M f – Frequency – Hz IOL – Low-Level Output Current – mA Figure 6 Figure 7 BUS INPUT CURRENT vs INPUT VOLTAGE (COMPLEMENTARY INPUT AT 0 V) 0.8 I I – Input Current – mA 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ –1 –8 24.5 TA = 25°C VCC = 5 V Propagation Delay Time – ns 1 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE VCC = 5 V CL = 15 pF VIO = ± 1.5 V 24 tPHL 23.5 23 tPLH 22.5 The shaded region of this graph represents more than 1 unit load per RS-485. –6 –4 –2 0 2 4 6 8 10 12 22 – 40 – 20 0 20 40 60 80 100 TA – Free-Air Temperature – °C VI – Input Voltage – V Figure 9 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 8 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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