DB LECTRO Inc. SPECIFICATION CUSTOMER Ver:0 : MODULE NO.: WP2002A-Y-JCS APPROVED BY: ( FOR CUSTOMER USE ONLY ) SALES BY APPROVED BY CHECKED BY PREPARED BY ISSUED DATE: 第 1 頁，共 18 頁 www.dblectro.com Version modify record NO. Version Date Modify contents 第 2 頁，共 18 頁 Page Remarks www.dblectro.com Contents 1.Module Classification Information 2.Precautions in use of LCD Modules 3.General Specification 4.Absolute Maximum Ratings 5.Electrical Characteristics 6.Optical Characteristics 7.Interface Pin Function 8.Contour Drawing & Block Diagram 9.Function Description 10.Character Generator ROM Pattern 11.Instruction Table 12.Timing Characteristics 13.Initializing of LCM 14.Quality Assurance 15.Reliability 第 3 頁，共 18 頁 www.dblectro.com 1.Module Classification Information WP 2002 A－Y－ cd c d e f g 6 ○ e f JCS g 6 ○ Brand：DB LECTRO Inc. Display Type：H→Character Type, G→Graphic Type , P→PLED Display Font：Character 16 words, 2Lines. Model serials no. Backlight Type： Y→Yellow Green Special Code JCS: English and Japanese standard font 2.Precautions in use of PLED Modules (1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don’t make extra holes on the printed circuit board, modify its shape or change the components of PLED module. (3)Don’t disassemble the PLEDM. (4)Don’t operate it above the absolute maximum rating. (5)Don’t drop, bend or twist PLEDM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment. 3.General Specification Item Dimension Unit 20 characters x 2 Lines － 116.0 x 37.0 x 9.5(MAX) mm View area 75.0 x 16.0 mm Active area 71.37 x 11.87 mm Dot size 0.57 x 0.67 mm Dot pitch 0.6 x 0.7 mm Character size 2.97 x 5.57 mm Character pitch 3.60 x 6.30 mm Number of Characters Module dimension LCD type PLED , Green Duty 1/16 第 4 頁，共 18 頁 www.dblectro.com 4.Absolute Maximum Ratings Item Symbol Min Typ Max Unit Operating Temperature TOP -20 25 +50 ℃ Storage Temperature TST -30 － +70 ℃ Input Voltage VI -0.3 － VDD V Supply Voltage For Logic VDD-VSS -0.3 － 7 V Supply Voltage For LCD VBT- VSS -0.3 － 5.0 V 5.Electrical Characteristics Item Symbol Condition Min Typ Max Unit Supply Voltage For Logic VDD-VSS － 4.5 5.0 5.5 V Supply Voltage For LCD VBT Ta=25℃ 2.0 2.5 5.0 V Input High Volt. VIH － 0.7 VDD － VDD V Input Low Volt. VIL － -0.3 － 0.55 V Output High Volt. VOH － 2.4 － － V Output Low Volt. VOL － － － 0.4 V Supply Current IDD VDD=5V － 0.35 0.6 mA Min Typ Max Unit 6.Optical Characteristics Item Symbol Condition (V)θ 80 deg (H)φ 80 deg View Angle Contrast Ratio － T rise － 10 us T fall － 10 us With polarizer 40 nits 第 5 頁，共 18 頁 100 － 100 lux Response Time Brightness － CR www.dblectro.com 7.Interface Pin Function Pin No. Symbol Level Description 1 VSS 0V Ground 2 VDD 5.0V 3 ※VBT 4 RS H/L H: DATA, L: Instruction code 5 R/W H/L H: Read(MPU→Module) L: Write(MPU→Module) 6 E H,H→L 7 DB0 H/L Data bit 0 8 DB1 H/L Data bit 1 9 DB2 H/L Data bit 2 10 DB3 H/L Data bit 3 11 DB4 H/L Data bit 4 12 DB5 H/L Data bit 5 13 DB6 H/L Data bit 6 14 DB7 H/L Data bit 7 15 NC － 16 NC － Supply Voltage for logic (Variable) Operating voltage for PLED Brightness adjhstment Chip enable signal ※Brightness Control VBT Brightness(nits) Power consumption(measured with random texts) 2.5V 20(typical) 50mW 3.0V 45(typical) 63mW Note:1.When random texts pattern is running,averagely,at any instance,about 1/4 of pixels will be on. 2.If VBT is not operated within 2V and 3V,non-uniformity display may occur. 3.You have to use the saving mode by VBT 2.5V in order to make long life. 第 6 頁，共 18 頁 www.dblectro.com 8.Contour Drawing &Block Diagram 116 93 75.0(VA) 71.37(AA) 6.5 4 9.5 MAX 4.9 15 2 1 18.5 16 4 29 37.0 0.5 31.2 16(VA) 11.87(AA) 4 2.9 4 8.5 59.0 4.0 4- 3.5 PTH 4- 5.5 PAD 108 2.97 2.5 1 PIN DETAIL 80 series or 68 series RS R/W E DB0~DB7 Vdd Vbt Vss DOT SIZE SCALE 5/1 Com1~16 Controller/Com Driver 20X2 LCD Bias and Power Circuit MPU Vss Vdd Vo RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 NC NC 5.57 0.7 0.67 2 0.73 (P2.54*7) 17.78 8.34 15 0.63 0.6 0.57 2.54 16 1.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D Seg Driver M CL1 CL2 Vdd,Vss,V1~V5 Character located 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 第 7 頁，共 18 頁 ~ 20 13 53 www.dblectro.com 9.Function Description The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected. RS R/W Operation 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB7) 1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) 1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR) Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. next instruction must be written after ensuring that the busy flag is 0. The Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM addresses and positions on the liquid crystal display. High bits Low bits Example: DDRAM addresses 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 第 8 頁，共 18 頁 1 0 0 1 1 1 0 www.dblectro.com Display position DDRAM address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 2-Line by 16-Character Display Character Generator ROM (CGROM) The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns can be written, and for 5×10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM. 第 9 頁，共 18 頁 www.dblectro.com Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1. F o r 5 * 8 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 H ig h 0 0 0 0 0 0 0 0 0 2 1 0 Low 0 0 0 * 0 * 0 * 1 0 0 1 C h a ra c te r P a tte rn s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 2 1 0 7 Low 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * H ig h 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 * 6 5 H ig h * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 4 3 2 1 0 Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a ra c te r p a tte rn ( 1 ) 0 0 0 0 C u rs o r p a tte rn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a ra c te r p a tte rn ( 2 ) C u rs o r p a tte rn * F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 H ig h 0 0 0 3 2 1 0 Low 0 * 0 0 C h a ra c te r P a tte rn s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 H ig h 0 0 2 1 0 7 Low 0 6 5 4 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H ig h 2 Low 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 * * * * * * * * * * * * * * * * * * * * * * * 0 * 0 * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 * * * * * * * * C h a ra c te r p a tte rn C u rs o r p a tte rn : " H ig h " 第 10 頁，共 18 頁 www.dblectro.com 10.Character Generator ROM Pattern Table.2 Upper 4 bit Lower 4 bit LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH LLLL CG RAM (1) LLLH (2) LLHL (3) LLHH (4) LHLL (5) LHLH (6) LHHL (7) LHHH (8) HLLL (1) HLLH (2) HLHL (3) HLHH (4) HHLL (5) HHLH (6) HHHL (7) HHHH (8) 第 11 頁，共 18 頁 www.dblectro.com 11.Instruction Table Instruction Code Instruction Execution time Description (fosc=270Khz) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Write “00H” to DDRAM and set 1.52ms DDRAM address to “00H” from AC Set DDRAM address to “00H” from AC Return Home 0 0 0 0 0 0 0 0 1 － and return cursor to its original position if shifted. The contents of DDRAM are 1.52ms not changed. Assign cursor moving direction and Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH enable the shift of entire display. I/D=1:Increment；0: Decrement 37μs SH=1:Display shift on Set display (D), cursor (C), and blinking Display ON/OFF Control of cursor (B) on/off control bit. 0 0 0 0 0 0 1 D C B 37μs D=1:Display on C=1:Cursor display on B=1:Cursor blink on Set cursor moving and display shift Cursor or Display Shift control bit, and the direction, without 0 0 0 0 0 1 S/C R/L － － changing of DDRAM data. 37μs S/C=1:Shift display；0:Move cursor R/L=1:Shift right；0:Shift leftf Set interface data length (DL) DL=1:8-bit；0:4-bit Function Set 0 0 0 0 1 DL N F － － Set numbers of display lines(N) N=1:Dual line；0:Single line 37μs Set display font type (F) F=1:5x10 dots；0:5x8dots Set CGRAM Address Set DDRAM Address 0 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 37μs AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 37μs 1 Whether during internal operation or not Read Busy Flag and Address can be known by reading BF. The 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 contents of address counter can also be read. 0μs BF=1:Internal operation BF=0:Ready for instruction Write Data to RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM). 37μs 37μs ＊ ”－”：don’t care 第 12 頁，共 18 頁 www.dblectro.com 12.Timing Characteristics VIH1 RS VIH1 VIL1 VIL1 tAS R/W tAH VIL1 VIL1 PWEH VIH1 E tAH tEf VIH1 VIL1 VIL1 tEr VIL1 tDSW tH VIH1 DB0 to DB7 VIH1 Valid data VIL1 VIL1 tcycE 12.1 Write Operation Ta=25℃, VDD=5.0± 0.5V Item Symbol Min Typ Max Unit tcycE 500 － － ns Enable pulse width (high level) PWEH 230 － － ns Enable rise/fall time tEr,tEf － － 20 ns Address set-up time (RS, R/W to E) tAS 40 － － ns Address hold time tAH 10 － － ns Data set-up time tDSW 80 － － ns tH 10 － － ns Enable cycle time Data hold time 第 13 頁，共 18 頁 www.dblectro.com 12.2 Read Operation VIH1 RS VIH1 VIL1 VIL1 tAS tAH VIH1 R/W VIH1 PWEH VIH1 E VIH1 VIL1 tEr tAH tEf VIL1 t VOH1 DB0 to DB7 VIL1 tDHR DDR VOL1* VOH1 Valid data *VOL1 tcycE NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation. Ta=25℃, VDD=5.0± 0.5V Item Symbol Min Typ Max Unit tcycE 500 － － ns Enable pulse width (high level) PWEH 230 － － ns Enable rise/fall time tEr,tEf － － 20 ns Address set-up time (RS, R/W to E) tAS 40 － － ns Address hold time tAH 10 － － ns Data delay time tDDR － － 160 ns Data hold time tDHR 5 － － ns Enable cycle time 第 14 頁，共 18 頁 www.dblectro.com 13.Initializing of LCM Power on Wait for more than 15 ms after VCC rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 0 0 1 1 * * * * Wait for more than 4.1 ms BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 1 0 0 1 * * * * Wait for more than 100 µs BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 1 * * * * 0 0 1 BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. RS R/W DB7 0 0 0 0 0 0 0 0 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 DB4 DB3 DB2 N F 1 0 1 0 0 0 0 0 0 1 DB1 DB0 * * 0 0 0 1 I/D S Function set ( Interface is 8 bits long. Specify the number of display lines and font. ) The number of display lines and character font can not be changed after this point. Display off Display clear Entry mode set Initialization ends 第 15 頁，共 18 頁 8-Bit Ineterface www.dblectro.com Power on Wait for more than 15 ms after VCC rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) Wait for more than 4.1 ms BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) Wait for more than 100 µs BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) RS R/W DB7 DB6 DB5 DB4 0 0 1 0 0 0 0 0 0 0 1 0 0 0 N F * * 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 I/D S 0 0 0 BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. Function set ( Set interface to be 4 bits long. ) Interface is 8 bits in length. Function set ( Interface is 4 bits long. Specify the number of display lines and character font. ) The number of display lines and character font can not be changed after this point. Display off Display clear Entry mode set Initialization ends 4-Bit Ineterface 第 16 頁，共 18 頁 www.dblectro.com 14.Quality Assurance Screen Cosmetic Criteria Item Defect 1 Spots 2 Bubbles in Polarize 3 Scratch 4 Allowable Density 5 Coloration Judgment Criterion A)Clear Size: d mm Acceptable Qty in active area d ≦0.1 Disregard 0.1<d≦0.2 6 0.2<d≦0.3 2 0.3<d 0 Note: Including pin holes and defective dots which must be within one pixel size. B)Unclear Size: d mm Acceptable Qty in active area d ≦0.2 Disregard 0.2<d≦0.5 6 0.5<d≦0.7 2 0.7<d 0 Size: d mm Acceptable Qty in active area d≦0.3 Disregard 0.3<d≦1.0 3 1.0<d≦1.5 1 1.5<d 0 In accordance with spots cosmetic criteria. When the light reflects on the panel surface, the scratches are not to be remarkable. Above defects should be separated more than 30mm each other. Not to be noticeable coloration in the viewing area of the LCD panels. Back-light type should be judged with back-light on state only. 第 17 頁，共 18 頁 Partition Minor Minor Minor Minor Minor www.dblectro.com 15.Reliability Content of Reliability Test Environmental Test Test Item High Temperature storage Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature/ Humidity Storage High Temperature/ Humidity Operation Temperature Cycle Content of Test Test Condition Applicable Standard Endurance test applying the high storage temperature for a long time. 70℃ 200hrs —— Endurance test applying the high storage temperature for a long time. -30℃ 200hrs —— Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. 50℃ 200hrs —— Endurance test applying the electric stress under low temperature for a long time. -20℃ 200hrs —— Endurance test applying the high 70℃,90%RH temperature and high humidity storage for a 96hrs long time. Endurance test applying the electric stress (Voltage & Current) and temperature / humidity stress to the element for a long time. Endurance test applying the low and high temperature cycle. -20℃ 25℃ 50℃ 30min 5min 1 cycle —— 50℃,90%RH 96hrs —— -20℃/50℃ 10 cycles —— 30min Mechanical Test Vibration test Endurance test applying the vibration during transportation and using. Shock test Constructional and mechanical endurance test applying the shock during transportation. Atmospheric pressure test Endurance test applying the atmospheric pressure during transportation by air. 10~22Hz→1.5mmp-p 22~500Hz→1.5G Total 0.5hrs 50G Half sign wave 11 msedc 3 times of each direction 115mbar 40hrs —— —— —— Others VS=800V,RS=1.5kΩ Static electricity Endurance test applying the electric stress to CS=100pF test the terminal. 1 time —— ***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25℃ 第 18 頁，共 18 頁 www.dblectro.com