TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 600 mA/1.25 MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER FEATURES • • • • • • • • • • • • • • • DESCRIPTION Up to 95% Conversion Efficiency Typical Quiescent Current: 18 µA Load Current: 600 mA Operating Input Voltage Range: 2.5 V to 6.0 V Switching Frequency: 1.25 MHz Adjustable and Fixed Output Voltage Power Save Mode Operation at Light load Currents Active-Low MODE pin on TPS62021 100% Duty Cycle for Lowest Dropout Internal Softstart Dynamic Output Voltage Positioning Thermal Shutdown Short-Circuit Protection 10 Pin MSOP PowerPad™ Package 10 Pin QFN 3 X 3 mm Package The TPS62020 is a high efficiency synchronous step-down dc-dc converter optimized for battery powered portable applications. This device is ideal for portable applications powered by a single Li-Ion battery cell or by 3-cell NiMH/NiCd batteries. With an output voltage range from 6.0 V down to 0.7 V, the device supports low voltage DSPs and processors in PDAs, pocket PCs, as well as notebooks and subnotebook computers. The TPS62020 operates at a fixed switching frequency of 1.25 MHz and enters the power save mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. The difference between the TPS62020 and the TPS62021 is the logic level of the MODE pin. The TPS62021 has an active-low MODE pin. The TPS62020 supports up to 600-mA load current. APPLICATIONS • • • • • • PDA, Pocket PC and Smart Phones USB Powered Modems CPUs and DSPs PC Cards and Notebooks xDSL Applications Standard 5-V to 3.3-V Conversion Typical Application Circuit (600-mA Output Current) EFFICIENCY vs LOAD CURRENT C3 10 µF TPS62020 2 SW VIN 3 SW VIN 1 EN FB 6 MODE PGND 4 GND PGND 8 7 L1 10 µH 5 10 9 VO 0.7 V to VI / 600 mA 100 VO = 1.8 V 95 VI = 2.7 V 90 R1 C1 R2 C2 C4 10 µF 85 Efficiency − % VI 2.5 V to 6 V VI = 3.6 V 80 VI = 5 V 75 70 Mode = Low 65 60 55 VI = 3.6 V Mode = High 50 45 40 0 0.01 0.10 1 10 100 1000 IL − Load Current − mA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION MODE PIN LOGIC LEVEL TA -40°C to 85°C (1) (2) PACKAGE PACKAGE MARKING MSOP (1) QFN (2) MSOP QFN MODE TPS62020DGQ TPS62020DRC BBK BBJ MODE TPS62021DGQ TPS62021DRC ASH ASJ The DGQ package is available in tape and reel. Add R suffix (DGQR) to order quantities of 2500 parts per reel. The DRC package is available in tape and reel. Add R suffix (DRCR) to order quantities of 3000 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNITS Supply voltage VIN (2) -0.3 V to 7 V Voltages on EN, MODE, FB, SW (2) -0.3 V to VCC +0.3 V Continuous power dissipation See Dissipation Rating Table Operating junction temperature range -40°C to 150°C Storage temperature range -65°C to 150°C Lead temperature (soldering, 10 sec) (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. PACKAGE DISSIPATION RATINGS RθJA (1) TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING MSOP 60°C/W 1.67 W 917 mW 667 mW QFN 48.7°C/W 2.05 W 1.13 W 821 mW PACKAGE (1) The thermal resistance, RθJA is based on a soldered PowerPAD using thermal vias. RECOMMENDED OPERATING CONDITIONS MIN VI Supply voltage 2.5 VO Output voltage range for adjustable output voltage version 0.7 IO Output current L Inductor (1) TYP MAX 6.0 VI 600 3.3 capacitor (1) UNIT V V mA 10 µH 10 µF CI Input CO Output capacitor (1) TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C (1) 2 Refer to application section for further information 10 µF TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS VI = 3.6 V, VO = 1.8 V, IO = 600 mA, EN = VIN, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range I(Q) Operating quiescent current IO = 0 mA, device is not switching 2.5 ISD Shutdown supply current EN = GND VUVLO Under-voltage lockout threshold 18 6.0 V 35 µA 1 µA 2.3 V 0.1 1.5 ENABLE AND MODE VEN EN high level input voltage VEN EN low level input voltage IEN EN input bias current V(MODE) MODE high level input voltage V(MODE) MODE low level input voltage I(MODE) MODE input bias current 1.4 EN = GND or VIN V 0.01 0.4 V 1.0 µA 1.4 MODE = GND or VIN V 0.01 0.4 V 1.0 µA POWER SWITCH P-channel MOSFET on-resistance VI = VGS = 3.6 V 115 210 mΩ P-channel MOSFET on-resistance VI = VGS = 2.5 V 145 270 mΩ P-channel leakage current VDS = 6.0 V 1 µA N-channel MOSFET on-resistance VI = VGS = 3.6 V 85 200 mΩ N-channel MOSFET on-resistance VI = VGS = 2.5 V 115 280 mΩ IIkg(N) N-channel leakage current VDS = 6.0 V 1 µA IL P-channel current limit 2.5 V < VI < 6.0 V rDS(ON) Ilkg(P) rDS(ON) 0.9 1.1 Thermal shutdown 1.3 A °C 150 OSCILLATOR fS VFB= 0.5 V Oscillator frequency 1 1.25 VFB = 0 V 1.5 625 MHz kHz OUTPUT VO Adjustable output voltage range Vref Reference voltage VFB (1) VIN 0.5 VI = 2.5 V to 6.0 V; IO = 0 mA Feedback voltage IIkg(SW) f 0.7 0% VI = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 600 mA V 3% -3% V 3% V V Line regulation (1) VI = VO + 0.5 V (min 2.5 V) to 6.0 V, IO = 10 mA 0 %/V Load regulation (1) IO = 10 mA to 1200 mA 0 %/mA Leakage current into SW pin VI > VO, 0 V≤ VSW ≤ VI 0.1 1 Reverse leakage current into pin SW VI = open; EN = GND; VSW = 6.0 V 0.1 1 Short circuit switching frequency VFB = 0 V 625 µA µA kHz The line and load regulations are digitally controlled to assure an output voltage accuracy of ±3%. PIN ASSIGNMENTS DGQ PACKAGE (TOP VIEW) EN VIN VIN GND FB NOTE: 1 10 2 9 3 8 4 7 5 6 DRC PACKAGE (TOP VIEW) PGND PGND SW SW MODE EN VIN VIN GND FB 1 10 2 9 3 8 4 7 5 6 PGND PGND SW SW MODE The PowerPAD must be connected to GND. 3 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 PIN ASSIGNMENTS (continued) Terminal Functions TERMINAL NAME I/O NO. DESCRIPTION EN 1 I Enable. Pulling EN to ground forces the device into shutdown mode. Pulling EN to VI enables the device. EN should not be left floating and must be terminated. VIN 2, 3 I Supply voltage input GND 4 FB 5 I Feedback. Connect an external resistor divider to this pin. MODE MODE 6 I The difference between TPS62020 and TPS62021 is the logic level of the MODE pin. The TPS62021 has an active-low MODE pin. The TPS62020 is forced into fixed-frequency PWM mode by pulling the MODE pin high. Pulling the MODE pin low enables the Power Save Mode, operating in PFM mode (Pulse frequency modulation) at light load current, and in fixed frequency PWM at medimum to heavy load currents. In contrast, the TPS62021 is forced into PWM mode by pulling the MODE pin low. Analog ground SW 7, 8 I/O This is the switch pin of the converter and connected to the drain of the internal power MOSFETs PGND 9, 10 Power ground FUNCTIONAL BLOCK DIAGRAM VIN Current limit Comparator Undervoltage Lockout Bias supply + − Soft Start EN + Ref SkipComparator − V Vcomp Comparator + Saw Tooth Generator Ref MODE 1.25 MHz Oscillator I P−Channel Power MOSFET VIN S R Control Logic − SW Driver Shoot−thru Logic SW Comp High N−Channel Power MOSFET Comp Low Comp Low 2 Comp High LoadComparator − Gm Compensation + + Comp Low Comp Low 2 Vref = 0.5 V MODE GND − + − FB (See Note A) NOTE A: The TPS62020 has an active-high MODE pin. The TPS62020 has an active-low MODE pin. 4 PGND PGND TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE η Efficiency vs Load current 1, 2, 3 η Efficiency vs Input voltage 4 IQ No load quiescent current vs Input voltage 5, 6 fs Switching frequency vs Input voltage 7 rDS(on) P-Channel switch rDS(on) vs Input voltage 8 rDS(on) N-Channel rectifier switch rDS(on) vs Input voltage 9 Load transient response 10 PWM operation 11 Power save mode operation 12 Start-up 13 EFFICIENCY vs LOAD CURRENT 100 EFFICIENCY vs LOAD CURRENT 100 VO = 3.3 V 95 90 VI = 2.7 V 90 VI = 3.6 V Mode = Low 85 80 85 VI = 5 V Mode = Low 75 VI = 3.6 V 80 Efficiency − % Efficiency − % VO = 1.8 V 95 70 65 75 Mode = Low 70 65 60 60 55 55 50 50 45 45 40 VI = 5 V VI = 3.6 V Mode = High 40 0 0.01 0.10 1 10 IL − Load Current − mA Figure 1. 100 1000 0 0.01 0.10 1 10 IL − Load Current − mA 100 1000 Figure 2. 5 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs LOAD CURRENT 100 100 VO = 1.5 V 95 90 VO = 1.8 V Mode = Low 95 VI = 2.7 V 85 VI = 3.6 V 75 IL = 250 mA 90 Efficiency − % 80 Efficiency − % EFFICIENCY vs INPUT VOLTAGE VI = 5 V 70 65 Mode = Low 60 IL = 500 mA 85 IL = 1 mA 80 55 50 75 Mode = High 45 40 0 0.01 0.10 1 10 IL − Load Current − mA 100 70 2.5 1000 4.5 5 Figure 4. QUIESCENT CURRENT vs INPUT VOLTAGE QUIESCENT CURRENT vs INPUT VOLTAGE 5.5 6 5.5 6 7.5 MODE = High 7 19 Quisecent Current − mA TA = 85°C 21 Quisecent Current − µ A 4 Figure 3. MODE = Low TA = 25°C 17 TA = −40°C 15 13 11 6.5 5.5 5 4.5 4 7 3.5 2.8 3.2 3.6 4 4.4 4.8 5.2 VI − Input Voltage − V 5.6 6 TA = 25°C 6 9 Figure 5. 6 3.5 VI − Input Voltage − V 23 5 2.4 3 3 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V Figure 6. TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE P-CHANNEL rDS(on) vs INPUT VOLTAGE 0.180 1.23 0.170 TA = 85°C 1.22 P−Channel r DS(on) − Ω f − Switching Frequency − MHz 1.23 TA = 25°C 1.22 1.21 1.21 TA = −40°C 1.20 1.20 TA = 85°C 0.150 0.140 TA = 25°C 0.130 0.120 0.110 1.19 0.100 1.19 TA = −40°C 0.090 1.18 1.18 2.5 0.160 2.9 3.3 3.7 4.1 4.5 4.9 VI − Input Voltage − V 5.3 5.7 0.080 2.5 6 2.9 3.3 3.7 4.1 4.5 4.9 VI − Input Voltage − V Figure 7. Figure 8. N-CHANNEL RECTIFIER rDS(on) vs INPUT VOLTAGE LOAD TRANSIENT RESPONSE 5.3 5.7 6 0.150 VO 100 mV/div 0.130 TA = 85°C 0.120 TA = 25°C 0.110 VI = 3.6 V, VO = 1.8 V, PWM/PFM Operation 0.100 0.090 IO 50 mA to 600 mA N-Channel Rectifier r DS(on) − Ω 0.140 0.080 0.070 TA = −40°C 0.060 0.050 2.5 2.9 3.3 3.7 4.1 4.5 4.9 VI − Input Voltage − V Figure 9. 5.3 5.7 6 50 µs/div Figure 10. 7 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) PWM OPERATION POWER SAVE MODE OPERATION IL 500 mA/div IL 500 mA/div VO 20 mV/div VO 20 mV/div VSW 5 V/div VSW 2 V/div VI = 3.6 V, VO = 1.8 V VI = 3.6 V, VO = 1.8 V 2.5 µs/div 500 ns/div Figure 11. Figure 12. 2 V/div VI = 3.6 V, VO = 1.8 V, IO = 545 mA II 200 mV/div VO 1 V/div Enable START-UP 200 µs/div Figure 13. 8 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 DETAILED DESCRIPTION OPERATION The TPS62020 is a synchronous step-down converter operating with typically 1.25-MHz fixed frequency. At moderate to heavy load currents the device operates in pulse width modulation (PWM), and at light load currents the device enters power save mode operation using pulse frequency modulation (PFM). When operating in PWM mode, the typical switching frequency is 1.25 MHz with a minimum switching frequency of 1 MHz. This makes the device suitable for xDSL applications minimizing RF (radio frequency) interference. During PWM operation the converter uses a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal (S) the P-channel MOSFET switch turns on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. The Gm amplifier as well as the input voltage determines the rise time of the saw tooth generator, and therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter, giving a very good line and load transient regulation. POWER SAVE MODE OPERATION As the load current decreases, the converter enters power save mode operation. During power save mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current maintaining high efficiency. The converter monitors the average inductor current and the device enters power save mode when the average inductor current is below the threshold. The transition point between PWM and power save mode is given by the transition current with the following equation: V I I transition 18.66 (1) During power save mode the output voltage is monitored with the comparator by the threshold's comp low and comp high. As the output voltage falls below the comp low threshold set to typically 0.8% above the nominal output voltage, the P-channel switch turns on. The P-channel switch remains on until the transition current Equation 1 is reached. Then the N-channel switch turns on completing the first cycle. The converter continues to switch with its normal duty cycle determined by the input and output voltage but with half the nominal switching frequency of 625-kHz typ. Thus the output voltage rises and, as soon as the output voltage reaches the comp high threshold of 1.6%, the converter stops switching. Depending on the load current, the converter switches for a longer or shorter period of time in order to deliver the energy to the output. If the load current increases and the output voltage can not be maintained with the transition current Equation 1, the converter enters PWM again. See Figure 11 and Figure 12 under the typical graphs section and Figure 14 for power save mode operation. Among other techniques this advanced power save mode method allows high efficiency over the entire load current range and a small output ripple of typically 1% of the nominal output voltage. Setting the power save mode thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converter to operate with small output capacitors like 10 µF or 22 µF and still having a low absolute voltage drop during heavy load transient. Refer to Figure 14 as well for detailed operation of the power save mode. 9 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 DETAILED DESCRIPTION (continued) PFM Mode at Light Load 1.6% Comp High 0.8% Comp Low VO Comp Low 2 PWM Mode at Medium to Full Load Figure 14. Power Save Mode Thresholds and Dynamic Voltage Positioning The converter enters the fixed frequency PWM mode as soon as the output voltage falls below the comp low 2 threshold. DYNAMIC VOLTAGE POSITIONING As described in the power save mode operation sections before and as detailed in Figure 14 the output voltage is typically 0.8% (i.e., 1% on average) above the nominal output voltage at light load currents, as the device is in power save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. In the other direction during a load transient from full load to light load the voltage overshoot is also minimized by turning on the N-Channel rectifier switch to pull the output voltage actively down. MODE (AUTOMATIC PWM/PFM OPERATION AND FORCED PWM OPERATION) Connecting the MODE pin of the TPS62020 to GND enables the automatic PWM and power save mode operation. The converter operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. Pulling the TPS62020 MODE pin high forces the converter to operate constantly in the PWM mode even at light load currents. The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads (see Figure 1 to Figure 3). For additional flexibility it is possible to switch from power save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the TPS6204x to the specific system requirements. The difference between the TPS62020 and the TPS62021 is the logic level of the MODE pin. The TPS62021 has an active-low MODE pin. Pulling the TPS62021 MODE pin high enables the automatic PWM and Power Save Mode. 100% DUTY CYCLE LOW DROPOUT OPERATION The TPS62020 offers a low input to output voltage difference while still maintaining regulation with the use of the 100% duty cycle mode. In this mode, the P-Channel switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as: V min V max I max r max R I O O DS(on) L with: • • 10 IO(max) = maximum output current plus inductor ripple current rDS(on)max = maximum P-channel switch tDS(on). (2) TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 DETAILED DESCRIPTION (continued) • • RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance SOFTSTART The TPS62020 series has an internal softstart circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage in case a battery or a high impedance power source is connected to the input of the TPS62020. The softstart is implemented with a digital circuit increasing the switch current in steps of typically ILIM/8, ILIM/4, ILIM/2 and then the typical switch current limit of 1.1 A as specified in the electrical parameter table. The start-up time mainly depends on the output capacitor and load current, see Figure 13. SHORT-CIRCUIT PROTECTION As soon as the output voltage falls below 50% of the nominal output voltage, the converter switching frequency as well as the current limit is reduced to 50% of the nominal value. Since the short-circuit protection is enabled during start up the device does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal output voltage. This needs to be considered in case a load acting as a current sink is connected to the output of the converter. THERMAL SHUTDOWN As soon as the junction temperature of typically 150°C is exceeded the device goes into thermal shutdown. In this mode, the P-Channel switch and N-Channel rectifier are turned off. The device continues its operation when the junction temperature falls below typically 150°C again. ENABLE Pulling the EN low forces the part into shutdown mode, with a shutdown current of typically 0.1 µA. In this mode, the P-Channel switch and N-Channel rectifier are turned off and the whole device is in shut down. If an output voltage is present during shut down, which could be an external voltage source or super cap, the reverse leakage current is specified under electrical parameter table. For proper operation the enable (EN) pin must be terminated and should not be left floating. Pulling EN high starts up the device with the softstart as described under the section Softstart. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents device misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET with undefined conditions. 11 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 APPLICATION INFORMATION ADJUSTABLE OUTPUT VOLTAGE VERSION When the adjustable output voltage version TPS62020 is used, the output voltage is set by the external resistor divider. See Figure 15. The output voltage is calculated as: V 0.5 V 1 R1 O R2 (3) with R1 + R2 ≤ 1 MΩ and internal reference voltage Vref typical = 0.5 V R1 + R2 should not be greater than 1 MΩ because of stability reasons. To keep the operating quiescent current to a minimum, the feedback resistor divider should have high impedance with R1+R2≤1 MΩ. Due to this and the low reference voltage of Vref = 0.5 V, the noise on the feedback pin (FB) needs to be minimized. Using a capacitive divider C1 and C2 across the feedback resistors minimizes the noise at the feedback, without degrading the line or load transient performance. C1 and C2 should be selected as: 1 C1 2 10 kHz R1 (4) with: • • R1 = upper resistor of voltage divider C1 = upper capacitor of voltage divider For C1 a value should be chosen that comes closest to the calculated result. C2 R1 C1 R2 (5) with: • • R2 = lower resistor of voltage divider C2 = lower capacitor of voltage divider For C2, the selected capacitor value should always be selected larger than the calculated result. For example, in Figure 15 for C2 100 pF are selected for a calculated result of C2 = 88.42 pF. If quiescent current is not a key design parameter C1 and C2 can be omitted, and a low impedance feedback divider has to be used with R1 + R2 < 100 kΩ. This reduces the noise available on the feedback pin (FB) as well but increases the overall quiescent current during operation. The higher the programmed output voltage the lower the feedback impedance has to be for best operation when not using C1 and C2. VI 2.5 V to 6 V C3 22 µF TPS62020 2 SW VIN 3 SW VIN 1 FB EN 6 MODE PGND 4 GND PGND 8 7 5 10 9 VO 1.8 V / 600 mA L1 6.2 µH R1 470 kΩ R2 180 kΩ C1 33 pF C4 22 µF C2 100 pF Figure 15. Adjustable Output Voltage Version 12 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 APPLICATION INFORMATION (continued) Inductor Selection The TPS62020 uses typically a 10-µH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. When changing inductor values, the product of the inductor value times output-capacitor value (L×C) should stay constant. For example, when reducing the inductor value, increase the output capacitor accordingly. See the application circuits in Figure 17, Figure 18, and Figure 19. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of the converter. Therefore an inductor with the lowest dc resistance should be selected for highest efficiency. Formula Equation 7 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with formula Equation 7. This is needed because during heavy load transient the inductor current rises above the value calculated under Equation 7. V 1– O V I I V L O Lƒ (6) I I max I max L L O 2 (7) with: • • • • 7 = Switching frequency (1.25 MHz typical) L = Inductor value ∆IL= Peak-to-peak inductor ripple current ILmax = Maximum inductor current The highest inductor current occurs at maximum VI. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of 1.3 A for the TPS62020. Keep in mind that the core material from inductor to inductor differs and has an impact on the efficiency, especially at high switching frequencies. Refer to Table 1 and the typical applications and inductors selection. Table 1. Inductor Selection INDUCTOR VALUE DIMENSIONS COMPONENT SUPPLIER 10 µH 6,6 mm × 4,75 mm × 2,92 mm Coilcraft DO1608C-103 10 µH 5,0 mm × 5,0 mm × 3,0 mm Sumida CDRH4D28-100 3.3 µH 5,0 mm × 5,0 mm × 2,4 mm Sumida CDRH4D22 3R3 6.8 µH 5,8 mm × 7,4 mm × 1,5 mm Sumida CMD5D13 6R8 Output Capacitor Selection The advanced fast response voltage mode control scheme of the TPS62020 allows the use of small ceramic capacitors with a typical value of 10 µF and 22 µF without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. Refer to Table 2 for component selection. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness the RMS ripple current is calculated as: V 1– O V I I V 1 RMSCout O Lƒ 2 3 (8) At nominal load current the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 13 TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 V 1– O V I V V O O Lƒ 1 ESR 8C ƒ O (9) Where the highest output voltage ripple occurs at the highest input voltage, VI. At light load currents, the device operates in power save mode and the output voltage ripple is independent of the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical output voltage ripple is 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The input capacitor should have a minimum value of 10 µF for the TPS62020. The input capacitor can be increased without any limit for better input voltage filtering. Table 2. Input and Output Capacitor Selection CAPACITOR VALUE CASE SIZE 10 µF 0805 Taiyo Yuden JMK212BJ106MG TDK C12012X5ROJ106K Ceramic Ceramic 10 µF 1206 Taiyo Yuden JMK316BJ106KL TDK C3216X5ROJ106M Ceramic 22 µF 1206 Taiyo Yuden JMK316BJ226ML Ceramic 22 µF 1210 Taiyo Yuden JMK325BJ226MM Ceramic COMPONENT SUPPLIER COMMENTS Layout Considerations For all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 16. These traces should be routed first. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. The feedback resistor network should be routed away from the inductor and switch node to minimize noise and magnetic interference. To further minimize noise from coupling into the feedback network and feedback pin, the ground plane or ground traces should be used for shielding. A common ground plane or a star ground as shown below should be used. This becomes very important especially at high switching frequencies of 1.25 MHz. The Switch Node Must Be Kept as Small as Possible TPS62020 VI C3 22 µF 2 3 1 6 4 VIN VIN EN MODE GND 8 SW 7 SW FB 5 10 PGND 9 PGND L1 6.2 µH Figure 16. Layout Diagram 14 VO C2 22 µF TPS62020, TPS62021 www.ti.com SLVS076B – JUNE 2003 – REVISED APRIL 2004 THERMAL INFORMATION One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat dissipating abilities of the PowerPAD™ packages, a board should be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. For further information please refer to Texas Instruments application note (SLMA002) PowerPAD Thermally Enhanced Package. The PowerPAD™ of the 10-pin MSOP package has an area of 1,52 mm × 1,79 mm (±0,05 mm) and must be soldered to the PCB to lower the thermal resistance. Thermal vias to the next layer further reduce the thermal resistance. TYPICAL APPLICATIONS Vin 3.6V to 6.0V L1 3.3uH TPS62020 2 3 1 6 4 C3 10uF 8 SW SW 7 5 FB 10 PGND PGND 9 VIN VIN EN MODE GND Vout 3.3V/0.6A C4 22uF R1 620k C1 22pF R2 110k C2 150pF C5 22uF Figure 17. Li-Ion to 3.3 V With Improved Load Transient Response Vin 2.5V to 6.0V TPS62020 C3 10uF 2 3 1 6 4 VIN VIN EN MODE GND 8 SW SW 7 5 FB 10 PGND PGND 9 L1 6.8uH R1 620k R2 240k Vout 1.8V/0.6A C1 22pF C4 22uF C2 68pF Figure 18. 1.8 V Output Using 6.8 µH Inductor Vin 2.5V to 6.0V TPS62020 C3 10uF 2 3 1 6 4 VIN VIN EN MODE GND 8 SW SW 7 5 FB 10 PGND PGND 9 L1 10uH R1 470k R2 330k Vout 1.2V/0.6A C1 33pF C4 10uF C2 68pF Figure 19. 1.2 V Output Using 10 µH Inductor 15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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