TI SN74AUP1G80DCKR

SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
FEATURES
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Low Static-Power Consumption
(ICC = 0.9 µA Max)
Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V)
•
•
•
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•
DBV PACKAGE
(TOP VIEW)
D
1
CLK
2
GND
3
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 4.3 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ESD Protection Exceeds ±5000 V With
Human-Body Model
DCK PACKAGE
(TOP VIEW)
D
1
CLK
2
GND
3
VCC
5
YEP OR YZP PACKAGE
(BOTTOM VIEW)
VCC
5
GND
CLK
D
4
3 4
Q
2
1 5
VCC
Q
Q
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see Figure 2).
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
Switching Characteristics
at 25 MHz†
100%
100%
3.5
80%
80%
2.5
60%
60%
3.3-V
Logic†
40%
Voltage − V
3
3.3-V
Logic
LVC †
40%
AUP
0%
†
0%
Output
0.5
20%
20%
Input
2
1.5
1
AUP
Single, dual, and triple gates
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74AUP1G80YEPR
Reel of 3000
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
(2)
_ _ _HX_
SN74AUP1G80YZPR
–40°C to 85°C
(1)
Reel of 3000
SN74AUP1G80DBVR
Reel of 250
SN74AUP1G80DBVT
Reel of 3000
SN74AUP1G80DCKR
Reel of 250
SN74AUP1G80DCKT
H80_
HX_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
FUNCTION TABLE
INPUTS
CLK
D
OUTPUT
Q
↑
H
L
↑
L
H
L or H
X
Q0
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
CLK
Q
D
2
TOP-SIDE MARKING (2)
D
Q
www.ti.com
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES593B – JULY 2004 – REVISED JULY 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (3)
Tstg
(1)
(2)
(3)
DBV package
206
DCK package
252
YEP/YZP package
132
Storage temperature range
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
MIN
MAX
0.8
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.65 × VCC
High-level output current (2)
2
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Low-level output current (2)
3.6
0
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
V
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
∆t/∆v
V
0.9
0
VCC = 3 V
IOL
V
1.6
VCC = 3 V to 3.6 V
IOH
V
VCC
VCC = 0.8 V
VIL
UNIT
µA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Defined by the signal integrity requirements and design-goal priorities.
3
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VOH
MIN
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –2.7 mA
IOH = –4 mA
2.3 V
3V
IOL = 20 µA
0.8 V to 3.6 V
IOL = 1.1 mA
2.6
UNIT
MAX
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0 V to 3.6 V
0.1
0.5
µA
IOL = 2.3 mA
IOL = 3.1 mA
IOL = 2.7 mA
IOL = 4 mA
II
MAX
IOH = –1.1 mA
IOH = –3.1 mA
D or CLK
input
TYP
IOH = –20 µA
IOH = –2.3 mA
VOL
TA = –40°C
to 85°C
TA = 25°C
VI = GND to 3.6 V
2.3 V
3V
V
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
µA
∆Ioff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
µA
ICC
VI = GND or VCC to 3.6 V, IO = 0
0.8 V to 3.6 V
0.5
0.9
µA
∆ICC
VI = VCC – 0.6 V, (1) IO = 0
3.3 V
40
50
µA
Ci
VI = VCC or GND
Co
VO = GND
(1)
4
One input at VCC – 0.6 V, other input at VCC or GND
0V
1.5
3.6 V
1.5
0V
3
pF
pF
www.ti.com
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES593B – JULY 2004 – REVISED JULY 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC
TA = 25°C
TYP
TA = –40°C
to 85°C
MIN
0.8 V
fclock
Clock frequency
20
1.2 V ± 0.1 V
80
1.5 V ± 0.1 V
120
1.8 V ± 0.15 V
160
2.5 V ± 0.2 V
220
3.3 V ± 0.3 V
tw
Pulse duration, CLK high or low
5.5
1.2 V ± 0.1 V
2.5
1.5 V ± 0.1 V
1.5
1.8 V ± 0.15 V
1.6
2.5 V ± 0.2 V
1.7
0.8 V
tsu
1.9
3.4
2.4
1.5 V ± 0.1 V
1.2
1.8 V ± 0.15 V
0.8
2.5 V ± 0.2 V
0.6
0.8 V
Data low
Hold time, data after CLK↑
8.9
1.2 V ± 0.1 V
2
1.5 V ± 0.1 V
1.3
1.8 V ± 0.15 V
1.1
2.5 V ± 0.2 V
0.8
0.8 V
ns
0.4
3.4
3.3 V ± 0.3 V
th
6.7
1.2 V ± 0.1 V
3.3 V ± 0.3 V
Setup time before CLK↑
MHz
260
0.8 V
3.3 V ± 0.3 V
Data high
UNIT
MAX
ns
0.7
0
1
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
ns
5
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
MAX
MIN
0.8 V
91
90
1.2 V ± 0.1 V
175
220
1.5 V ± 0.1 V
237
230
1.8 V ± 0.15 V
269
240
2.5 V ± 0.2 V
280
250
3.3 V ± 0.3 V
280
260
0.8 V
17.2
UNIT
MAX
MHz
1.2 V ± 0.1 V
3.2
7.1
14.9
2.7
16.3
1.5 V ± 0.1 V
1.9
5
9.8
2.1
10.3
1.8 V ± 0.15 V
1.7
3.9
7.6
1.6
8.1
2.5 V ± 0.2 V
1.4
2.8
5.3
1.2
5.6
3.3 V ± 0.3 V
1.2
2.2
4.1
1
4.4
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
6
CLK
Q
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
MAX
MIN
0.8 V
68
70
1.2 V ± 0.1 V
128
170
1.5 V ± 0.1 V
189
220
1.8 V ± 0.15 V
234
240
2.5 V ± 0.2 V
273
250
3.3 V ± 0.3 V
280
260
0.8 V
19.4
UNIT
MAX
MHz
1.2 V ± 0.1 V
4.4
8.2
16.2
3.4
17.7
1.5 V ± 0.1 V
3.6
5.8
10.7
2.6
11.3
1.8 V ± 0.15 V
2.9
4.6
8.4
2.1
3
2.5 V ± 0.2 V
2.2
3.3
5.9
1.7
6.3
3.3 V ± 0.3 V
1.9
2.7
4.7
1.4
4.9
ns
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
MAX
MIN
0.8 V
52
50
1.2 V ± 0.1 V
98
130
1.5 V ± 0.1 V
148
180
1.8 V ± 0.15 V
196
240
2.5 V ± 0.2 V
249
250
3.3 V ± 0.3 V
280
260
0.8 V
21.5
UNIT
MAX
MHz
1.2 V ± 0.1 V
3
9.1
17.4
4.1
19
1.5 V ± 0.1 V
3.2
6.5
11.7
3.2
12.3
1.8 V ± 0.15 V
2.7
4.2
9.2
2.6
9.8
2.5 V ± 0.2 V
2.2
3.8
6.5
2.1
6.9
3.3 V ± 0.3 V
1.9
3.1
5.1
1.8
5.5
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
fmax
tpd
CLK
Q
TA = –40°C
to 85°C
TA = 25°C
VCC
TYP
MAX
MIN
32
UNIT
MAX
20
1.2 V ± 0.1 V
71
80
1.5 V ± 0.1 V
104
120
1.8 V ± 0.15 V
133
160
2.5 V ± 0.2 V
181
220
3.3 V ± 0.3 V
257
260
0.8 V
28.4
MHz
1.2 V ± 0.1 V
5.1
11.8
20.7
6.2
28.7
1.5 V ± 0.1 V
4.8
8.5
14.1
6.9
16.7
1.8 V ± 0.15 V
4
6.9
11.2
2
13.3
2.5 V ± 0.2 V
3.3
5.1
7.9
3.2
9.3
3.3 V ± 0.3 V
2.9
4.2
6.4
2.8
7.5
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
2.5
1.2 V ± 0.1 V
2.5
1.5 V ± 0.1 V
2.5
1.8 V ± 0.15 V
2.5
2.5 V ± 0.2 V
3
3.3 V ± 0.3 V
3
UNIT
pF
7
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
Data Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
th
SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
www.ti.com
SCES593B – JULY 2004 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G80DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G80YZPR
ACTIVE
WCSP
YZP
5
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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