TI ADS62C17IRGCT

ADS62C17
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
FEATURES
•
•
•
•
•
•
•
1
•
•
•
Maximum Sample Rate: 200 MSPS
11-bit Resolution with No Missing Codes
90 dBc SFDR at Fin = 10 MHz
79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
using TI proprietary SNRBoost technology
Total Power 1.1 W at 200 MSPS
90 dB Cross-talk
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
•
•
•
Programmable Gain up to 6dB for SNR/SFDR
Trade-off
DC Offset Correction
Gain Tuning Capability in Fine Steps (0.001
dB) Allows Channel-to-channel Gain Matching
Supports Input Clock Amplitude Down to 400
mV p-p Differential
Internal and External Reference Support
64-QFN Package (9 mm × 9 mm)
DESCRIPTION
ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low
power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width
communications applications.
ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to
quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital
functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001
dB).
The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain
tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching.
The device also includes a dc offset correction loop that can be used to cancel the ADC offset.
Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes
internal references while the traditional reference pins and associated decoupling capacitors have been
eliminated. Nevertheless, the device can also be driven with an external reference.
The device is specified over the industrial temperature range (–40°C to 85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
ADS62C17
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DRGND
DRVDD
AGND
AVDD
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LVDS
INTERFACE
DA0P/M
Digital
Processing
Block
Sample
&
Hold
INA_P
INA_M
14 bit
ADC
DA2P/M
DA4P/M
SNRBoost
11 bit
DDR
Serializer
DA6P/M
DA8P/M
Channel A
DA10P/M
CLKP
CLKM
OUTPUT
CLOCK
BUFFER
CLOCKGEN
CLKOUTP/M
DB0P/M
INB_P
Digital
Processing
Block
Sample
&
Hold
INB_M
14 bit
ADC
DB2P/M
DB4P/M
SNRBoost
11 bit
DDR
Serializer
DB6P/M
DB8P/M
Channel B
DB10P/M
VCM
REFERENCE
CONTROL
INTERFACE
SDOUT
RESET
SCLK
SEN
SDATA
CTRL1
CTRL2
CTRL3
ADS62C17
Figure 1. ADS62C17 Block Diagram
PACKAGE/ORDERING INFORMATION
2
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE RANGE
PACKAGE MARKING
ORDERING NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS62C17
QFN-64
RGC
–40°C to 85°C
AZ62C17
ADS62C17IRGCR
ADS62C17IRGCT
Tape and Reel
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THERMAL CHARACTERISTICS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RθJA (2)
RθJT
(1)
(2)
(3)
(3)
TEST CONDITIONS
TYP
Soldered thermal pad, no airflow
22
Soldered thermal pad, 200 LFM
15
Bottom of package (thermal pad)
0.57
UNIT
° C/W
With a JEDEC standard high K board and 5x5 via array. See Exposed Pad in the Application Information.
RθJA is the thermal resistance from the junction to ambient.
RθJT is the thermal resistance from the junction to the thermal pads.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
Supply voltage range AVDD
-0.3 to 3.9
Supply voltage range DRVDD
–0.3 to 2.2
Voltage between AGND and DRGND
–0.3 to 0.3
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
0 to 3.3
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
–1.5 to 1.8
Voltage applied to external pin, VCM (in external refersnce mode)
Voltage applied to analog input pins – INP_A, INM_A, INP_B, INM_B
Voltage applied to input pins – CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, CTRL1,
CTRL2, CTRL3
UNIT
V
V
–0.3 to 2.0
–0.3V to minimum
(3.6, AVDD + 0.3V)
V
–0.3V to ADD + 0.3V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
ESD, human body model
(1)
(2)
–54 to 150
°C
2
kV
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. This
prevents the ESD protection diodes at the clock input pins from turning on.
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RECOMMENDED OPERATING CONDITIONS (1)
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3.15
3.3
3.8
V
DRVDD
Digital supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
Differential input voltage range
2
Input common-mode voltage
VPP
1.5 ± 0.1
Voltage applied on CM in external reference mode
V
1.5 ± 0.05
V
Maximum analog input frequency with 2V pp input amplitude
(1)
500
MHz
Maximum analog input frequency with 1V pp input amplitude
(1)
800
MHz
CLOCK INPUT
Input clock sample rate
1
200 MSPS
Input Clock amplitude differential (VCLKP– VCLKM)
Sine wave, ac-coupled
3.0
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
3.3
V
Input clock duty cycle
0.2
40%
50%
60%
DIGITAL OUTPUTS
CL
Maximum external load capacitance from each output pin to DRGND
RL
Differential external load resistance between the LVDS output (LVDS interface)
TA
Operating free-air temperature
(1)
4
–40
5
pF
100
Ω
85
°C
See Theory of Operation in the application section.
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ELECTRICAL CHARACTERISTICS (1)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, LVDS and CMOS interfaces unless otherwise noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
11
bits
ANALOG INPUTS
Differential input voltage range
2.0
VPP
Differential input resistance (at dc)
See Figure 44
>1
MΩ
Differential input capacitance
See Figure 45
3.5
pF
Analog input bandwidth
700
MHz
Analog input common mode current (per channel)
3.6
µA/MSPS
VCM common mode voltage output
1.5
V
VCM output current capability
±4
mA
262
mA
120
mA
87
mA
POWER SUPPLY
IAVDD
Analog supply current
IDRVDD
Output buffer supply current LVDS interface
With 100 Ω external
termination
IDRVDD
Output buffer supply current CMOS interface
No external load
capacitance
Analog power
865
1025
mW
Digital power LVDS interface
216
306
mW
45
75
mW
Global power down
No missing codes
Assured
DC ACCURACY
DNL
Differential Non-Linearity
Fin = 170 MHz
-0.6
±0.2
0.6
LSB
INL
Integral Non-Linearity
Fin = 170 MHz
-2.5
±0.75
2.5
LSB
-20
±2
20
mV
Offset Error
Offset error temperature coefficient
Offset error variation with supply
0.02
mV/C
0.5
mV/V
There are two sources of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal reference inaccuracy alone
-1
±0.2
1
Gain error of channel alone (2)
-1
+0.2
1
Channel gain error temperature coefficient
Gain matching
(1)
(2)
(3)
(3)
-2
Difference in gain errors
between two channels
across two devices
-4
% FS
Δ%/°C
0.002
Difference in gain errors
between two channels
within the same device
% FS
2
% FS
4
In CMOS interface, the DRVDD current scales with the sampling frequency and the load capacitance on output pins.
This is specified by design and characterization; it is not tested in production.
For two channels within the same device, only the channel gain error matters, as the reference is common for both channels.
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, SNRBoost disabled, LVDS and CMOS interfaces unless otherwise noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V
PARAMETER
SNR
Signal to noise ratio
LVDS
TEST CONDITIONS
MIN
TYP MAX
Fin = 20 MHz
67
Fin = 70 MHz
66.8
Fin = 170 MHz
0 dB gain
64.5
6 dB gain
UNIT
dBFS
66.3
64.4
Table 1. SNR Enhancement With SNRBoost Enabled
SNRBoost bath-tub centered at Fsx0.25, –1 dBFS input applied at Fin = 125MHz, Sampling frequency = 200MSPS
SNR Within Specified bandwidth, dBFS
Bandwidth, MHz
(1)
6
With SNRBoost Enabled (1)
In Default Mode (SNRBoost Disabled)
MIN
TYP
5
78.8
79.6
10
75.8
15
74
20
MAX
MIN
TYP
83
85.6
76.6
80
82.6
74.9
78.2
80.9
72.7
73.6
77
79.6
30
71
71.9
74.4
76.4
40
69.8
70.6
72.7
74.5
MAX
Using recommended SNRBoost coefficients. See note on SNRBoost in application section.
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, SNRBoost disabled, 0dB gain, LVDS and CMOS interfaces unless
otherwise noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
Fin= 20 MHz
SINAD
Signal to Noise and Distortion Ratio
66.6
0 dB gain
63.5
6 dB gain
THD
Total Harmonic Distortion
83
0 dB gain
73
6 dB gain
83
Fin = 70 MHz
81
0 dB gain
71.5
6 dB gain
90
0 dB gain
73
6 dB gain
dBc
83
dBc
92
85
Fin = 70 MHz
83
0 dB gain
73
6 dB gain
78
dBc
81
Fin= 20 MHz
Worst Spur
Other than second, third harmonics
75.5
94
Fin= 20 MHz
Fin = 170 MHz
dBc
79
Fin = 70 MHz
Fin = 170 MHz
dBFS
81
Fin= 20 MHz
HD3
Third Harmonic Distortion
78
Fin= 20 MHz
Fin = 170 MHz
HD2
Second Harmonic Distortion
65.7
85
Fin = 70 MHz
Fin = 170 MHz
UNIT
64.2
Fin= 20 MHz
SFDR
Spurious Free Dynamic Range
MAX
66.9
Fin = 70 MHz
Fin = 170 MHz
TYP
94
Fin = 70 MHz
92
Fin = 170 MHz
80
IMD
2-Tone Inter-modulation Distortion
F1 = 185 MHz, F2 = 190 MHz, Each tone at –7 dBFS
Input Overload recovery
Recovery to within 1% (of final value) for 6-dB overload with
sine wave input at Fclk/4
Cross-talk
PSRR
AC Power Supply Rejection Ratio
dBc
90
87
dBFS
1
clock
cycles
Up to 200 MHz cross-talk frequency
90
dB
For 100 mV pp signal on AVDD supply
25
dB
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DIGITAL CHARACTERISTICS — ADS62C17
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 3.3V, DRVDD = 1.8V
PARAMETER
TEST CONDITIONS
DIGITAL INPUTS – CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN
High-level input voltage
MIN
High-level input current
Low-level input current
MAX
1.3
All digital inputs support 1.8 V and 3.3 V CMOS
logic levels.
Low-level input voltage
TYP
UNIT
(1)
0.4
SDATA, SCLK (2)
VHIGH = 3.3 V
16
SEN (3)
VHIGH = 3.3 V
10
SDATA, SCLK
VLOW = 0 V
0
SEN
VLOW = 0 V
–20
Input capacitance
V
µA
µA
4
pF
DRVDD – DRVDD
0.1
V
DIGITAL OUTPUTS – CMOS INTERFACE (DA0-DA10, DB0-DB10, CLKOUT, SDOUT)
High-level output voltage
Low-level output voltage
Ioh = 1mA
Iol = 1mA
0
Output capacitance (internal to device)
0.1
2
V
pF
DIGITAL OUTPUTS – LVDS INTERFACE (DA0P/M TO DA10P/M, DB0P/M TO DB10P/M, CLKOUTP/M)
VODH, High-level output differential voltage
With external 100 Ω termination
+275
+350
+425
mV
VODL, Low-level output differential voltage
With external 100 Ω termination.
–425
–350
–275
mV
1.0
1.15
1.40
VOCM, Output common-mode voltage
Capacitance inside the device from each output
to ground
Output Capacitance
(1)
(2)
(3)
2
V
pF
SCLK, SDATA, SEN function as digital input pins in serial configuration mode.
SDATA, SCLK have internal 200 kΩ pull-down resistor
SEN has internal 100 kΩ pull-up resistor to AVDD.
DAnP / DBnP
Logic 0
VODL = -350 mV*
Logic 1
VODH = +350 mV*
DAnM / DBnM
VOCM
GND
GND
* With external 100 W termination
Figure 2. LVDS Output Voltage Levels
8
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TIMING CHARACTERISTICS — LVDS AND CMOS MODES (1)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD =
5pF (2), RLOAD = 100 Ω (3), no internal termination, LOW SPEED mode disabled, unless otherwise noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to
1.9V.
PARAMETER
ta
TEST CONDITIONS
Aperture delay
Aperture delay matching
tj
MIN
TYP
MAX
0.7
1.2
1.7
between two channels of the same device
Aperture jitter
Wake-up time
ADC Latency (4)
UNIT
ns
±50
ps
145
fs rms
Time to valid data after coming out of STANDBY mode
1
3
Time to valid data after coming out of global powerdown
20
50
Time to valid data after stopping and restarting the input clock
10
Default, after reset
22
µs
Clock
cycles
DDR LVDS MODE (5)
Data setup time (6)
tsu
(7)
th
Data hold time
tPDI
Clock propagation delay
tdelay
Data valid (7) to zero-crossing of CLKOUTP
0.8
1.15
ns
Zero-crossing of CLKOUTP to data becoming invalid (7)
0.8
1.15
ns
Input clock falling edge cross-over to output clock rising edge
cross-over
100 MSPS ≤ Sampling frequency ≤ 200 MSPS
Ts = 1/Sampling frequency
tPDI = 0.69×Ts + tdelay
4.2
5.7
7.2
ns
tdelay skew
Difference in tdelay between two devices operating at same
temperature & SVDD supply voltage.
±500
LVDS bit clock duty cycle
Duty cycle of differential clock, (CLKOUTP-CLKOUTM)
100 MSPS ≤ Sampling frequency ≤ 200 MSPS
52%
tRISE, tFALL
Data rise time, Data fall time
Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1MSPS ≤ Sampling frequency ≤ 200 MSPS
0.14
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
0.14
ns
tOE
Output buffer enable to data delay
Time to valid data after output buffer becomes active
100
ns
ps
PARALLEL CMOS MODE at Fs=200 MSPS (8)
tSTART
Input clock to data delay
Input clock falling edge cross-over to start of data valid (7)
tDV
Data valid time
Time interval of valid data (7)
1.7
tPDI
Clock propagation delay
Input clock falling edge cross-over to output clock rising edge
cross-over
100 MSPS ≤ Sampling frequency ≤ 150 MSPS
Ts = 1/Sampling frequency
tPDI = 0.28×Ts + tdelay
tdelay
2.5
5.5
2.7
7.5
ns
ns
8.5
ns
Output clock duty cycle
Duty cycle of output clock, CLKOUT
100 MSPS ≤ Sampling frequency ≤ 150 MSPS
43
tRISE, tFALL
Data rise time, Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Sampling frequency ≤ 200 MSPS
1.2
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Sampling frequency ≤ 150 MSPS
0.8
ns
tOE
Output buffer enable (OE) to data
delay
Time to valid data after output buffer becomes active
100
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Timing parameters are ensured by design and characterization and not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground
RLOAD is the differential load resistance between the LVDS output pair.
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV.
Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.
For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).
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Table 2. LVDS Timings at Lower Sampling Frequencies
Sampling Frequency, MSPS
Setup Time, ns
Hold Time, ns
MIN
TYP
185
0.9
1.25
MAX
MIN
TYP
0.85
1.25
150
1.15
1.6
1.1
1.5
125
1.6
2
1.45
1.85
<100 Enable LOW SPEED mode
2
MAX
2
tPDI, ns
1 ≤ Fs ≤ 100 Enable LOW SPEED mode
MIN
TYP
MAX
12.6
Table 3. CMOS Timings at Lower Sampling Frequencies
Timings Specified With Respect to Input Clock
Sampling Frequency, MSPS
tSTART, ns
MIN
TYP
Data Valid Time, ns
MAX
MIN
TYP
190
1.9
2
3
170
0.9
2.7
3.7
150
6
3.6
4.6
MAX
Timings Specified With Respect to CLKOUT
Sampling Frequency, MSPS
Setup Time, ns
MIN
TYP
150
2.8
125
3.8
<100 Enable LOW SPEED mode
5
MAX
Hold Time, ns
MIN
TYP
4.4
0.5
1.2
5.4
0.8
1.5
MAX
1.2
tPDI, ns
1 ≤ Fs ≤ 100 Enable LOW SPEED mode
MIN
TYP
MAX
9
10
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N+3
N+2
N+1
Sample
N
N+4
N+24
N+23
N+22
INPUT
SIGNAL
ta
INPUT
CLOCK
CLKM
CLKP
CLKOUTM
CLKOUTP
22 clock cycles *
DDR
LVDS
OUTPUT DATA
DXP, DXM
E
O
E
O
E
O
E
O
E
t PDI
O
E
O
E
O
E
O
E
O
E
O
E – Even bits D0, D2, D4...
N-22
O – Odd bits D1, D3, D5...
N-21
N-20
N-1
N-19
N
N+2
N+1
CLKOUT
t PDI
22 clock cycles *
PARALLEL
CMOS
OUTPUT DATA
D0:D10
N-22
N-21
N-20
N18
N-19
N-1
N
N+1
N+2
Figure 3. Latency Diagram
CLKP
Input
clock
CLKM
t PDI
CLKOUTM
Output
clock
CLKOUTP
t su
Output
data pair
DAnP/M
DBnP/M
th
Dn*
t su
th
Dn+1*
*Dn – Bits D1,D3,D5...
*Dn+1 – Bits D0,D2,D4...
Figure 4. LVDS Interface Timing
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CLKP
CLKP
Input Clock
CLKM
CLKM
tPDI
Output Clock
CLKOUTCLKOUT
tsu
su
Output Data
DAn, DBn
th
Dn*
CLKP
CLKP
Input Clock
CLKM
CLKM
tSTART
tDV
Output Clock
DAn, DBn
Dn*
*Dn - Bits D0, D1, D2....of channel A and B
Figure 5. CMOS Interface Timing
DEVICE CONFIGURATION
ADS62C17 can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device in parallel configuration mode, keep RESET tied to high (AVDD).
Now, pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC.
The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in
Table 3 to Table 6. There is no need to apply reset and SDATA can be kept low.
In this mode, SEN and SCLK function as parallel interface control pins. Frequently used functions can be
controlled in this mode – Power down modes, internal/external reference, selection between LVDS/CMOS
interface and output data format.
Table 4 has a brief description of the modes controlled by the four parallel pins.
Table 4. PARALLEL PIN DEFINITION
PIN
SCLK
SEN
CTRL1
CTRL2
CONTROLS MODES
Analog control pins (controlled by analog
voltage level, see Figure 5
Digital control pints (controlled by digital
logic levels)
Internal or External reference
LVDS/CMOS interface and Output Data
Format
Control SNRBoost, Standby and MUX
mode.
CTRL3
12
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SERIAL INTERFACE CONFIGURATION ONLY
To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be
kept low.
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal
registers of the ADC.
The registers can be reset either by applying a pulse on RESET pin or by setting the <RESET> bit high. The
serial interface section describes the register programming and register reset in more detail.
USING BOTH SERIAL INTERFACE and PARALLEL CONTROLLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins
CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage
settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to
access the internal registers of ADC. The registers must first be reset to their default values either by applying a
pulse on RESET pin or by setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial
interface section describes the register programming and register reset in more detail.
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 6.
Table 5. SCLK Control Pin
SCLK
DESCRIPTION
0
+200mV/-0mV
Internal reference
(3/8)AVDD
±200mV
External reference
(5/8)2AVDD
±200mV
External reference
AVDD
+0mV/-200mV
Internal reference
Table 6. SEN Control Pin
SEN
DESCRIPTION
0
+200mV/-0mV
Offset binary and DDR LVDS output
(3/8)AVDD
±200mV
2’s complement format and DDR LVDS output
(5/8)2AVDD
±200mV
2’s complement format and parallel CMOS output
AVDD
+0mV/-200mV
Offset binary and parallel CMOS output
Table 7. CTRL1, CTRL2 and CTRL3 Pins
CTRL1
CTRL2
LOW
LOW
LOW
Normal operation
LOW
LOW
HIGH
SNRBoost enabled for Channel B (1)
LOW
HIGH
LOW
SNRBoost enabled for Channel A (1)
LOW
HIGH
HIGH
SNRBoost enabled for Channel A and B (1)
HIGH
LOW
LOW
Global power down
HIGH
LOW
HIGH
Channel B standby
(1)
CTRL3
DESCRIPTION
To enable & disable SNRBoost mode using the CTRL pins, reset the register bits <SNRBoost Enable CHA> = 0 & <SNRBoost Enable - CHB> = 0.
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Table 7. CTRL1, CTRL2 and CTRL3 Pins (continued)
CTRL1
CTRL2
CTRL3
HIGH
HIGH
LOW
Channel A standby
DESCRIPTION
HIGH
HIGH
HIGH
MUX mode of operation, Channel A and B data is multiplexed and output
on DA10 to DA0 pins.
AVDD
(5/8)AVDD
(5/8)AVDD
AVDD
GND
(3/8)AVDD
(3/8)AVDD
To Parallel Pin
GND
Figure 6. Simple Scheme to Configure Parallel Pins
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
Register Initialization (when using serial interface only)
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two
ways:
1.
Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 7
2.
OR
By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal
registers to their default values and then self-resets the <RESET> bit to low. In this case the RESET pin is kept low.
REGISTER DATA
REGISTER ADDRESS
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
tSCLK
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
SEN
tSLOADH
tSLOADS
RESET
Figure 7. Serial Interface Timing
14
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40C to TMAX = 85°C, AVDD = 3.3V,
DRVDD = 1.8V, unless otherwise noted.
PARAMETER
MIN
>DC
TYP
MAX
UNIT
20
MHz
fSCLK
SCLK frequency (= 1/ tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDS
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
Serial Register Readout
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic check to verify the serial interface communication between the external controller and the ADC.
a.
b.
c.
d.
e.
First, set register bit <SERIAL READOUT> = 1 to put the device in serial readout mode. This disables any further writes into the
registers, EXCEPT the register at address 0. Note that the <SERIAL READOUT> bit is also located in register 0. The device can exit
readout mode by writing <SERIAL READOUT> to 0. Also, only contents of register at adress 0 cannot be read in the register readout
mode.
Initiate a serial interface cycle specifying the address of the register (A7–A0) whose content has to be read.
The device outputs the contents (D7–D0) of the selected register on the SDOUT pin.
The external controller can latch the contents at the falling edge of SCLK.
To exit the serial readout mode, reset register bit <SERIAL READOUT> = 0, which enables writes into all registers of the device.
The serial register readout works with both CMOS and LVDS interfaces.
When <SERIAL READOUT> is disabled, SDOUT pin is forced low by the device (and not put in
high-impedance). If serial readout is not used, SDOUT pin has to be floated.
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A) Enable serial readout (<SERIAL READOUT> = 1)
REGISTER DATA (D7:D0) = 0x01
REGISTER ADDRESS (A7:A0) = 0x00
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
SDOUT
Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0)
B) Read contents of register 0x3F.
This register has been initialized with 0x04
(device is put in global power down mode)
REGISTER DATA (D7:D0 ) = XX (don’t care)
REGISTER ADDRESS (A7:A0) = 0x3F
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1)
Figure 8. Serial Readout
RESET TIMING (WHEN USING SERIAL INTERFACE ONLY)
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise
noted.
PARAMETER
CONDITIONS
MIN
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
t2
Reset pulse width
Pulse width of active RESET signal
TYP
MAX
1
ns
10
ns
1 (1)
t3
(1)
16
Register write delay
Delay from RESET disable to SEN active
100
UNIT
µs
ns
The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1usec, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 9. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 8. Summary of Functions Supported by Serial Interface (1)
REGISTER
ADDRESS
REGISTER FUNCTIONS
A7 - A0
IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
00
<RESET>
Software
Reset
0
0
0
0
0
0
<SERIAL
READOUT>
0
0
<STAND
BY>
0
0
0
0
<ENABLE
LOW
SPEED
mode>
<REF>
Internal or external reference
0
0
0
20
0
0
3F
0
40
0
0
0
0
41
<LVDS
CMOS>
Output
interface
0
0
0
0
<ENABLE
INDEPENDENT
CHANNEL CONTROL>
44
50
53
(1)
18
0
0
<CLKOUT EDGE CONTROL>
51
52
<POWER DOWN MODES>
0
0
0
0
0
0
0
<DATA FORMAT>
2s comp or offset
binary
<CUSTOM PATTERN LOW>
0
0
0
<CUSTOM PATTERN HIGH>
0
<OFFSET CORRECTION
ENABLE – Common/Ch
A>
0
0
0
0
55
<GAIN PROGRAMMABILITY – Common/Ch A>
0 to 6 dB in 0.5 dB steps
<OFFSET CORRECTION TIME
CONSTANT – Common/ Ch A >
56
<SNRBoost Coeff 1 – Common/ Ch A >
<SNRBoost Coeff 2 – Common/ Ch A >
<FINE GAIN ADJUST – Common/ Ch A >
+0.001 dB to +0.134 dB, in 128 steps
57
0
59
0
0
0
0
0
62
0
0
0
0
0
63
0
0
66
0
<OFFSET CORRECTION
ENABLE– Ch B>
0
0
<SNRBoost
Enable –
Common/ Ch A
>
<TEST PATTERNS - Common/ Ch A >
<OFFSET PEDESTAL – Common/ Ch A >
0
0
0
0
0
0
68
<GAIN PROGRAMMABILITY – Ch B>
0 to 6 dB in 0.5 dB steps
<OFFSET CORRECTION TIME
CONSTANT – Ch B>
69
<SNRBoost Coeff 1 – Ch B>
<SNRBoost Coeff 2 – Ch B>
<FINE GAIN ADJUST – Ch B>
+0.001 dB to +0.134 dB, in 128 steps
6A
0
6C
0
0
0
0
75
0
0
0
0
76
0
0
0
0
0
0
<SNRBoost
Enable – Ch
B>
<TEST PATTERNS - Ch B>
<OFFSET PEDESTAL – Ch B>
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
A7 – A0 IN HEX
00
D7
D7
<RESET>
Software Reset
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
<SERIAL
READOUT>
<RESET>
1 Software reset applied – resets all internal registers and self-clears to 0.
D0
<SERIAL READOUT>
0 Serial readout disabled. SDOUT is forced high or low by the device (and not out in high impedance
state).
1 Serial readout enabled, Pin SDOUT functions as serial data readout. This mode is available only with
CMOS output interface. With LVDS interface, pin 56 becomes CLKOUTM.
A7 – A0 IN HEX
20
D2
D7
0
D6
0
D5
0
D4
0
D3
0
D2
<ENABLE LOW
SPEED MODE>
D1
0
D0
0
<ENABLE LOW SPEED MODE>
0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS.
1 Enable LOW SPEED mode for sampling frequencies <= 100 MSPS.
A7 – A0 IN HEX
3F
D6-D5
D7
0
D6
D5
<REF>
D4
0
D3
0
D2
0
D1
<STANDBY>
D0
0
<REF> Internal or external reference selection
01 Internal reference enabled
11 External reference enabled
D1
<STANDBY>
0 Normal operation
1 ADC is powered down for both channels. Internal references, output buffers are active. This results in
quick wake-up time from standby.
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A7 – A0 IN HEX
40
D3-D0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
POWER DOWN MODES
D0
<POWER DOWN MODES>
0000 Pins CTRL1, CTRL2 & CTRL3 determine power down modes.
1000 Normal operation
1001 Output buffer disabled for channel B
1010 Output buffer disabled for channel A
1011 Output buffer disabled for channel A and B
1100 Global power down
1101 Channel B standby
1110 Channel A standby
1111 Multiplexed mode, MUX– (only with CMOS interface)
Channel A and B data is multiplexed and output on DA10 to DA0 pins.
A7 – A0 IN HEX
41
D7
D7
<LVDS
CMOS>
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
<LVDS CMOS>
0 Parallel CMOS interface
1 DDR LVDS interface
20
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A7 – A0 IN HEX
44
D7
D6
D5
D4
<CLKOUT EDGE CONTROL>
Output clock edge control
D3
D2
D1
0
D0
0
LVDS Interface
D7-D5
<CLKOUT POSN> Output clock rising edge position
000, 100 Default output clock position (refer to timing specification table)
101 Rising edge shifted by + (4/26)Ts
110 Rising edge aligned with data transition
111 Rising edge shifted by – (4/26)Ts
D4-D2
<CLKOUT POSN> Output clock falling edge position
000, 100 Default output clock position (refer to timing specification table)
101 Falling edge shifted by + (4/26)Ts
110 Falling edge aligned with data transition
111 Falling edge shifted by – (4/26)Ts
CMOS INterface
D7-D5
<CLKOUT POSN> Output clock rising edge position
000, 100 Default output clock position (refer to timing specification table)
101 Rising edge shifted by + (4/26)Ts
110 Rising edge shifted by – (6/26)Ts
111 Rising edge shifted by – (4/26)Ts
D4-D2
<CLKOUT POSN> Output clock falling edge position
000, 100 Default output clock position (refer to timing specification table)
101 Falling edge shifted by + (4/26)Ts
110 Falling edge shifted by – (6/26)Ts
111 Falling edge shifted by – (4/26)Ts
A7 – A0 IN HEX
50
D6
D7
0
D6
<ENABLE INDEPENDENT
CHANNEL CONTROL>
D5
0
D4
0
D3
0
D2
D1
<DATA FORMAT>
2s complement or offset binary 0
D0
0
<ENABLE INDEPENDENT CHANNEL CONTROL>
0 Common control – both channels use common control settings for test patterns, offset correction,
gain, gain correction and SNRBoost functions. These settings can be specified in a single set of
registers.
1 Independent control – both channels can be programmed with independent control settings for test
patterns, offset correction and SNRBoost functions. Separate registers are available for each
channel.
D2-D1
<DATA FORMAT>
10 2s complement
11 Offset binary
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A7 – A0 IN HEX
51
52
D7-D3
D7
D6
0
0
D5
D4
<Custom Pattern Low>
D3
D2
0
<Custom Pattern High>
D1
0
D0
0
<CUSTOM LOW>
5 lower bits of custom pattern available at the output instead of ADC data
D5-D0
<CUSTOM HIGH>
6 upper bits of custom pattern available at the output instead of ADC data
A7 – A0 IN HEX
53
D6
D7
0
D6
<OFFSET CORRECTION ENABLE –
Common/Ch A>
Offset correction enable
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
<OFFSET CORRECTION ENABLE – Common/Ch A>
Offset correction enable control for both channels (with common control) or for channel A only (with
independent control).
0 Offset correction disabled
1 Offset correction enabled
See Offset Correction
22
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A7 – A0 IN HEX
55
D7-D4
D7
D6
D5
D4
<GAIN PROGRAMMABILITY – Common/Ch A>
D3
D2
D1
D0
<OFFSET CORR TIME CONSTANT – Common/Ch A>
Offset correction time constant
<GAIN PROGRAMMABILITY – Common/Ch A>
Gain control for both channels (with common control) or for channel A only (with independent
control).
0000 0 dB gain, default after reset
0001 0.5 dB gain
0010 1.0 dB gain
0011 1.5 dB gain
0100 2.0 dB gain
0101 2.5 dB gain
0110 3.0 dB gain
0111 3.5 dB gain
1000 4.0 dB gain
1001 4.5 dB gain
1010 5.0 dB gain
1011 5.5 dB gain
1100 6.0 dB gain
D3-D0
<OFFSET CORR TIME CONSTANT – Common/Ch A>
Correction loop time constant in number of clock cycles.
Applies to both channels (with common control) or for channel A only (with independent control).
0000 256 k
0001 512 k
0010 1 M
0011 2 M
0100 4 M
0101 8 M
0110 16 M
0111 32 M
1000 64 M
1001 128 M
1010 256 M
1011 512 M
A7 – A0 IN HEX
56
D7
D6
D5
D4
<SNRBoost Coeff 1 – Common/CH A>
D3
D2
D1
D0
<SNRBoost Coeff 2 – Common/CH A>
See SNR enhancement using SNRBoost
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A7 – A0 IN HEX
57
D7
0
D6
D5
D4
D3
D2
D1
D0
<FINE GAIN ADJUST – Common/Ch A> +0.001 dB to +0.134 dB, in 128 steps
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only
additive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmed
channel gain is:
Δ Channel Gain = 20 × log10[1 + (FINE GAIN ADJUST/8192)]
Note that the total device gain = ADC gain + Δ Channel gain. The ADC gain is determined by register bits <GAIN
PROGRAMMABILITY>
A7 – A0 IN
HEX
D7
D6
D5
D4
D3
D2
D1
D0
59
0
0
0
0
0
0
0
<SNRBoost Enable – CH A>
D0
<SNRBoost Enable – CH A>
SNRBoost control for both channels (with common control) or for channel A only (with independent
control).
0 SNRBoost disabled
1 SNRBoost enabled
A7 – A0 IN HEX
62
D2-D0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
<TEST PATTERNS>
D0
<TEST PATTERNS> Test Patterns to verify data capture.
Applies to both channels (with common control) for channel A only (with independent control)
000 Normal operation
001 Outputs all zeros
010 Outputs all ones
011
Outputs toggle pattern
Output data <D10:D0> alternates between 01010101010 and 10101010101 every clock cycle.
100
Outputs digital ramp
Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047.
101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)
110 Unused
111 Unused
24
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A7 – A0 IN HEX
63
D5-D0
D7
0
D6
0
D5
D4
D3
D2
<OFFSET PEDESTAL – Common/Ch A>
D1
D0
<OFFSET PEDESTAL – Common/Ch A>
When the offset correction is enabled, the final converged value after the offset is corrected will be
the ADC mid-code value. A pedestal can be added to the final converged value by programming
these bits. See "Offset Correction" in application section.
Applies to both channels (with common control) or for channel A only (with independent control).
011111
PEDESTAL = 31 LSB
011110
PEDESTAL = 30 LSB
011101
PEDESTAL = 29 LSB
....
000000
PEDESTAL = 0 LSB
....
111111
PEDESTAL = –1 LSB
111110
PEDESTAL = –2 LSB
....
100000
PEDESTAL = –32LSB
A7 – A0 IN HEX
66
D6
D7
0
D6
<OFFSET CORRECTION ENABLE
– CH B>
Offset correction enable
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
<OFFSET CORRECTION ENABLE – CH B>
Offset correction enable control for channel B (only with independent control).
0 offset correction disabled
1 offset correction enabled
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A7 – A0 IN HEX
68
D7-D4
D7
D6
D5
D4
<GAIN PROGRAMMABILITY – CH B>
D3
D2
D1
D0
<OFFSET CORR TIME CONSTANT – CH B>
Offset correction time constant
<GAIN – CH B> Gain programmability in 0.5 dB steps
Applies to channel B (only with independent control).
0000 0 dB gain, default after reset
0001 0.5 dB gain
0010 1.0 dB gain
0011 1.5 dB gain
0100 2.0 dB gain
0101 2.5 dB gain
0110 3.0 dB gain
0111 3.5 dB gain
1000 4.0 dB gain
1001 4.5 dB gain
1010 5.0 dB gain
1011 5.5 dB gain
1100 6.0 dB gain
D3-D0
<OFFSET CORR TIME CONSTANT – CH B> Time constant of correction loop in number of clock
cycles.
Applies to channel B (only with independent control)
0000 256 k
0001 512 k
0010 1 M
0011 2 M
0100 4 M
0101 8 M
0110 16 M
0111 32 M
1000 64 M
1001 128 M
1010 256 M
1011 512 M
A7 – A0 IN HEX
69
D7
D6
D5
<SNRBoost Coeff 1 – CH B>
D4
D3
D2
D1
<SNRBoost Coeff 2 – CH B>
D0
See SNR enhancement using SNRBoost
26
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A7 – A0 IN HEX
6A
D7
D6
D5
D4
D3
D2
D1
<GAIN CORRECTION – CH B> +0.001 dB to +0.134 dB, in 128 steps
D0
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only
additive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmed
channel gain is:
Δ Channel Gain = 20 × log10[1 + (FINE GAIN ADJUST/8192)]
Note that the total device gain = ADC gain + Δ Channel gain. The ADC gain is determined by register bits <GAIN
PROGRAMMABILITY>
A7 – A0 IN
HEX
D7
D6
D5
D4
D3
D2
D1
D0
6C
0
0
0
0
0
0
0
<SNRBoost Enable – CH B>
D0
<SNRBoost Enable – CH B>
SNRBoost control for channel B (only with independent control).
0 SNRBoost disabled
1 SNRBoost enabled
A7 – A0 IN HEX
75
D2-D0
D7
D6
D5
0
D4
0
D3
0
D2
D1
D0
<TEST PATTERNS – CH B>
<TEST PATTERNS> Test Patterns to verify data capture
Applies to both channels (with common control) for channel A only (with independent control)
000 Normal operation
001 Outputs all zeros
010 Outputs all ones
011
Outputs toggle pattern
Output data <D10:D0> alternates between 01010101010 and 10101010101 every clock cycle.
100
Outputs digital ramp
Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047.
101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)
110 Unused
111 Unused
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A7 – A0 IN HEX
76
D5-D0
D7
0
D6
0
D5
D4
D3
D2
D1
<OFFSET PEDESTAL – Common/Ch A>
D0
<OFFSET PEDESTAL – Ch B>
When the offset correction is enabled, the final converged value after the offset is corrected will be
the ADC mid-code value. A pedestal can be added to the final converged value by programming
these bits. See "Offset Correction" in application section.
Applies to both channels (with common control) or for channel A only (with independent control).
011111
PEDESTAL = 31 LSB
011110
PEDESTAL = 30 LSB
011101
PEDESTAL = 29 LSB
....
000000
PEDESTAL = 0 LSB
....
111111
PEDESTAL = –1 LSB
111110
PEDESTAL = –2 LSB
....
100000
28
PEDESTAL = –32LSB
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DB0M
NC
NC
DRGND
D R V DD
C LKO UTP
C LKOU TM
DA 10P
DA 10M
DA8P
DA8 M
DA 6 P
DA 6M
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
DRGND
DB0P
DRVDD
SDOUT
PIN CONFIGURATION (LVDS INTERFACE) – ADS62C17
1
48
DRVDD
DB 2M
2
47
DA4P
DB 2P
3
46
DA4M
PAD (Connected to DRGND)
4
45
DA 2 P
DB4P
5
44
DA 2M
DB 6M
6
43
DA0P
DB 6P
7
42
DA 0 M
DB8M
8
41
NC
DB8P
9
40
NC
DB10M
10
39
DRGND
DB10P
11
38
DRVDD
RESET
12
37
CTRL 3
SCLK
13
36
CTRL 2
SDATA
14
35
CTRL 1
SEN
15
34
AVDD
AVDD
16
25
26
27
28
29
30
31
AGND
AGND
IN P _ A
IN M_ A
AGND
32
AGND
24
C LKM
AGND
23
C LKP
IN M _ B
22
AGND
21
VCM
20
NC
19
IN P _ B
AVDD
18
AGND
AGND
DB4M
Figure 10. Pin Configuration
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PIN ASSIGNMENTS (LVDS INTERFACE) – ADS62C17
PIN
NUMBER
NO.
OF
PINS
PIN
TYPE
AVDD
16, 33, 34
3
I
Analog power supply
AGND
17,18,21,24,
27,28,31,32
8
I
Analog ground
CLKP, CLKM
25, 26
2
I
Differential clock input
INP_A, INM_A
29, 30
2
I
Differential analog input, Channel A
INP_B, INM_B
19, 20
2
I
Differential analog input, Channel B
23
1
IO
NAME
VCM
DESCRIPTION
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the
internal references.
RESET
12
1
I
Serial interface RESET input.
When using the serial interface mode, the user must initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
software reset option. Refer to Serial Interface section.
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK
and SEN are used as parallel control pins in this mode)
The pin has an internal 100 kΩ pull-down resistor.
SCLK
13
1
I
This pin functions as serial interface clock input when RESET is low.
It controls selection of internal or external reference when RESET is tied high. See
Table 5 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SDATA
14
1
I
Serial interface data input.
The pin has an internal 100 kΩ pull-down resistor.
The pin has no function in parallel interface mode and can be tired to ground.
SEN
15
1
I
This pin functions as serial interface enable input when RESET is low.
It controls selection of data format and interface type when RESET is tied high.
See Table 6 for detailed information.
The pin has an internal 100 kΩ pull-up resistor to AVDD
SDOUT
64
1
O
This pin functions as serial interface register readout, when the <SERIAL
READOUT> bit is enabled.
CTRL1
35
1
I
CTRL2
36
1
I
CTRL3
37
1
I
CLKOUTP
57
1
O
Differential output clock, true
CLKOUTM
56
1
O
Differential output clock, complement
DA0P, DA0M
2
O
Differential output data pair, D0 and 0 multiplexed – Channel A
DA2P, DA2M
2
O
Differential output data D1 and D2 multiplexed, true – Channel A
DA4P, DA4M
2
O
Differential output data D3 and D4 multiplexed, true – Channel A
DA6P, DA6M
2
O
Differential output data D5 and D6 multiplexed, true – Channel A
DA8P, DA8M
2
O
Differential output data D7 and D8 multiplexed, true – Channel A
DA10P, DA10M
2
O
Differential output data D9 and D10 multiplexed, true – Channel A
2
O
Differential output data pair, D0 and 0 multiplexed – Channel B
DB2P, DB2M
2
O
Differential output data D1 and D2 multiplexed, true – Channel B
DB4P, DB4M
2
O
Differential output data D3 and D4 multiplexed, true – Channel B
DB6P, DB6M
2
O
Differential output data D5 and D6 multiplexed, true – Channel B
DB8P, DB8M
2
O
Differential output data D7 and D8 multiplexed, true – Channel B
DB10P, DB10M
2
O
Differential output data D9 and D10 multiplexed, true – Channel B
4
I
Output buffer supply
When <SERIAL READOUT> = 0, this pin forces logic LOW & is not tri-stated.
DB0P, DB0M
DRVDD
30
Refer to
Figure 10
1,38,48,58
Digital control input pins. Together, they control SNRBoost control and power down
modes.
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PIN
NAME
DRGND
NC
NUMBER
NO.
OF
PINS
PIN
TYPE
39,49,59,PAD
4
I
DESCRIPTION
Output buffer ground
Refer to
Figure 10
Do not connect
DB0
NC
NC
NC
DRGND
DRVDD
CLKOUT
U NUSED
DA10
DA9
DA8
DA7
DA6
DA5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
DRGND
SDOUT
PIN CONFIGURATION (CMOS INTERFACE) – ADS62C17
DRVDD
1
48
DRVDD
DB1
2
47
DA4
DB2
3
46
DA3
PAD (Connected to DRGND)
4
45
DA2
DB 4
5
44
DA1
DB 5
6
43
DA0
DB 6
7
42
NC
DB 7
8
41
NC
DB 8
9
40
NC
DB 9
10
39
DRGND
DB10
11
38
DRVDD
RESET
12
37
CTRL 3
SCLK
13
36
CTRL 2
SDATA
14
35
CTRL 1
SEN
15
34
AVDD
AVDD
16
25
26
27
28
29
30
31
AGND
AGND
INP_A
INM_A
AGND
32
AGND
24
CLKM
AGND
23
CLKP
INM_B
22
AGND
21
VCM
20
NC
19
INP_B
AVDD
18
AGND
AGND
DB3
Figure 11. Pin Configuration
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PIN ASSIGNMENTS (CMOS INTERFACE) – ADS62C17
PIN
NUMBER
NO.
OF
PINS
PIN
TYPE
AVDD
16, 33, 34
3
I
Analog power supply
AGND
17,18,21,24,
27,28,31, 32
8
I
Analog ground
CLKP, CLKM
25, 26
2
I
Differential clock input
INP_A, INM_A
29, 30
2
I
Differential analog input, Channel A
INP_B, INM_B
19, 20
2
I
Differential analog input, Channel B
23
1
IO
NAME
VCM
DESCRIPTION
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
RESET
12
1
I
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
software reset option. Refer to SERIAL INTERFACE section.
In parallel interface mode, the user has to tie RESET pin permanently high.
(SDATA and SEN are used as parallel control pins in this mode)
The pin has an internal 100 kΩ pull-down resistor.
SCLK
13
1
I
This pin functions as serial interface clock input when RESET is low.
It controls selection of internal or external reference when RESET is tied high.
See Table 5 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SDATA
14
1
I
Serial interface data input.
The pin has an internal 100 kΩ pull-down resistor.
The pin has no function in parallel interface mode and can be tired to ground.
SEN
15
1
I
This pin functions as serial interface enable input when RESET is low.
It controls selection of data format and interface type when RESET is tied high.
See Table 6 for detailed information.
The pin has an internal 100 kΩ pull-up resistor to AVDD
SDOUT
64
1
O
This pin functions as serial interface register readout, when the <SERIAL
READOUT> bit is enabled.
CTRL1
35
1
I
CTRL2
36
1
I
CTRL3
37
1
I
CLKOUT
57
1
O
CMOS output clock
11
O
Channel A 11-bit ADC output data bits, CMOS levels
11
O
Channel B 11-bit ADC output data bits, CMOS levels
1,38,48,58
4
I
Output buffer supply
39,49,59,PAD
3
I
Output buffer ground
When <SERIAL READOUT> = 0, this pin forces logic LOW & is not tri-stated.
DA0, DA10
DB0-DB10
DRVDD
DRGND
NC
32
Refer to Figure 11
Refer to Figure 11
Digital control input pins. Together, they control SNRBoost control & power down
modes.
Do not connect
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TYPICAL CHARACTERISTICS
All plots are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, SNRBoost disabled, internal reference
mode, 0 dB gain, LVDS output interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
0
Ain = -1 dBFS,
SFDR = 83.8 dBc,
SNR = 67 dBFS,
SINAD = 66.9 dBFS,
THD = 83.3 dBc
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 12.
FFT for 60 MHz INPUT SIGNAL
0
Ain = -1 dBFS,
SFDR = 83.6 dBc,
SNR = 66.8 dBFS,
SINAD = 66.8 dBFS,
THD = 83 dBc
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 13.
FFT for 170 MHz INPUT SIGNAL
0
Ain = -1 dBFS,
SFDR = 74.2 dBc,
SNR = 66.3 dBFS,
SINAD = 65.7 dBFS,
THD = 73.5 dBc
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, SNRBoost disabled, internal reference
mode, 0 dB gain, LVDS output interface (unless otherwise noted)
FFT for 270 MHZ INPUT SIGNAL
0
Ain = -1 dBFS,
SFDR = 71.7 dBc,
SNR = 65.7 dBFS,
SINAD = 64.8 dBFS,
THD = 70.8 dBc
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 15.
FFT for 2-TONE INPUT SIGNAL
(INTERMODULATION DISTORTION)
0
Ain = -7 dBFS each tone,
Fin1 = 185 MHz,
Fin2 = 190 MHz,
AMD3 = 87.5 dBFS,
SFDR = 90 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 16.
FFT for 2-TONE INPUT SIGNAL
(INTERMODULATION DISTORTION)
0
Ain = -35 dBFS each tone,
Fin1 = 185 MHz,
Fin2 = 190 MHz,
IMD3 = 107 dBFS,
SFDR = 104 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 17.
34
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, SNRBoost disabled, internal reference
mode, 0 dB gain, LVDS output interface (unless otherwise noted)
FFT with SNRBOOST ENABLED
for
5MHz, 10MHZ, and 15 MHz BANDWIDTHS, Fin = 150 MHz, Fcenter = Fs/4
0
Ain = -36 dBFS,
SNRBoost Coeff1 = 0x0,
SNRBoost Coeff2 = 0x0,
SFDR = 51.8 dBc,
THD = 51 dBc,
SNR over 5 M BW (47.5 M to 52.5 M) = 88.4 dBFS,
SNR over 10 M BW (45 M to 55 M) = 84.5 dBFS,
SNR over 15 M BW (42.5 M to 57.5 M) = 82.5 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 18.
FFT with SNRBOOST ENABLED
for
20 MHz BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4
0
Ain = -36 dBFS,
SNRBoost Coeff1 = 0xF,
SNRBoost Coeff2 = 0x1,
SFDR = 52 dBc,
THD = 52.8 dBc,
SNR over 20 M BW (40 M to 60 M) = 80.9 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 19.
FFT with SNRBOOST ENABLED
for
30MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4
0
Ain = -36 dBFS,
SNRBoost Coeff1 = 0xD,
SNRBoost Coeff2 = 0x3,
SFDR = 52.7 dBc,
THD = 53.1 dBc,
SNR over 30 M BW (35 M to 65 M) = 78.4 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, SNRBoost disabled, internal reference
mode, 0 dB gain, LVDS output interface (unless otherwise noted)
FFT with SNRBOOST ENABLED
for
40MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4
0
Ain = -36 dBFS,
SNRBoost Coeff1 = 0xD,
SNRBoost Coeff2 = 0x3,
SFDR = 54.4 dBc,
THD = 53.8 dBc,
SNR over 40 M BW (30 M to 70 M) = 75.8 dBFS
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
f - Frequency - MHz
70
80
90
100
Figure 21.
SNR with SNRBOOST ENABLE
and DISABLED
90
88
SFDR ACROSS INPUT FREQUENCY
90
Ain = -36 dBFS,
Fin = 150.2 MHz,
SNRBoost Coeff2 = 0x1,
Optimized for 20 MHz Bandwidth,
SNR over 20 M BW (SNRBoost Disabled) = 73.7 dBFS,
SNR over 20 M BW (SNRBoost Enabled) = 80.9 dBFS
86
SNRBoost Enabled
82
SFDR - dBc
SNR - dBFS
86
84
82
SNRBoost Disabled
78
74
80
70
78
SNR
SNR
SNR
SNR
SNR
(37.5 M to 42.5 M) (42.5 M to 47.5 M) (47.5 M to 52.5 M) (52.5 M to 57.5 M) (57.5 M to 62.5 M)
66
0
Figure 22.
36
100
200
300
400
Input Frequency - MHz
500
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, SNRBoost disabled, internal reference
mode, 0 dB gain, LVDS output interface (unless otherwise noted)
SNR ACROSS INPUT FREQUENCY
SFDR ACROSS GAIN
68
92
Gain = 6 dB
88
67
Gain = 4 dB
66
SFDR - dBc
SNR - dBFS
84
65
Gain = 5 dB
80
76
64
Gain = 3 dB
72
Gain = 2 dB
Gain = 1 dB
63
68
0
100
200
300
400
Input Frequency - MHz
500
0
200
300
400
Input Frequency - MHz
500
Figure 24.
Figure 25.
SINAD SCROSS GAIN
PERFORMANC