TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 D D D D D D D D D D D 8-Bit Resolution 2.7 V to 3.6 V VCC Easy Microprocessor Interface or Standalone Operation Operates Ratiometrically or With VCC Reference 4- or 8-Channel Multiplexer Options With Address Logic Input Range 0 V to VCC With VCC Reference Remote Operation With Serial Data Link Inputs and Outputs Are Compatible With TTL and MOS Conversion Time of 32 µs at f(CLK) = 250 kHz Functionally Equivalent to the ADC0834 and ADC0838 at 3-V Supply Without the Internal Zener Regulator Network Total Unadjusted Error . . . ±1 LSB TLV0834 . . . D OR N PACKAGE (TOP VIEW) NC CS CH0 CH1 CH2 CH3 DGTL GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC DI CLK SARS DO REF ANLG GND TLV0838 . . . DW OR N PACKAGE (TOP VIEW) CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGTL GND description These devices are 8-bit successive-approximation analog-to-digital converters, each with an input-configurable multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is readily available from the factory. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC NC CS DI CLK SARS DO SE REF ANLG GND The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software configured for single-ended or differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution. The TLV0834C and TLV0838C are characterized for operation from 0°C to 70°C. The TLV0834I and TLV0838I are characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) SMALL OUTLINE (DW) 0°C to 70°C TLV0834CD TLV0838CDW TLV0834CN TLV0838CN – 40°C to 85°C TLV0834ID TLV0838IDW TLV0834IN TLV0838IN PLASTIC DIP (N) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CS CLK CS DI (see Note A) SARS R D S 5-Bit Shift Register R CLK SELECT0 SELECT1 TLC0838 Only SE POST OFFICE BOX 655303 TLC0834 TLC0838 ODD\ EVEN SGL\ DIF START To Internal Circuits CLK • DALLAS, TEXAS 75265 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog MUX S Time Delay EN R CS Comparator CS CS R R CS EN REF Ladder and Decoder SAR Logic and Latch Bits 0–7 One Shot CS CLK Bits 0–7 Bit 1 MSB First NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high. LSB First 9-Bit Shift Register EOC R CLK DO D TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL Start Flip-Flop CLK SLAS147 – SEPTEMBER 1996 2 functional block diagram TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 functional description The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–) polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. The common input on the TLV0838 can be used for a pseudo-differential input. In this mode, the voltage on the common input is considered to be the negative differential input for all channel inputs. This voltage can be any reference potential common to all channel inputs. Each channel input can then be selected as the positive differential input. This feature is useful when all analog circuits are biased to a potential other than ground. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is disabled for the duration of the conversion. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low. The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 sequence of operation TLV0834 1 2 3 4 5 7 6 10 11 12 13 15 14 18 19 20 21 CLK tconv CS tsu Start Bit +Sign SELECT Bit Bit 1 SGL ODD Don’t Care DI DIF 1 EVEN Hi-Z SARS MUX Settling Time MSB-First Data DO Hi-Z LSB-First Data Hi-Z LSB MSB 7 6 2 1 0 MSB 1 2 6 TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS CHANNEL NUMBER CH0 CH1 CH2 CH3 ODD/EVEN SELECT BIT 1 SGL/DIF + – L L L + – L H L – + L L H – + L H H + H L L + H H L + H L H + H H H H = high level, L = low level, – or + = terminal polarity for the selected input channel 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 sequence of operation TLV0838 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CLK tconv tsu CS MUX Addressing tsu + Sign SEL SEL Start Bit Bit Bit 1 Bit SGL ODD 0 Don’t Care DI DIF EVEN 1 0 Hi-Z Hi-Z SARS SE LSB-First Data MSB-First Data Hi-Z DO Hi-Z 7 MSB LSB MSB 6 2 1 0 1 2 3 4 5 6 7 SE Used to Control LSB-First Data SE MUX Settling Time MSB-First Data DO LSB Held MSB 7 LSB-First Data MSB LSB 6 2 1 POST OFFICE BOX 655303 0 1 • DALLAS, TEXAS 75265 2 3 4 5 6 7 5 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS SELECTED CHANNEL NUMBER SELECT 0 SGL/DIF ODD/EVEN 1 0 CH0 CH1 L L L L + – L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H – 1 CH2 CH3 + – 2 CH4 CH5 + – 3 CH6 CH7 + – – + COM + – + – + + – + – + – + – + – + – + – + – H = high level, L = low level, – or + = polarity of external input absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC+ 0.3 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 recommended operating conditions Supply voltage, VCC (see clock frequency operating conditions) High-level input voltage, VIH MIN NOM MAX 2.7 3.3 3.6 2 Clock frequency, f(CLK) VCC = 2.7 V VCC = 3.3 V Clock duty cycle (see Note 2) V V Low-level input voltage, VIL Clock frequency, f(CLK) UNIT 0.8 V 10 250 kHz 10 600 kHz 40% 60% Pulse duration, CS high, twH(CS) 220 ns Setup time, CS low, SE low, or data valid before CLK↑, tsu 350 ns Hold time, data valid after CLK↑, th free air temperature, temperature TA Operating free-air 90 C suffix I suffix ns 0 70 – 40 85 °C NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs. electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted) digital section PARAMETER TEST CONDITIONS† VCC = 3 V, VCC = 3 V, IOH = – 360 µA IOH = – 10 µA VCC = 3 V, VIH = 3.6 V IOL = 1.6 mA VOH High level output voltage High-level VOL IIH Low-level output voltage IIL IOH Low-level input current High-level output (source) current VIL = 0 At VOH, DO = 0 V, TA = 25°C IOL Low-level output (sink) current A t VOL, DO = VCC, TA = 25°C IOZ High-impedance-state output g current (DO or SARS) VO = 3.3 V, VO = 0, Ci Input capacitance High-level input current TA = 25°C TA = 25°C MIN C SUFFIX TYP‡ MAX MIN 2.8 2.4 2.9 2.8 I SUFFIX TYP‡ MAX V 0.4 V 0.005 0.34 1 0.005 1 µA – 0.005 –1 – 0.005 –1 µA – 6.5 – 15 – 6.5 – 15 8 16 8 16 mA mA 0.01 3 0.01 3 – 0.01 –3 – 0.01 –3 5 Co Output capacitance 5 † All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified). ‡ All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 µA pF pF 7 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 analog and converter section TEST CONDITIONS† PARAMETER VIC Common-mode input voltage g See Note 3 On channel II( I(stdby) tdb ) Off channel Standby input current (see Note 4) On channel Off channel ri(REF) MIN TYP‡ MAX – 0.05 to VCC + 0.05 V VI = 3.3 V VI = 0 1 –1 VI = 0 VI = 3.3 V Input resistance to REF UNIT –1 µA 1 1.3 2.4 5.9 TYP‡ MAX kΩ total device PARAMETER MIN UNIT ICC Supply current 0.2 0.75 mA † All parameters are measured under open-loop conditions with zero common-mode input voltage. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. NOTES: 3. When channel IN – is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of 3.25 V for all variations of temperature and load. 4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is in a high or low steady-state condition. operating characteristics, VCC = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise noted) TEST CONDITIONS§ PARAMETER Supply-voltage variation error Total unadjusted error (see Note 5) Common-mode error MSB-first data tpd d Propagation g delay y time,, output data after CLK↓ (see Note 6) tdi dis Output disable time time, DO or SARS after CS↑ tconv Conversion time (multiplexer-addressing time not included) LSB-first data MIN TYP MAX UNIT VCC = 3 V to 3.6 V Vref = 3.3 V, TA = MIN to MAX ± 1/16 ± 1/4 LSB ±1 LSB Differential mode ± 1/16 ± 1/4 LSB 500 CL = 100pF 200 CL = 10 pF, RL = 10 kΩ 80 CL = 100 pF, RL = 2 kΩ 250 8 ns ns clock periods § All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response time. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION VCC CLK 50% 50% GND tsu tsu VCC CS 0.4 V GND th th VCC 2V 2V DI 0.4 V 0.4 V GND Figure 1. Data-Input Timing VCC CLK 50% 50% GND tpd tpd VCC DO 50% 50% GND tsu VCC 50% SE GND Figure 2. Data-Output Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION VCC Test Point S1 RL From Output Under Test CL (see Note A) S2 LOAD CIRCUIT tr tr VCC CS 50% 90% 10% CS 10% GND S1 open S2 closed VCC 90% DO and SARS S1 closed S2 open GND VCC 10% VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Output Disable Time Test Circuit and Voltage Waveforms 10 GND tdis tdis DO and SARS VCC 90% 50% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GND TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 TYPICAL CHARACTERISTICS LINEARITY ERROR vs REFERENCE VOLTAGE UNADJUSTED OFFSET ERROR vs REFERENCE VOLTAGE 1.5 VCC = 3.3 V f(CLK) = 250 kHz TA = 25°C VI(+) = VI(–) = 0 V 14 1.25 12 E L – Linearity Error – LSB EO(unadj) – Unadjusted Offset Error – LSB 16 10 8 6 4 1.0 0.75 0.5 0.25 2 0 0.01 0.1 1 0 10 1 0 Figure 4 4 Figure 5 LINEARITY ERROR vs CLOCK FREQUENCY LINEARITY ERROR vs FREE-AIR TEMPERATURE 2.0 0.5 Vref = 3.3 V VCC = 3.3 V 1.8 Vref = 3.3 V f(CLK) = 250 kHz 1.6 E L – Linearity Error – LSB E L – Linearity Error – LSB 3 Vref – Reference Voltage – V Vref – Reference Voltage – V 0.45 2 0.4 0.35 0.3 1.4 85°C 1.2 1 0.8 25°C 0.6 0.4 – 40°C 0.2 0.25 – 50 – 25 0 25 50 75 100 TA – Free-Air Tempertature – °C 0 0 100 200 300 400 500 600 700 800 f(CLK) – Clock Frequency – kHz Figure 6 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 TYPICAL CHARACTERISTICS TLV0831 TLV0831 SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs CLOCK FREQUENCY 0.3 0.5 f(CLK) = 250 kHz CS = High VCC = 3.3 V TA = 25°C 0.4 I CC – Supply Current – mA I CC – Supply Current – mA VCC = 3.6 V VCC = 3.3 V 0.2 VCC = 3 V 0.3 0.2 0.1 0.1 – 50 – 25 0 25 50 75 0 100 0 TA – Free-Air Temperature — °C 100 200 Figure 9 OUTPUT CURRENT vs FREE-AIR TEMPERATURE 16.5 VCC = 3.3 V I O – Output Current – mA 16 IOL (DO = 3.3 V) 15.5 – IOH (DO = 0 V) 15 – IOH (DO = 2.4 V) 14.5 IOL (DO = 0.4 V) – 25 0 25 50 TA – Free-Air Temperature – °C Figure 10 12 400 f(CLK) – Clock Frequency – kHz Figure 8 14 – 50 300 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 100 500 TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147 – SEPTEMBER 1996 Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS 1 0.5 0 Vref = 3.3 V TA = 25°C F(CLK) = 250 kHz VDD = 3.3 V – 0.5 –1 0 32 64 96 128 160 192 224 256 224 256 Output Code Figure 11. Differential Nonlinearity With Output Code Integral Nonlinearity – LSB 1 Vref = 3.3 V TA = 25°C F(CLK) = 250 kHz VDD = 3.3 V 0.5 0 – 0.5 –1 0 32 64 96 128 160 192 Output Code Figure 12. Integral Nonlinearity With Output Code Total Unadjusted Error – LSB 1 Vref = 3.3 V TA = 25°C F(CLK) = 250 kHz VDD = 3.3 V 0.5 0 – 0.5 –1 0 32 64 96 128 160 192 224 256 Output Code Figure 13. Total Unadjusted Error With Output Code POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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