Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Document Title 128M: 8M x 16 Mobile SDRAM Revision History Revision No. Date History 0.0 Jun 4, 2007 Initial Draft 0.1 Nov 8, 2007 - Table9 Operating AC Parameter updated for setup & hold time - Table9 Operating AC Parameter updated for tWR - Table2 Bonding Pad Location and Identification table deleted - Signal names unified to /CK, /CS, /RAS, /CAS, /WE respectively (Ex.) CK#, CK, CKB unified to /CK - Release date for Revision 0.0 corrected - IDD6 value in Table 6 & Table 13 modified Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial CooperationB/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : www.emlsi.com The attached datasheets provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM 128M : 8M x 16bit Mobile SDRAM FEATURES · · · · 1.8V power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. · CAS latency (1, 2 & 3). · Burst length (1, 2, 4, 8 & Full page). · Burst type (Sequential & Interleave). · All inputs are sampled at the positive going edge of the system clock. · Burst read single-bit write operation. · EMRS cycle with address key programs. · PASR(Partial Array Self Refresh). · DS (Driver Strength) · Internal auto TCSR (Temperature Compensated Self Refresh) · Deep power-down(DPD) mode. · DQM for masking. · Auto refresh. · 64ms refresh period (4K cycle). · Extended Temperature Operation (-25℃ ~ 85℃). GENERAL DESCRIPTION This EM series is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,098,152 words by 16bits, fabricated with EMLSI’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. Table 1: ORDERING INFORMATION Part No. Max Freq. EM828164PA-60 166㎒(CL3), 111㎒(CL2) EM828164PA-75 133㎒(CL3), 83㎒(CL2) EM828164PA-90 111㎒(CL3), 66㎒(CL2) Interface Package LVCMOS Wafer Biz. NOTE : 1. EMLSI are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in emlsi electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. 2 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 2: Pad Description Symbol Type Descriptions Input Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable : CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), ACTIVE POWER-DOWN(row ACTIVE in any bank), DEEP POWER-DOWN (all banks idle), or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. /CS Input Chip Select : /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. /RAS, /CAS, /WE Input Command Inputs: /CAS, /RAS, and /WE(along with /CS) define the command being entered. LDQM, UDQM Input Input/Output Mask : DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. LDQM corresponds to DQ0DQ7, UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. These balls also select between the mode register and the extended mode register. Input Address Inputs: A0-A11 are sampled during the ACTIVE command(row address A0-A11) and READ/ WRITE command(column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged(A10 HIGH) or bank selected by BA0, BA1(LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. CLK A0 - A11 DQ0-DQ15 I/O Data Bus: Input / Output VDD Supply Power Supply VSS Supply Ground VDDQ Supply I/O Power Supply VSSQ Supply I/O Ground 3 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Device Operation Simplified State Diagram Power On Power applied Deep Power Down DPDSX Precharge All Banks Self Refresh DPDS REFSX REFS Idle All banks precharged MRS MRS EMRS Auto Refresh REFA CKEL CKEH Active Power Down ACT Precharge Power Down Row Active Burst Stop CKEH CKEL Burst Stop READ WRITE BST BST WRITEA WRITE WRITE READ READA READ WRITE WRITEA READ READA WRITEA READA READ A WRITE A PRE PRE PRE PRE Precharge PREALL Automatic Sequence Command Sequence ACT = Active EMRS = Ext. Mode Reg. Set REFSX = Exit Self Refresh BST = Burst Terminate MRS = Mode Register Set READ = Read w/o Auto Precharge CKEL = Enter Power-Down PRE = Precharge READA = Read with Auto Precharge CKEH =Exit Power-Down PREALL = Precharge All Banks WRITE = Write w/o Auto Precharge DPDS = Enter Deep Power-Down REFA = Auto Refresh WRITEA = Write with Auto Precharge DPDSX = Exit Deep Power-Down REFS = Enter Self Refresh 4 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM FUNCTIONAL BLOCK DIAGRAM REFRESH COUNTER 12 BANK MEMORY ROW ADDRESS DECODER ARRAY 4,096 (4,096 x 512 x 16) A0 - A11 BA0, BA1 14 ADDRESS REGISTER x4 x4 ○ DQ0 DQ15 ○ LDQM UDQM 16 512 2 16 2 SENSE AMPLIFIERS 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 x4 12 COLUMN ADDRESS DECODER x4 DATA INPUT REGISTER I/O GATING DM MASK LOGIC READ DATA LATCH WRITE DRIVERS 16 16 9 2 14 CKE ○ CLK ○ /CS ○ /RAS ○ /CAS ○ /WE ○ CONTROL LOGIC COMMAND DECODE STANDARD MODE REGISTER EXTENDED MODE REGISTER 5 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Electrical Specifications Table 3: ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN,VOUT -0.5 ~ 2.5 V VDD, VDDQ -0.5 ~ 2.5 V TSTG -55 ~ +150 ℃ Power dissipation PD 1.0 W Short circuit current IOS 50 ㎃ Voltage on any pin relative to VSS Voltage on VDD and VDDQ supply relative to VSS Storage temperature NOTE : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Table 4: DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25oC~ 85oC for Extended) Parameter Symbol Min Typ Max Unit Note VDD 1.7 1.8 1.95 V 1 VDDQ 1.7 1.8 1.95 V 1 Input logic high voltage VIH 0.8 x VDDQ 1.8 VDDQ + 0.3 V 2 Input logic low voltage VIL -0.3 0 0.3 V 3 Output logic high voltage VOH 0.9 x VDDQ - - V IOH = -0.1mA Output logic low voltage VOL - - 0.1 x VDDQ V IOL = 0.1mA ILI -2 - 2 ㎂ 4 Note Supply voltage Input leakage current NOTE : 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VIH (max) = 2.2V AC. The overshoot voltage duration is ≤ 3ns. 3. VIL (min) = -0.1V AC. The undershoot voltage duration is ≤ 3ns. 4. Any input 0V ≤ VIN ≤ VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. Table 5: CAPACITANCE (VDD = 1.8V, Pin TA = 23℃, f=1㎒, Vref = 0.9V ± 50mV) Symbol Min Max Unit CCLK 1.5 3.5 ㎊ CIN 1.5 3.0 ㎊ Address CAD0 1.5 3.0 ㎊ DQ0 ~ DQ15 COUT 2.0 4.5 ㎊ Clock /RAS, /CAS, /WE, /CS, CKE, DQM 6 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 6: DC CHARACTERISRICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25oC~ 85oC for Extended) Version Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) -75 -90 50 40 35 Burst length = 1 tRC ≥ tRC(min) Io = 0mA IDD2P CKE ≤ VIL(max), tcc =10ns 0.3 IDD2PS CKE & CLK ≤ VIL(max), tcc = ∞ 0.3 IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min), tcc = 10ns Input signals are changed one time during 20ns 10 IDD2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞ Input signals are stable 1 IDD3P CKE ≤ VIL(max), tcc = 10ns 5 IDD3PS CKE & CLK ≤ VIL(max), tcc = ∞ 1 IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min), tcc = 10ns Input signals are changed one time during 20ns 20 mA IDD3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞ Input signals are stable 10 mA mA mA mA mA IDD4 Refresh Current IDD5 Deep Power Down Current Unit -60 IDD1 Operationg Current (Burst Mode) Self Refresh Current Test Condition IDD6 IDD8 mA Io = 0mA Page burst 4banks activated tCCD = 2clks 80 tRFC ≥ tRFC(min) 90 80 45 mA CKE ≤ 0.2v 90 85 TCSR Range 45*1 85 Full Array 120 200 1/2 of Full Array 120 160 1/4 of Full Array 100 140 CKE ≤ 0.2v 10 mA °C µA µA NOTE : 1. It has ± 5℃ tolerance. 2. Refresh period is 64ms. 3. Internal TCSR can be supported. In extended Temp : 45°C/Max 85°C 4. DPD (Deep Power Down) function is an optional feature and it will be enabled upon request. Please contact EMLSI for more information. 5. Unless otherwise noted, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ) 7 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 7: AC OPERATING TEST CONDITIONS (VDD = 1.7V ~ 1.95V, TA = -25oC~ 85oC for Extended) Parameter Value Unit 0.8 × VDDQ / 0.2 × VDDQ V 0.5 × VDDQ V 1.0 V/ns Output timing measurement reference level 0.5 × VDDQ V Output load condition See Figure 2 AC input levels(Vih/Vil) Input timing measurement reference level Input rise and fall time Note 1.8V Vtt=0.5 × VDDQ 13.9㏀ 50Ω VOH (DC) = 0.9 x VDDQ, IOH = -0.1㎃ Output 10.6㏀ VOL (DC) = 0.1 x VDDQ, IOL = 0.1 ㎃ Z0=50Ω Output 20㎊ 20㎊ Figure 2. AC Output Load Circuit Figure 1. DC Output Load Circuit 8 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 8: OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Symbol Parameter -60 -75 -90 Unit Note Min Max Min Max Min Max DQ output access time from CLK tAC Clock high-level width tCH 0.45 0.55 0.45 0.55 Clock low-level width tCL 0.45 0.55 0.45 0.55 Clock half period tHP min (tCL,tCH) min (tCL,tCH) min (tCL,tCH) ns 6 7.5 9 ns 9 12 15 ns CL = 3 5.4 5.4 7.0 ns 1,2 0.45 0.55 tCK 3 0.45 0.55 tCK 3 tCK Clock cycle time CL = 2 1 DQ input setup time tDS 2.5 2.5 2.5 ns DQ input hold time tDH 1.0 1.0 1.0 ns Address input setup time tAS 2.5 2.5 2.5 ns 3 Address input hold time tAH 1.0 1.0 1.0 ns 3 DQ low-impedance time from CLK tLZ 1.0 1.0 1.0 ns 2 DQ high-impedance time from CLK tHZ 6.0 6.0 7.0 ns MODE REGISTER SET command period tMRD 2 2 2 tCK CKE hold time tCKH 1 1 1 ns CKE setup time tCKS 1.5 1.5 2.5 ns /CS, /RAS, /CAS, /WE, DQM hold time tCMH 1.0 1.0 1.0 ns /CS, /RAS, /CAS, /WE, DQM setup time tCMS 2.5 2.5 2.5 ns Data-out hold time tOH 2.5 2.5 2.5 ns 2 ACTIVE to PRECHARGE command period tRAS 50 ns 4 ACTIVE to ACTIVE command period tRC 72.5 72.5 74 ns 4 AUTO REFRESH to ACTIVE / AUTO REFRESH command period tRFC 80 80 90 ns 7 ACTIVE to READ or WRITE delay tRCD 22.5 22.5 24 ns 4 tRP 18 22.5 24 ns 4 ACTIVE bank A to ACTIVE bank b delay tRRD 2 2 2 tCK 4 READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK WRITE recovery time tWR 15 15 15 ns Auto precharge write recovery + precharge time tDAL tWR+tRP tWR+tRP tWR+tRP Self refresh exit to next valid command delay tXSR 90 112.5 120 Exit power down to next valid command delay tXP tCK+tCKS tCK+tCKS tCK+tCKS PRECHARGE command period 100,000 9 50 100,000 50 100,000 5 ns Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM NOTE : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered. i.e.,[(tr + tf)/2-1]ns should be added to the parameter. 4. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 5. Minimum delay is required to completed write. 6. Maximum burst refresh cycle : 8 7. All parts allow every cycle column address change. Functional Description In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power should be applied to VDD and VDDQ simultaneously. Once the power is applied to VDD and VDDQ, and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a DESELECT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, DESELECT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one DESELECT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. 10 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Mode Register Definition In order to achieve low power consumption, there are two mode registers in the mobile component, mode register and extended mode register. The mode register defines the specific mode of operation of the SDRAM, including burst length, burst type, CAS latency, operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, A7 and A8 specify the operating mode, A9 specifies the write burst mode. A10 and A11 should be set to zero. BA0 and BA1 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting A7 and A8 to zero; the other combinations of values for A7 and A8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When A9 = 0, the burst length programmed via A0-A2 applies to both READ and WRITE bursts; when A9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. 11 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Extended Mode Register The extended mode register controls functions specific to low power operation. These additional functions include drive strength, temperature compensated self refresh, and partial array self refresh. This device has default values for the extended mode register (if not programmed, the device will operate with the default values . PASR = Full Array, DS = Full Drive). Temperature Compensated Self Refresh On this version of the Mobile SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Programming of the temperature compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature. Partial Array Self Refresh For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. Low Power SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array BA1=0 BA1=0 BA0=0 BA0=1 BA1=0 BA1=0 BA0=0 BA0=1 BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1 - Full Array - 1/4 Array - 1/2 Array Partial Self Refresh Area Output Driver Strength Because the Mobile SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of the DQ outputs. 12 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 9: Mode Register Field Table to Program modes Register Programmed with Normal MRS Address BA0 ~ BA1 A11 ~ A10/AP A9 Function "0" Setting for Normal MRS RFU*1 W.B.L A8 A7 A6 Operating Mode A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length NOTE : 1. RFU(Reserved for future use) should stay “0” during MRS cycle. Table 10: Normal Mode Operating Mode A8 A7 CAS Latency Burst Type Burst Length Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved A9 Length Mode Select BA1 0 0 Burst 1 1 0 Reserved 1 Single Bit 1 1 1 Reserved BA0 0 Mode Setting for Normal MRS Mode Register Set 0 1 2 3 4 5 6 7 8 CLK *1 Precharge All Banks Command tCK Any Command Mode Register Set tRP*2 2 Clock min. NOTE : 1. MRS can be issued only at all bank precharge state. 2. Minimum tRP is required to issue MRS command. 13 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 11: Register Programmed with Extended MRS Address BA1 Function BA0 A11 ~ A10/AP A9 A8 A7 A6 RFU*1 Mode Select A5 A4 A3 A2 RFU*1 DS A1 A0 PASR NOTE : 1. RFU(Reserved for future use) should stay “0” during MRS and EMRS cycle. Table 12: EMRS for PASR(Partial Array Self Refresh) & DS(Driver Strength) Mode Select Driver Strength PASR BA1 BA0 MODE A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Array 0 0 Normal MRS 0 0 Full 0 0 0 Full Array 0 1 Reserved 0 1 1/2 0 0 1 1/2 of Full Array 1 0 EMRS for SDRAM 1 0 1/4 0 1 0 1/4 of Full Array 1 1 Reserved 1 1 1/8 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Reserved Address A11~A10/AP A9 A8 A7 A4 A3 0 0 0 0 0 0 14 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 13: Internal Temperature Compensated Self Refresh (TCSR) Self Refresh Current (Icc 6) Temperature Range Unit Full Array 1/2 of Full Array 1/4 of Full Array Max 85℃ 200 160 140 Max 45℃ 120 120 100 ㎂ NOTE : 1. In order to save power consumption, Low power SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 85℃, Max 45℃ 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCRS is ignored. 3. It has +/- 5 ℃ tolerance. BURST SEQUENCE Table 14: BURST LENGTH = 2 Initial Address Sequential Interleave A0 0 0 1 0 1 1 1 0 1 0 Table 15: BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 Table 16: BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 15 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Commands DESELECT The DESELECT function(/CS HIGH) prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (/CS is LOW ). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A11, BA0, BA1. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The values of the mode register and extended mode register will be retained even when exiting deep power-down. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the CASe where only 1 bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. 16 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to /CAS BEFORE-/RAS (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command . The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. Auto Refresh CK Command CKE = High Auto PRE CMD Refresh tRFC tRP 17 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down, as long as power is not completely removed from the SDRAM. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. Self Refresh CLK Command Self Refresh Active CKE = High CMD tXSR tCKS DEEP POWER-DOWN The operating mode deep power-down achieves maximum power reduction by eliminating the power of the whole memory array of the device. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then /CS and /WE held LOW with /RAS and /CAS held HIGH at the rising edge of the clock, while CKE is LOW. This mode is exited by asserting CKE HIGH. 18 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Operations Bank/Row Activation The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock(CLK). The SDRAM has four independent banks, so two bank select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any READ or WRITE operation is executed. The delay from the Bank Activation command to the first READ or WRITE command must meet or exceed the minimum of /RAS to /CAS delay time(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min). Bank Activation Command Cycle 0 2 1 3 Tn Bank A Col. Addr. Bank B Row Addr. Write with Auto Precharge Bank B Activate Tn+1 Tn+2 CLK Address Bank A Row Address Command Bank A Activate /RAS - /CAS delay time(tRCD) NOP NOP Bank A Row. Addr. /RAS - /RAS delay time(tRRD) Row Cycle Time(tRC) 19 NOP Bank A Activate : Don't care Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READs READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ comand. Each subsequent dataout element will be valid by the next positive clock edge. Upon completion of a burst, assuming no other comands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either CASe, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ comand should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. Burst Read Operation < Burst Length=4, CAS Latency=2, 3) > 1 0 2 3 5 4 6 8 7 CLK Command CL2 DQ’s CL3 DQ’s READ NOP NOP NOP NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 Dout 0 Dout 1 Dout 2 NOP NOP Dout 3 DQM Masking < Burst Length = 4 > 1 0 2 3 5 4 6 8 7 CLK Command READ NOP NOP NOP NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 NOP NOP DQM CL3 DQ’s 20 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Read Interrupted by a Read < Burst Length=4, CAS Latency = 2 > 0 1 READ A READ B 2 3 5 4 6 8 7 CLK Command CL2 DQ’s NOP NOP NOP NOP NOP Dout a0 Dout b0 Dout b1 Dout b2 Dout b3 NOP NOP The DQM input is used to avoid I/O contention. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Read Interrupted by a Write < Burst Length=4, CAS Latency = 3 > 1 0 2 3 5 4 6 8 7 CLK Command READ NOP NOP NOP WRITE NOP NOP NOP Dout 0 Din 0 Din 1 Din 2 Din 3 NOP DQM CL3 DQ’s Read Interrupted by a Precharge < Burst Length=4, CAS Latency = 2 > 1 0 2 3 5 4 6 8 7 CLK 1tCK Command CL2 DQ’s READ Precharge NOP NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 NOP NOP NOP Interrupted by precharge 21 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITEs Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank or each subsequent WRITE may be performed to a different bank. Burst Write Operation < Burst Length = 4 > 1 0 2 3 5 4 6 8 7 CLK Command NOP DQ’s WRITE A NOP NOP NOP WRITE B NOP NOP NOP Din a0 Din a1 Din a2 Din a3 Din b0 Din b1 Din b2 Din b3 Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. Write Interrupted by a Read < Burst Length = 4, CAS Latency = 2 > 1 0 2 3 5 4 6 8 7 CLK Command NOP DQ’s WRITE NOP NOP Din 0 Din 1 Din 2 READ NOP NOP NOP Dout 0 Dout 1 NOP Write Interrupted by a Write < Burst Length = 4 > 1 0 2 3 5 4 6 8 7 CLK 1tCK Command DQ’s NOP WRITE A WRITE B NOP NOP NOP Din a0 Din b0 Din b1 Din b2 Din b3 22 NOP NOP NOP Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. DQM Masking < Burst Length = 4 > 1 0 5 4 3 2 6 7 8 CLK Command NOP DQ’s WRITE NOP NOP NOP NOP Din 0 Din 1 Din 2 Din 3 NOP NOP NOP DQM Masked by DQM = H In the CASe of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. Write Interrupted by a Precharge & DQM < Burst Length = 4 > 1 0 4 3 2 5 6 7 8 CLK Command NOP WRITE NOP NOP NOP Precharge NOP NOP NOP tWR DQ’s Din 0 Din 1 Din 2 Din 3 DQM 23 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the CASe where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Read with Auto Precharge < Burst Length = 4, CAS Latency = 2 > 1 0 5 4 3 2 6 7 8 9 CLK BANK A ACTIVE NOP NOP READ NOP Auto Precharge Command NOP NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 NOP tRAS CL = 2 DQ’s tRP Bank can be reactivated at the completion of precharge Begin Auto-Precharge Write with Auto Precharge < Burst Length = 4 > 0 1 2 5 4 3 6 7 8 10 9 11 CLK Command BANK A ACTIVE DQ’s NOP AutoWRITE Precharge Din 0 NOP NOP NOP Din 1 Din 2 Din 3 NOP NOP NOP NOP BANK A ACTIVE NOP Bank can be reactivated at the completion of precharge tRP tWR tDAL Internal precharge start 24 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or DESELECT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if powerdown occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or DESELECT and CKE HIGH at the desired clock edge (meeting tCKS). Power down CLK Command Precharge CKE Precharge power down Entry tCKS Precharge power NOP down Exit Active Active power down Entry Active power down Exit NOP tCKS 25 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Table 17: SIMPLIFIED TRUTH TABLE (V=Valid, X =Don't care, H=Logic High, L=Logic Low) CKEn-1 CKEn COMMAND Register Mode Register Set H Auto Refresh X Entry Self Refresh /CAS /WE L L L L X OP CODE L L L H X X Note 1, 2 3 L 3 L Exit Bank Active & Row Addr. Read & Column Address /RAS H H Refresh DQM BA0, 1 A10/AP A11 A9 ~ A0 /CS L H H H H 3 X H X X X X 3 H X L L H H X V H X L H L H X V Auto Precharge Disable L Auto Precharge Enable Auto Precharge Disable Write & Column Address Auto Precharge Enable Row Address H L H X L H L L X V H Entry H L L H H L X Exit L H H X X X X H X L H H L X H X L L H L X Deep Power down Column Address (A0~A8) Column Address (A0~A8) 4 4, 5 4 4, 5 X Burst Stop Bank Selection Precharge All Banks H Entry H Clock Suspend or Active Power Down Exit Entry L H X X X L V L X H 6 X X X L H H H H X X X L H H H H X X X L H H H H X X X L H H H H X L Precharge Power Down Mode X X X Exit L DQM H No Operation Command(NOP) H H X X H X X X L H H H X V X X X 7 NOTE : 1. OP Code : Operand Code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 CLK cycles after EMRS or MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only at all banks precharge state. 4. BA0 ~BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2CLK cycles. (Read DQM latency is 2). 26 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Timing Diagrams Basic Timing (Setup, Hold and Access Time @ BL=2, CL=2) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS tCMS tCMH /RAS /CAS BA0,BA1 BAa BAa BAb Ra Ca Cb A10/AP ADDR /WE tDS Hi-Z DQ Qa0 Qa1 tDH Db0 Db1 DQM COMMAND ACTIVE READ WRITE : Don’t care 27 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Power up & Initialization Sequence VDD VDDQ tCK A10 BA0, BA1 DQ High-Z T=100us tRP4 tRFC4 AR MRS tIS tIH CODE tIS tIH CODE tIS tIH BA0=L BA1=L tRFC4 tMRD4 tMRD4 EMRS CODE CODE BA0=H BA1=L ACT RA RA BA ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ A11 AR ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ A0-A9, PRE ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ DQM NOP ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ NOP2 ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ tIS tIH ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ LVTTL HIGH LEVEL CKE ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CLK ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~ tCH tCL NOP3 NOP Load Extended Mode Mode Register Register Power-up: VDD and CLK stable Notees: 1. PRE = PRECHARGE command, MRS = LOAD MODE REGISTER command, AR = AUTO REFRESH command ACT = ACTIVE command, RA = Row address, BA = Bank address 2. NOP or DESELECT commands are required for at least 100us. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. 28 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Mode Register Set 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE 2 Clock min. /CS /RAS /CAS /WE BA0, BA1 A10/AP ADDRESS KEY ADDR DQM High-Z tRP High-Z DQ Precharge Command All Bank Any Command Mode Register Set Command Note : Power & Clock must be stable for 100us before precharge all banks 29 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Powerdown Mode n+3 n+4 n+5 tCH Ra ~ ~~ ~ ~ ~ ~ ~ BAa DISABLE AUTO PRECHARGE SINGLE BANK Ca /WE BAa Ra Ra ~ ~ ~ ~ Ra BAa ALL BANK ~ ~ tAS tAH m+2 ~ ~ tAS tAH m+1 ~ ~ BAa ~ ~ tAS tAH ~ ~ /CAS ~ ~ /RAS m ~ ~ n+2 tCL ~ ~ /CS ADDR n+1 tCK ~ ~ CKE A10/AP n ~ ~~ ~ CLK BA0,BA1 1 ~ ~ 0 Da1 ~ ~ DQM COMMAND Da0 ~ ~ DQ ~ ~ ~ ~ tDS tDH NOP ACTIVE Input buffers gated off while in power-down mode PRE CHARGE WRITE NOP Exit power-down mode Exit power-down mode Enter power-down mode ACTIVE Input buffers gated off while in power-down mode tWR Precharge all activebanks All banks idle, enter power-down mode Note 1 Violating refresh requirements during power-down may result in a loss of data. 30 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Clock Suspend Mode 0 1 2 3 tCK CLK 4 5 6 7 8 9 10 tCL tCH tCKS tCKH CKE /CS /RAS /CAS tAS tAH BA0,BA1 BAa BAb tAS tAH A10/AP DISABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE tAS tAH ADDR Ca Cb /WE tAC DQ tOH Qa0 tHZ Qa1 tDH Da0 Da1 DQM COMMAND READ WRITE Note 1 For this example, BL=2, CL=3 and auto precharge is disabled. 31 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READ with Auto Precharge (@ BL=4, CL=2) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAa Ca Ra A10/AP ADDR /WE Auto Precharge start(Note 1) Da0 DQ Da1 Da2 tRP Da3 DQM COMMAND READ ACTIVE Note 1 The row active command of the precharged bank can be issued after tRP from this point. 32 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITE with Auto Precharge (@ BL=4) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAa Ca Ra A10/AP ADDR /WE Auto Precharge start(Note 1) DQ Da0 Da1 Da2 Da3 tWR tRP tDAL DQM COMMAND WRITE ACTIVE Note 1 The row active command of the precharged bank can be issued after tRP from this point. 33 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READ Interrupted by Precharge (@ BL=4, CL=2) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAa A10/AP ADDR Ca /WE Qa0 DQ Qa1 Qa2 DQM COMMAND READ PRE CHARGE When a burst Read command is issued to a SDRAM, a Prechcrge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and When a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP(RAS Precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 34 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READ Interrupted by a WRITE (@ BL=4, CL=2) 0 1 2 3 4 5 6 7 Db2 Db3 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR /WE Qa0 DQ Db0 Db1 DQM COMMAND READ WRITE 35 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READ Interrupted by READ (@ BL=4, CL=2) 0 1 2 3 4 5 6 7 Db2 Db3 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR /WE DQ Da0 Db0 Db1 DQM tCCD COMMAND READ READ 36 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITE followed by Precharge (@ BL=4) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAa A10/AP ADDR Ca /WE DQ Da0 Da1 Da2 Da3 tWR DQM COMMAND WRITE PRE CHARGE 37 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITE Interrupted by Precharge & DQM (@ BL=4) 0 1 2 3 4 5 6 7 BAb BAc Cb Cc Db0 Dc0 8 9 Dc1 Dc2 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAa A10/AP ADDR Ca /WE tWR DQ Da0 Da1 Da2 Da3 Dc3 DQM tCCD COMMAND WRITE PRE CHARGE WRITE 38 WRITE Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITE Interrupted by a READ (@ BL=4, CL=2) 0 1 2 3 4 5 6 7 8 9 Qb0 Qb1 Qb2 Qb3 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR /WE DQ Da0 Da1 Da2 DQM COMMAND WRITE READ 39 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM DQM Function (@BL=8) for write 0 1 2 3 4 5 6 7 8 Da5 Da6 Da7 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa A10/AP ADDR Ca /WE DQ Da0 Da1 Da2 Da3 Da4 DQM COMMAND WRITE 40 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM DQM Function (@BL=8, CL=2) for read 0 1 2 3 4 5 6 7 8 9 Da3 Da4 Da5 Da6 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa A10/AP ADDR Ca /WE Da0 DQ Da1 Da2 Da7 DQM COMMAND READ 41 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Single WRITE - Without Auto Precharge 0 1 2 3 CLK 4 5 6 7 8 9 10 tCL tCK tCH HIGH CKE /CS /RAS /CAS tAS tAH BA0,BA1 BAa BAa tAS tAH A10/AP ADDR BAa BAa ALL BANK Ra Ra tAS tAH DISABLE AUTO PRECHARGE Ra Ca SINGLE BANK Ra /WE tDS DQ tDH Da0 Da1 Da2 Da3 tCMS tCMH DQM COMMAND PRE CHARGE WRITE ACTIVE tRCD tWR ACTIVE tRP tRAS tRC 42 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Single WRITE - With Auto Precharge 0 1 2 3 CLK 4 5 6 7 8 9 10 tCL tCK tCH HIGH CKE /CS /RAS /CAS tAS tAH BA0,BA1 BAa BAa BAa tAS tAH ENABLE AUTO PRECHARGE A10/AP Ra Ra tAS tAH ADDR Ra Ca Ra /WE tDS DQ tDH Da0 Da1 Da2 Da3 tCMS tCMH DQM COMMAND WRITE ACTIVE tRCD ACTIVE tWR tRP tRAS tRC 43 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Multi Bank Interleaving READ (@ BL=2, CL=2) 0 1 2 3 4 5 6 7 8 9 Qa1 Qb0 Qb1 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAb BAa BAb Ra Rb Ca Cb A10/AP ADDR /WE tRRD tCCD Qa0 DQ DQM COMMAND ACTIVE ACTIVE READ READ 44 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM Multi Bank Interleaving WRITE (@ BL=2) 0 1 2 3 4 5 6 7 8 9 10 CLK tCH tCL tCK HIGH CKE /CS /RAS /CAS BA0,BA1 BAa BAb BAa BAb Ra Rb Ca Cb A10/AP ADDR /WE tCCD Da0 DQ Da1 Db0 Db1 DQM tRCD COMMAND ACTIVE ACTIVE WRITE WRITE 45 Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM READ - Full_Page Burst 2 3 tCK CLK 4 5 6 tCL tCH HIGH CKE /RAS /CAS tAS tAH BAa BAa tAS tAH A10/AP Ra tAS tAH ADDR Ra n+2 n+3 n+4 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ /CS BA0,BA1 n+1 ~ ~ 1 ~ ~~ ~ 0 Ca /WE DQ Qa m Qa m+1 tCMS tCMH DQM COMMAND tRCD Qa m-1 Qa m Qa n+1 BURST TERM READ ACTIVE ~ ~ ~ ~ tOH tAC CAS Latency Full page completed 46 Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop. Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM WRITE - Full_Page Burst 3 5 6 tCL tCK CLK 4 tCH HIGH CKE /RAS /CAS tAS tAH BAa BAa tAS tAH A10/AP Ra tAS tAH ADDR Ra Ca /WE tDS DQ Da m Da m+1 Da m+2 Da m+3 DQM n+4 Da m-1 Da m BURST TERM WRITE ACTIVE n+3 tDH tCMS tCMH COMMAND n+2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ /CS BA0,BA1 n+1 ~ ~ 2 ~ ~~ ~ 1 ~ ~ ~ ~ 0 tRCD Full page completed 47 Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop. Rev 0.1 Preliminary EM828164PA 128M: 8M x 16 Mobile SDRAM SDRAM FUNCTION GUIDE EM X XX XX X X X - XX X X X 1. EMLSI Memory 11. Temperature 2. Device Type 10. Power 3. Density 9. Speed 4. Organization 8. Package 5. Bank 7. Version 6. Interface ( VDD,VDDQ ) 1. Memory Component 2. Device Type 8 ------------------------ Low Power SDRAM 9 ------------------------ SDRAM D ------------------------ Mobile DDR 3. Density 32 ----------------------- 32M 64 ----------------------- 64M 28 ----------------------- 128M 56 ----------------------- 256M 12 ----------------------- 512M 1G ----------------------- 1G 4. Organization 04 ---------------------- x4 bit 08 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 5. Bank 2 ----------------------- 2 Bank 4 ----------------------- 4 Bank 6. Interface ( VDD,VDDQ ) V ------------------------- LVTTL ( 3.3V,3.3V ) H------------------------- LVTTL ( 3.3V,2.5V ) K ------------------------- LVTTL ( 3.0V,3.0V ) X ------------------------- LVTTL ( 3.0V,2.5V ) U ------------------------- P-LVTTL ( 3.0V,1.8V ) S ------------------------- LVCMOS ( 2.5V,2.5V ) R ------------------------- LVCMOS ( 2.5V,1.8V ) P ------------------------- LVCMOS ( 1.8V,1.8V ) 7. Version Blank ----------------- 1st generation A ------------------------2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation 8. Package Blank ----------------- KGD U ------------------------44 TSOP2 P ----------------------- 48 FpBGA Z ----------------------- 52 FpBGA Y ----------------------- 54 FpBGA V ----------------------- 90 FpBGA 9. Speed 60 ---------------------- 6.0ns (166MHz CL=3) 70 ---------------------- 7.0ns (143MHz CL=3) 75 ---------------------- 7.5ns (133MHz CL=3) 7C ---------------------- 7.5ns (133MHz CL=2) 80 ---------------------- 8.0ns (125MHz CL=3) 8C ---------------------- 8.0ns (125MHz CL=2) 90 ---------------------- 9.0ns (111MHz CL=3) 10 ---------------------- 10.0ns (100MHz CL=3) 1C ---------------------- 10.0ns (100MHz CL=2) 12 ---------------------- 12.0ns (83MHz CL=2) 1L ---------------------- 25.0ns (40MHz CL=1) 10. Power U ---------------------- Low Low Power L ---------------------- Low Power S ---------------------- Standard Power 11. Temperature C ---------------------- Commercial ( 0’C ~ 70’C ) E ---------------------- Extended (-25’C ~ 85’C ) I ---------------------- Industrial (-40’C ~ 85’C ) 48 Rev 0.1