EMLSI EMC646SP16JT-85L

Preliminary
EMC646SP16J
4Mx16 CellularRAM
Document Title
4Mx16 bit CellularRAM
Revision History
Revision No.
0.0
History
Initial Draft
Draft Date
Remark
July 05,2007
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
1
Preliminary
EMC646SP16J
4Mx16 CellularRAM
64Mb Async/Page/Burst CellularRAM
FEATURES
- Sigle device supports asynchrous, page and burst operation
- Vcc, VccQ voltages:
1.7V.1.95V VCC
1.7V.1.95V VCCQ
- Random access time: 70ns
- Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 104 MHz (tCLK = 9.62ns)
Burst initial latency: 38.5ns (4 clocks) @ 104 MHz ,
tACLK: 7ns @ 104 MHz
- Page mode READ access:
Sixteen-word page size
Interpage READ access : 70ns
Intrapage READ access : 20ns
- Low power consumption:
Asynchronous READ: <25mA
Initial access, burst READ:
(38.5ns [4 clocks] @ 104 MHz) <35mA
Continuous burst READ: <30mA
- Low-power features
On-chip temperature compensated self refresh (TCSR)
Partial array refresh (PAR)
Deep Power-down(DPD) mode
OPTIONS
- Configuration: 64Mb (4 megabit x 16)
- Vcc core / VccQ I/O voltage supply: 1.8V
- Timing: 70ns access
- Frequency: 83 MHz, 104 MHz
- Standby current at 85°C
Low Low Power : 140µA(max)
Low Power
: 160µA(max)
Standard
: 180µA(max)
- Operating temperature range:
Wireless -30°C to +85°C
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Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table of Contents
Features ......................................................................................................................................................................................
Options ...................................................................................................................................................................................
General Description ....................................................................................................................................................................
Functional Description ................................................................................................................................................................
Power-Up Initialization ............................................................................................................................................................
Bus Operating Modes .................................................................................................................................................................
Asynchronous Mode ...............................................................................................................................................................
Page Mode READ Operation ................................................................................................................................................
Burst Mode Operation ............................................................................................................................................................
Mixed-Mode Operation ...........................................................................................................................................................
WAIT Operation ......................................................................................................................................................................
LB# / UB# Operation...............................................................................................................................................................
Low-Power Operation......... ........................................................................................................................................................
Standby Mode Operation ........................................................................................................................................................
Temperature Compensated Refresh.......................................................................................................................................
Partial Array Refresh ..............................................................................................................................................................
Deep Power-Down Operation.................................................................................................................................................
Registers.....................................................................................................................................................................................
Access Using CRE .................................................................................................................................................................
Software Access .....................................................................................................................................................................
Bus Configuration Register......................................................................................................................................................
Burst Length (BCR[2:0]) Default = Continuous Burst .........................................................................................................
Burst Wrap (BCR[3]) Default = No Wrap ............................................................................................................................
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ...............................................................................
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid / Invalid.......................................
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH.......................................................................................................
Latency Counter (BCR[13:11]) Default = Three Clock Latency ..........................................................................................
Initial Access Latency (BCR[14]) Default = Variable...........................................................................................................
Operating Mode (BCR[15]) Default = Asynchronous Operation.........................................................................................
Refresh Configuration Register...............................................................................................................................................
Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh .........................................................................................
Deep Power-Down (RCR[4]) Default = DPD Disabled .......................................................................................................
Page Mode Operation (RCR[7]) Default = Disabled ..........................................................................................................
Device Identification Register..................................................................................................................................................
Electrical Characteristics.............................................................................................................................................................
Timing Requirements...................................................................................................................................................................
Timing Diagrams..........................................................................................................................................................................
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Preliminary
EMC646SP16J
4Mx16 CellularRAM
List of Figures
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Figure 50:
Functional Block Diagram - 4 meg x 16 .................................................................................................................
Power-Up Initialization Timing ...............................................................................................................................
READ Operation (ADV# LOW) ..............................................................................................................................
WRITE Operation (ADV# LOW) .............................................................................................................................
Page Mode READ Operation (ADV# LOW) ...........................................................................................................
Burst Mode READ (4-word burst)...........................................................................................................................
Burst Mode WRITE (4-word burst)..........................................................................................................................
Refresh Collision During Variable-Latency READ Operation .................................................................................
Wired or WAIT Configuration .................................................................................................................................
Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ..............................
Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ................................
Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ......................................................
Register READ, Synchronous Mode, Followed by READ ARRAY Operation ........................................................
Load Configuration Register ..................................................................................................................................
Read Configuration Register .................................................................................................................................
Bus Configuration Register Definition ....................................................................................................................
WAIT Configuration During Burst Operation ..........................................................................................................
Latency Counter (Variable Initial Latency, No Refresh Collision) ...........................................................................
Latency Counter (Fixed Latency) ...........................................................................................................................
Refresh Configuration Register Mapping ...............................................................................................................
AC Input/Output Reference Waveform ..................................................................................................................
AC Output Load Circuit ..........................................................................................................................................
Initialization Period .................................................................................................................................................
DPD Entry and Exit Timing Parameters .................................................................................................................
Asynchronous READ .............................................................................................................................................
Asynchronous READ Using ADV# .........................................................................................................................
PAGE MODE READ ..............................................................................................................................................
Single-Access Burst READ Operation - Variable Latency ......................................................................................
4-Word Burst READ Operation - Variable Latency .................................................................................................
Single-Access Burst READ Operation - Fixed Latency ..........................................................................................
4-Word Burst READ Operation - Fixed Latency .....................................................................................................
READ Burst Suspend ............................................................................................................................................
Burst READ at End-of-Row (Wrap off) ...................................................................................................................
CE# - Controlled Asychronous WRITE ..................................................................................................................
LB#/UB# - Controlled Asychronous WRITE ...........................................................................................................
WE# - Controlled Asychronous WRITE .................................................................................................................
Asynchronous WRITE Using ADV# .......................................................................................................................
Burst WRITE Operation - Variable Latency Mode ..................................................................................................
Burst WRITE Operation - Fixed Latency Mode ......................................................................................................
Burst WRITE at End-of-Row (Wrap off) .................................................................................................................
Burst WRITE Followed by Burst READ ..................................................................................................................
Burst READ Interrupted by Burst READ or WRITE ................................................................................................
Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode .......................................................
Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode ...........................................................
Asynchronous WRITE Followed by Burst READ ...................................................................................................
Asynchronous WRITE (ADV# LOW) Followed by Burst READ .............................................................................
Burst READ Followed by Asynchronous WRITE (WE# - Controlled) .....................................................................
Burst READ Followed by Asynchronous WRITE Using ADV# ...............................................................................
Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ...............................................................
Asynchronous WRITE Followed by Asynchronous READ .....................................................................................
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Preliminary
EMC646SP16J
4Mx16 CellularRAM
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
PIN Descriptions ..........................................................................................................................................................
Bus Operations ............................................................................................................................................................
Sequence and Burst Length ........................................................................................................................................
Drive Strength ..............................................................................................................................................................
Variable Latency Configuration Codes.........................................................................................................................
Fixed Latency Configuration Codes.............................................................................................................................
Address Patterns for PAR(RCR[4] =1).........................................................................................................................
Device Identification Register Mapping .......................................................................................................................
Absolute Maximum Ratings .........................................................................................................................................
Electrical Characteristics and Operating Conditions ....................................................................................................
Deep Power-Down Specifications ...............................................................................................................................
Capacitance ................................................................................................................................................................
Asynchronous READ Cycle Timing Requirements ......................................................................................................
Burst READ Cycle Timing Requirements ....................................................................................................................
Asynchronous WRITE Cycle Timing Requirements ....................................................................................................
Burst WRITE Cycle Timing Requirements ...................................................................................................................
Initialization and DPD Timing Parameters ...................................................................................................................
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Preliminary
EMC646SP16J
4Mx16 CellularRAM
General Description
CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications.
The 64Mb CellularRAM device has a DRAM core organized as 4 Meg x 16 bits. These devices include an industry-standard burst mode
Flash interface that dramatically increase read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offering.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden
refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device
interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration
register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. 64M CellularRAM products include three
mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match
the device temperature-the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep powerdown (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system
configurable refresh mechanisms are accessed through the RCR.
This 64M CellularRAM devices is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM
Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, additional wrap
options, and a device ID register (DIDR).
Figure 1 : Functional Block Diagram - 4 meg x 16
A[21:0]
Address Decode
Logic
4,096K x 16
DRAM
MEMORY
ARRAY
Refresh Configuration
Register (RCR)
Input
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
CLK
CE#
WE#
OE#
ADV#
CRE
LB#
UB#
WAIT
Control
Logic
Internal
External
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions(Table 1); Bus operations table(Table 2); and timing diagrams for detailed
information.
6
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 1 : PIN Descriptions
Symbol
Type
Descriptions
A[21:0]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
CLK
(Note1)
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
ADV#
(Note1)
Input
Address valid: Indiates that a valid address is present on the address inputs. Addresses can be latched on
the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during
asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations
access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby or deep power-down mode.
OE#
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB#
Input
Lower byte enable. DQ[7:0]
UB#
Input
Upper byte enable. DQ[15:8]
DQ[15:0]
Input/Output Data inputs/outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#.
WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at
the end of a row unless wrapping within the burst length. WAIT is asserted and should be ignored during
asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH.
WAIT
(Note1)
Output
RFU
-
Vcc
Supply
Device power supply: (1.70V.1.95V) Power supply for device core operation.
VccQ
Supply
I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
Vss
Supply
Vss must be connected to ground.
VssQ
Supply
VssQ must be connected to ground.
Reserved for future use.
Note:
1. When using asynchronous mode or page mode exclusively, CLK and ADV# inputs can be tied to Vss. WAIT will be asserted but should be ignored during asynchronous
and page mode operations.
7
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 2: Bus Operations
Asynchfonous Mode
BCR[15]=1
Power
OE#
WE#
CRE
UB#/
LB#
WAIT2
DQ[15:0]3
Note
Read
Active
L
L
L
H
L
L
Low-z
Data out
4
Write
Active
L
L
X
L
L
L
Low-z
Data in
4
Standby
Standby
L
X
H
X
X
L
X
High-z
High-z
5, 6
No operation
Idle
L
X
L
X
X
L
X
Low-z
X
4, 6
Configuration register
write
Active
L
L
H
L
H
X
Low-z
High-z
Configuration register
read
Active
L
L
L
H
H
L
Low-z
Config.
Reg.out
DPD
Deep
Power-down
L
H
X
X
X
X
High-z
High-z
7
Burst Mode
BCR[15]=0
Power
OE#
WE#
CRE
UB#/
LB#
WAIT2
DQ[15:0]3
Note
Async read
Active
L
L
L
H
L
L
Low-z
Data out
4, 8
Async write
Active
L
L
X
L
L
L
Low-z
Data in
4
Standby
Standby
L
X
H
X
X
L
X
High-z
High-z
5, 6
No operation
Idle
L
X
L
X
X
L
X
Low-z
X
4, 6
Initial burst read
Active
L
L
X
H
L
L
Low-z
X
4, 9
Initial burst write
Active
L
L
H
L
L
X
Low-z
X
4, 9
Burst continue
Active
H
L
X
X
X
L
Low-z
Data out or
Data in
4, 9
Burst suspend
Active
X
L
H
X
X
X
Low-z
High-z
4, 9
Configuration register
write
Active
L
L
H
L
H
X
Low-z
High-z
9, 10
Configuration register
read
Active
L
L
L
H
H
L
Low-z
Config.
Reg.out
9, 10
DPD
Deep
Power-down
X
H
X
X
X
X
High-z
High-z
7
CLK1 ADV# CE#
X
CLK1 ADV# CE#
X
L
Note:
1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during
burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is
in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VccQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW.
8. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI.
9. Burst mode operation is initialized through the bus configuration register (BCR[15]).
10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT).
8
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Functional Description
In general, 64M CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power,
portable applications. The 64Mb device contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits.The device
implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both
asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the
asynchronous read protocol.
Power-Up Initialization
64M CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will
configure the BCR and the RCR with their default settings. (See Figure 16 and 20) Vcc and VccQ must be applied simultaneously.
When they reach a stable level at or above 1.7V, the device will require 150µs to complete its self-initialization process. During the
initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation.
Figure 2: Power-Up Initialization Timing
Vcc=1.7V
Vcc
VccQ
tPU ≥ 150µs
Device Initialization
9
Device ready for
normal operation
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Bus Operating Modes
64M CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This
bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined
by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode.This mode uses the industry- standard SRAM control bus (CE#,
OE#, WE#, and LB#/UB#). READ operations (Figure 3) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 4) occur when
CE#, WE#, and LB#/UB# are driven LOW. During asychronous WRITE operations, the OE# level is a “Don’t care”, and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asychronous operations (page mode disabled) can either use the ADV# input to latch the address, or ADV# can be driven LOW during the entire READ/
WRITE operation.
During asychronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state
should be ignored. WE# LOW time must be limited to tCEM
Figure 3: READ Operation (ADV# LOW)
CE#
OE#
WE#
Address
DATA
Address Valid
High-Z
Data Valid
LB#/UB#
tRC = READ Cycle Time
Don’t Care
Note: ADV# must remain Low for PAGE MODE operation.
10
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 4: WRITE Operation (ADV# LOW)
CE#
OE#
< tCEM
WE#
Address
DATA
Address Valid
High-Z
Data Valid
LB#/UB#
tWC = WRITE Cycle Time
Don’t Care
Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an
initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address.
Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will
initiate a new tAA access time. Figure 5 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent
addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode
functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion
of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by
setting RCR[7] to HIGH. ADV# must be driven LOW during all page mode READ accesses. Due to refresh considerations, CE# must not
be LOW longer than tCEM.
Figure 5: Page Mode READ Operation (ADV# LOW)
＜ tCEM
CE#
OE#
WE#
Address
Add0
tAA
DATA
Add1 Add2 Add3
tAPA
tAPA
D1
D0
tAPA
D2
D3
LB#/UB#
Don’t Care
11
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock
sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the
next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# =
HIGH, Figure 6) or WRITE (WE# = LOW, Figure 7).
Figure 6: Burst Mode READ (4-word burst)
CLK
A[21:0]
Address
Valid
ADV#
Latency Code 2 (3 clocks)
CE#
OE#
WE#
WAIT
D0
DQ[15:0]
D1
D2
D3
LB#/UB#
Don’t Care
READ Burst Identified
(WE# = HIGH)
Undefined
Note: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
Diagram in the figure 6 is representative of variable latency with no refresh collision or fixed-latency access.
12
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 7: Burst Mode WRITE (4-word burst)
CLK
A[21:0]
Address
Valid
ADV#
Latency Code 2(3 clocks)
CE#
OE#
WE#
WAIT
DQ[15:0]
D0
D1
D2
D3
LB#/UB#
Don’t Care
WRITE Burst Identified
(WE# = LOW)
Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen,
or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the row ( 128 or 256 words,
determined by the manufacturer).
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between
the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE
operations always use fixed latency). Variable latency allows the CellarRAM to be configured for minimum latency at high clock
frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency
time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency
also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory.
WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length.
To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended.
Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is
suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT
output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time is
limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for
longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW / ADV# LOW cycle.
13
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 8: Refresh Collision During Variable-Latency READ Operation
VIH
CLK
VIL
VIH
A[21:0]
Valid
Address
VIL
VIH
ADV#
CE#
VIL
VIH
VIL
VIH
OE#
WE#
VIL
VIH
VIL
VIH
LB#/UB#
VIL
VOH
WAIT
High-Z
VOL
VOH
DQ[15:0]
D0
VOL
Additional WAIT states inserted to allow refresh completion
D1
D2
D3
Don’t Care
Undefined
Note:
Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
14
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. (Some vendors also support asychronous READ.) The asynchronous WRITE operations require that the clock
(CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during
the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled;
however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash
memory controllers. See Figure 45 for the “Asychronous WRITE Followed by Burst READ”timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal. (See Figure 9.) The shared
WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
Figure 9: Wired or WAIT Configuration
External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Processor
Other
Device
Other
Device
When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time
before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE
operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions
to an inactive state, the data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during WAIT cycles may cause data
corruption. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed. (See Figure 8) When the refresh operation has completed, the READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations. By using fixed initial
latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still
be used to determine when valid data is available at the start of the burst and at the end of row. If WAIT is not monitored, the controller
must stop burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written
is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When
both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data.
Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
15
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby
operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or
when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the
address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an
on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually
adjusts the refresh rate to match that temperature.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce
standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map. (See Table 11) READ and WRITE operations to address ranges receiving refresh will not be affected. Data
stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are
available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage
provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled, the CellularRAM device will require 150µs to perform an initialization procedure before normal operations can resume. During
this 150µs period, the current consumption will be higher than the specified standby levels, but considerably lower than the active
current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE#
goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10µs.
Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded
with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides
information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input
is HIGH. (See Figure 10 through 13) When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration
register values are written via addresses A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on
the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”. The BCR is accessed when A[19:18] are
10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than
A[19:18] are “Don’t Care”, and register bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or
WRITE operation, reading the memory array is highly recommended.
16
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 10: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
A[21:0]
(except A[19:18])
Address
OPCODE
tAVS
tAVH
Select control register
A[19:18]1
CRE
Address
tAVS
tAVH
ADV#
tVP
CE#
tCPH
Initiate control register access
tCW
OE#
tWP
WE#
Write address bus value
to control register
LB#/UB#
DQ[15:0]
Data Valid
Don’t Care
Note: 1. A[19:18] = 00b to load RCR, and 10b to load BCR.
17
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[21:0]
(except A[19:18])
OPCODE
tSP
Address
tHD
Latch control register address
A[19:18]2
Address
tSP
tHD
CRE
tSP
tHD
ADV#
tCBPH3
tCSP
CE#
OE#
tSP
tHD
WE#
LB#/UB#
tCEW
WAIT
High-Z
High-Z
Data
Valid
DQ[15:0]
Don’t Care
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
collisions require a corresponding number of additional CE# LOW cycles.
18
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 12: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation
A[21:0]
(except A[19:18])
Address
tAVS
tAVH
Select Register
A[19:18]1
Address
tAA
tAVH
CRE
tAVS
tAA
ADV#
tVP
CE#
tAADV
tCPH
Initiate register access
tCO
tHZ
OE#
tOHZ
tOE
tBA
WE#
tOLZ
tBHZ
tLZ
LB#/UB#
tLZ
DQ[15:0]
CR Valid
Data Valid
Don’t Care
Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
19
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 13: Register READ, Synchronous Mode, Followed by READ ARRAY Operation (WE# HIGH)
CLK
Latch control register value
A[21:0]
(except A[19:18])
Address
tSP
Latch control register address
A[19:18]2
Address
tSP
tHD
CRE
tHD
tSP
ADV#
tHD
tCBPH3
tABA
tCSP
CE#
tHZ
OE#
tOHZ
WE#
tSP
tHD
tBOE
LB#/UB#
tACLK
tCW
WAIT
DQ[15:0]
High-Z
tOLZ
tKOH
High-Z
Data
Valid
CR Valid
Don’t Care
Note:
1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks);
WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CE# LOW cycles.
20
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the
configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are
loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE
operations.(See Figure 14.) The read sequence is virtually identical except that an asynchronous READ is performed during the fourth
operation. (See Figure 15.) The address used during all READ and WRITE operations is the highest address of the CellularRAM device
being accessed (3FFFFFh); the contents of this address are not changed by using this sequence. The data value presented during the
third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the
sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access
the DIDR. During the fourth operation, DQ[15:0] transfer data in to or out of bits 15:0 of the registers. The use of the software sequence
does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to Vss. The
port line often used for CRE control purposes is no longer required.
Figure 14: Load Configuration Register
Address
READ
READ
WRITE
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
XXXXh
XXXXh
WRITE
ADDRESS
Max
CE#
OE#
WE#
LB#/UB#
DATA
CR Value In
RCR : 0000h
BCR : 0001h
Don’t Care
Figure 15: Read Configuration Register
Address
READ
READ
WRITE
READ
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
XXXXh
XXXXh
CE#
OE#
WE#
LB#/UB#
DATA
CR Value out
RCR : 0000h
BCR : 0001h
DIDR : 0002h
21
Don’t Care
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the
register access software sequence with DQ = 0001h on the third cycle.
Figure 16: Bus Configuration Register Definition
A[21:20]
A[19:18]
21-20
19-18
Reserved
Register
Select
A[17:16]
A15
A14
A13 A12 A11
13
17-16
15
14
Reserved
Operating
Mode
Initial
Latency
12
11
Latency
Counter
A10
A9
10
WAIT
Polarity
A8
A7
A6
9
8
7
6
Reserved
WAIT
Configuration(WC)
Must be set to “0”
All must be set to “0”
BCR[14]
Initial Access Latency
Reserved
A5 A4
5
4
Drive
Strength
Reserved
A3
3
Burst
Wrap(BW)*
BCR[3]
0
Burst wraps within the burst length
1
Fixed
1
Burst no wrap (default)
BCR[5]
BCR[4]
0
0
Drive Strength
BCR[13]
BCR[12]
BCR[11]
0
0
0
Code 0 - Reserved
0
1
1/2 (default)
0
0
1
Code 1 - Reserved
1
0
1/4
Full
1
1
Reserved
0
1
0
Code 2
0
1
1
Code 3 (default)
1
0
0
Code 4
1
0
1
Code 5
BCR[8]
1
1
0
Code 6
0
Asserted during delay
1
1
1
Code 7 - Reserved
1
Asserted one data before delay(default)
BCR[15]
1
WAIT Configuration
WAIT Polarity
0
Active LOW
1
Active HIGH (default)
Operating Mode
0
Synchronous burst access mode
1
Asynchronous access mode (default)
BCR[2]
BCR[1]
BCR[0]
0
0
1
4 words
Burst Length (Note 1)
0
1
0
8 words
0
1
1
16 words
Select RCR
1
0
0
32 words
0
Select BCR
1
1
1
Continuous burst (default)
1
Select DIDR
BCR[19]
BCR[18]
0
0
1
0
Register Select
Others
Note: 1. Burst wrap and length apply to both READ and WRITE operations.
22
Reserved
0
Burst
Length(BL)*
Burst Wrap (Note 1)
Variable (default)
BCR[10]
2
Must be set to “0”
Must be set to “0”
0
Latency Counter
A2 A1 A0
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst
length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is accessed sequentially up to the end
of row.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4, 8, 16, or 32 word READ or WRITE burst wraps within the burst length, or steps through
sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses up to the end of the row.
Table 3: Sequence and Burst Length
BURST Wrap
BCR[3]
0
Wrap
Yes
Starting
Address
4 Word
Burst
Length
Decimal
Linear
Linear
Linear
Linear
Linear
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2 ... 29-30-31
0-1-2-3-4-5-6-...
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3 ... 30-31-0
1-2-3-4-5-6-7-...
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4 ... 31-0-1
2-3-4-5-6-7-8-...
3
3-0-1-2
8 Word
Burst Length
16 Word
Burst Length
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5 ... 0-1-2
3-4-5-6-7-8-9-...
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6 ... 1-2-3
4-5-6-7-8-9-10-...
5
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7 ... 2-3-4
5-6-7-8-9-10-11-...
6
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8 ... 3-4-5
6-7-8-9-10-11-12-...
7
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-...
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9 ... 4-5-6
...
...
...
...
14
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-...-11-12-13
14-15-16-17-18-19-20-...
15
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17...-12-13-14
15-16-17-18-19-20-21-...
...
...
...
30
30-31-0-...-27-28-29
30-31-32-33-34-...
31-0-1-... -28-29-30
31-32-33-34-35-...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-...-29-30-31
0-1-2-3-4-5-6-...
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
1-2-3-...-30-31-32
1-2-3-4-5-6-7-...
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
2-3-4-...-31-32-33
2-3-4-5-6-7-8-...
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
3-4-5-...-32-33-34
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
4-5-6-...-33-34-35
4-5-6-7-8-9-10-...
4
No
Continuous
Burst
4
31
1
32 Word
Burst Length
5
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20
5-6-7-...-34-35-36
5-6-7-8-9-10-11-...
6
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21
6-7-8-...-35-36-37
6-7-8-9-10-11-12-...
7
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-...
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22
7-8-9-...-36-37-38
...
...
...
...
14
14-15-16-17-18-...-23-24-25-26-27-28-29
14-15-16-...43-44-45
14-15-16-17-18-19-20-...
15
15-16-17-18-19-...-24-25-26-27-28-29-30
15-16-17-...-44-45-46
15-16-17-18-19-20-21-...
...
...
...
30
30-31-32-...-59-60-61
30-31-32-33-34-35-36-...
31
31-32-33-...-60-61-62
31-32-33-34-35-36-37-...
23
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The
reduced-strength options are intended for stacked chip (Flash + CelllularRAM) environments when there is a dedicated memory bus.
The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength
should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at
half-drive strength during testing. See Table 4 for additional information.
Table 4: Drive Strength
BCR[5]
BCR[4]
Drive Strength
Impedance Typ (Ω )
Use Recommendation
0
0
Full
25~30
CL = 30pF to 50pF
0
1
1/2
(default)
50
CL = 15pF to 30pF
104 MHz at light load
1
0
1/4
100
CL = 15pF or lower
1
1
Reserved
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to
valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the
de-asserted or asserted state, respectively. When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid
or invalid. (See Figure 17.)
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT
signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 17: WAIT Configuration During Burst Operation
CLK
BCR[8] = 0
Data valid in current cycle
WAIT
BCR[8] = 1
Data valid in next cycle
WAIT
DQ[15:0]
D0
D1
D2
D3
End of row
Note: Non-default BCR setting: WAIT active LOW.
24
Don’t Care
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data
value transferred. For allowable latency codes, see Tables 5 and 6, respectively, and Figures 18 and 19, respectively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to
detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that
allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is
not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency
counter. (See Table 6 and Figure 19)
Table 5: Variable Latency Configuration Codes
Latency
Configuration
Code
BCR[13:11]
Latency 1
Max Input CLK Frequency (MHz)
Normal
Refresh Collision
104
83
66
010
2 (3 clocks)
2
4
66(15ns)
52(19.2ns)
40(25ns)
011
3 (4 clocks)-default
3
6
104(9.62ns)
83(12ns)
66(15ns)
Reserved
-
-
-
-
-
Others
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
Figure18: Latency Counter (Variable Initial Latency, No Refresh Collision)
VIH
CLK
VIL
VIH
A[21:0]
VIL
VIH
Valid
Address
ADV#
VIL
DQ[15:0]
VOH
Code 2
Valid
Output
VOL
DQ[15:0]
VOH
Code 3
(default)
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Don’t Care
25
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 6: Fixed Latency Configuration Codes
Latency
Configuration
Code
BCR[13:11]
Max Input CLK Frequency (MHz)
Latency Count (N)
104
83
66
010
2 (3 clocks)
2
33(30ns)
33(30ns)
20(50ns)
011
3 (4 clocks)-default
3
52(19.2ns)
52(19.2ns)
33(30ns)
100
4 (5 clocks)
4
66(15ns)
66(15ns)
40(25ns)
101
5 (6 clocks)
5
75(13.3ns)
75(13.3ns)
52(19.2ns)
110
6 (7 clocks)
6
104(9.62ns)
83(12ns)
66(15ns)
Reserved
--
-
-
-
Others
Figure 19: Latency Counter (Fixed Latency)
N-1
Cycles
CLK
Cycle N
VIH
VIL
VIH
A[21:0]
VIL
tAA
Valid
Address
tAADV
VIH
ADV#
VIL
VIH
tCO
CE#
VIL
tACLK
VOH
DQ[15:0]
(READ) V
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
tSP tHD
VOH
DQ[15:0]
(WRITE) V
OL
Valid
Input
Valid
Input
Valid
Input
Don’t Care
Burst Identified
(ADV# = LOW)
Valid
Input
Valid
Input
Undefined
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
26
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh
parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 20 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and
A[19:18] = 00b; or through the register access software sequence with DQ = 0000h on the third cycle.
Figure 20: Refresh Configuration Register Mapping
Address Bus
A[21:20]
A[19:18]
A[17:8]
A7
A6
6
21-20
19-18
17-8
7
Reserved
Register Select
Reserved
Page
All must be
set to “0”
All must be
set to “0”
A5
5
Reserved
A4
A3
A2
4
3
2
DPD
Reserved
A1
A0
1
0
PAR
Must be set to “0”
Setting is ignored
(Default 00b)
RCR[19]
RCR[18]
RCR[2]
RCR[1]
RCR[0]
0
0
Select RCR
0
0
0
Full array (default)
1
0
Select BCR
0
0
1
Bottom 1/2 array
0
1
Select DIDR
0
1
0
Bottom 1/4 array
0
1
1
Bottom 1/8 array
1
0
0
None of array
1
0
1
Top 1/2 array
RCR[7]
Register Select
Page Mode Enable/Disable
Refresh Coverage
0
Page Mode Disable (default)
1
1
0
Top 1/4 array
1
Page Mode Enable
1
1
1
Top 1/8 array
RCR[4]
0
1
27
Deep Power-Down
DPD Enable
DPD Disable (default)
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address
map.
Table 7: Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
0
0
Full Die
000000h-3FFFFFh
4 Meg x 16
64Mb
1
One-half die
000000h-1FFFFFh
2 Meg x 16
32Mb
0
0
1
0
One-quarter of die
000000h-0FFFFFh
1 Meg x 16
16Mb
1
1
One-eighth of die
000000h-07FFFFh
512 K x 16
8Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
200000h-3FFFFFh
2 Meg x 16
32Mb
1
1
0
One-quarter of die
300000h-3FFFFFh
1 Meg x 16
16Mb
1
1
1
One-eighth of die
380000h-3FFFFFh
512 K x 16
8Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage
provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled, the CellularRAM device will require 150µs to perform an initialization procedure before normal operations can resume. Deep
power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the software sequence to
access the RCR. Taking CE# LOW for at least 10µs disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable
DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD.
Page Mode Operation (RCR[7]) Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default
state, page mode is disabled.
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8
describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the
register access software sequence with DQ = 0002h on the third cycle.
Table 8: Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
Field name
Row Length
Device version
Device density
CellularRAM generation
Vendor ID
Length
Bit
Setting
256words
1b
Version
Bit
Setting
Density
Bit
Setting
Generation
Bit
Setting
Vendor
Bit
Setting
1st
0000b
64Mb
010b
CR 1.5
010b
EMLSI
01010b
2nd
0001b
Options
28
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Electrical Characteristics
Table 9: Absolute Maximum Ratings
Parameter
Rating
Voltage to any pin except Vcc, VccQ relative to Vss
-0.30V to VccQ + 0.3V
Voltage on Vcc supply relative to Vss
-0.2V to +2.45V
Voltage on VccQ supply relative to Vss
-0.2V to +2.45V
Storage temperature (plastic)
-55°C to +150°C
Operating temperature (case) Wireless
-30°C to +85°C
Soldering temperature and time 10s (solder ball only)
+260°C
Stresses greater than those listed may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 10: Electrical Characteristics and Operating Conditions
Wireless Temperature (-30°C < TC < +85°C)
Min
Max
Unit
Supply voltage
Description
Conditions
Vcc
Symbol
1.7
1.95
V
Note
I/O supply voltage
VccQ
1.7
1.95
V
Input high voltage
VIH
VccQ - 0.4
VccQ + 0.2
V
1
Input low voltage
VIL
-0.20
0.4
V
2
0.80 VccQ
Output high voltage
IOH = -0.2mA
VOH
V
3
Output low voltage
IOL = +0.2mA
VOL
0.20 VccQ
V
3
Input leakage current
VIN = 0 to VccQ
ILI
1
µA
Output leakage current
OE# = VIH or chip disabled
ILO
1
µA
Operating current
Conditions
Max
Unit
Note
Symbol
Typ
Asynchronous random
READ/WRITE
ICC1
70ns
25
mA
4
Asynchronous
PAGE READ
ICC1P
70ns
18
mA
4
Initial access
burst READ/WRITE
ICC2
VIN = VccQ or 0V chip enabled, IOUT = 0
ICC3R
Continuous burst READ
ICC3W
Continuous burst WRITE
Standby current
VIN = VccQ or 0V, CE# = VccQ
ISB
104MHz
35
mA
83MHz
30
mA
66MHz
25
mA
104MHz
30
mA
83MHz
25
mA
66MHz
20
mA
104MHz
35
mA
83MHz
30
mA
66MHz
25
mA
Standard
180
µA
160
µA
140
µA
Low Power
LowLowPower
50
Note:
1. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b (default setting of one-half drive strength).
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output
capacitance expected in the actual system.
5. ISB (max) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs must be driven to
either VccQ or Vss. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode.
6. ISB (typ) is the average ISB at 25°C and Vcc = VccQ = 1.8V. This parameter is verified during characterization, and is not 100% tested.
29
4
4
4
5, 6
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 11: Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Max
Unit
Deep Power-Down
VIN = VccQ or 0V;
Vcc, VccQ = 1.95V; +85°C
IZZ
3
10
µA
Note: Typical (TYP) IZZ value is tested at Vcc=1.8V, TA=25°C and not guaranteed.
Table 12: Capacitance
Description
Conditions
Input Capacitance
Tc = = +25°C; f = 1 MHz;
VIN = 0V
Input/Output
Capacitance(DQ)
Symbol
Min
Max
Unit
Note
CIN
2.0
6
pF
1
CIO
3.5
6
pF
1
Note: These parameters are verified in device characterization and are not 100% tested.
Figure 21: AC Input/Output Reference Waveform
VssQ
Input1
VccQ/22
Test Points
VccQ/23
VccQ
Note:
1. AC test inputs are driven at VccQ for a logic 1 and VssQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VccQ/2.
3. Output timing ends at VccQ/2.
Figure 22: AC Output Load Circuit
Test Points
50-Ohm
VccQ/2
DUT
30pF
Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
30
Output
Preliminary
EMC646SP16J
4Mx16 CellularRAM
TIMING REQUIREMENTS
Table 13: Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol
104/83 MHz
Min
66 MHz
Max
Min
Max
Unit
Note
tAA
70
85
ns
ADV# access time
tAADV
70
85
ns
Page access time
tAPA
25
ns
Address hold from ADV# HIGH
tAVH
2
Address setup to ADV# HIGH
tAVS
5
LB#/UB# access time
tBA
70
85
ns
LB#/UB# disable to DQ High-Z output
tBHZ
8
8
ns
1
LB#/UB# enable to Low-Z output
tBLZ
ns
2
4
µs
3
Address access time
Maximum CE# pulse width
tCEM
CE# LOW to WAIT valid
tCEW
Chip select access time
tCO
CE# LOW to ADV# HIGH
tCVS
Chip disable to DQ and WAIT High-Z output
tHZ
Chip enable to Low-Z output
tLZ
20/25
2
5
10
1
ns
10
4
7.5
1
70
7
7.5
ns
85
ns
7
8
10
4
ns
ns
8
10
ns
1
ns
2
Output enable to valid output
tOE
Output hold from address change
tOH
Output disable to DQ High-Z output
tOHZ
ns
1
Output enable to Low-Z output
tOLZ
3
3
ns
2
4
20
5
20
5
8
ns
ns
8
Page READ cycle time
tPC
20/25
25
ns
READ cycle time
tRC
70
85
ns
ADV# pulse width LOW
tVP
5
7
ns
Note:
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
3. Page mode enabled only.
4. Contact EMLSI for specific timing.
31
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 14: Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
104MHz
Symbol
Min
83MHz
Max
Min
66MHZ
Max
Min
Unit
tAA
70
70
85
ns
ADV# access time (fixed latency)
tAADV
70
70
85
ns
Burst to READ access time (variable latency)
tABA
35.9
45
55
ns
CLK to output delay
tACLK
7
9
11
ns
20
ns
Address access time (fixed latency)
Address hold from ADV# HIGH(fixed latency)
tAVH
Burst OE# LOW to output delay
tBOE
CE# HIGH between subsequent burst or mixed mode
operations
tCBPH
Maximum CE# pulse width
tCEM
CE# or ADV# LOW to WAIT valid
tCEW
1
CLK period
tCLK
9.62
2
2
20
5
2
20
6
4
7.5
1
ns
8
4
7.5
12.5
1
ns
1
4
µs
1
7.5
ns
15
ns
Chip select access time (fixed latency)
tCO
CE# setup time to active CLK edge
tCSP
3
4
5
ns
Hold time from active CLK edge
tHD
2
2
2
ns
Chip disable to DQ and WAIT High-Z output
tHZ
8
8
8
ns
CLK rise or fall time
tKHKL
1.6
1.8
2.0
ns
CLK to WAIT valid
tKHTL
11
ns
Output HOLD from CLK
tKOH
2
tKP
3
CLK HIGH or LOW time
70
70
7
85
9
2
2
4
Output disable to DQ High-Z output
tOHZ
Output enable to Low-Z output
tOLZ
3
3
Setup time to active CLK edge
tSP
3
3
8
2
ns
8
ns
2
3
ns
3
3
ns
Note:
1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
32
ns
ns
5
8
Note
Max
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 15: Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol
104/83 MHz
Min
Max
66MHz
Min
Max
Unit
Address and ADV# LOW setup time
tAS
0
0
ns
Address HOLD from ADV# going HIGH
tAVH
2
2
ns
Address setup to ADV# going HIGH
tAVS
5
5
ns
Address valid to end of WRITE
tAW
70
85
ns
LB#/UB# select to end of WRITE
tBW
70
85
ns
CE# LOW to WAIT valid
tCEW
1
CE# HIGH between subsequent async operations
tCPH
5
5
ns
CE# LOW to ADV# HIGH
tCVS
7
7
ns
Chip enable to end of WRITE
tCW
70
85
ns
Data HOLD from WRITE time
tDH
0
0
ns
Data WRITE setup time
tDW
20
Chip disable to WAIT High-Z output
tHZ
7.5
1
7.5
20
8
Note
ns
ns
8
ns
1
Chip enable to Low-Z output
tLZ
10
10
ns
2
End WRITE to Low-Z output
tOW
5
5
ns
2
ADV# pulse width
tVP
5
7
ns
ADV# setup to end of WRITE
tVS
70
85
ns
WRITE cycle time
tWC
70
85
ns
WRITE to DQ High-Z output
tWHZ
ns
1
WRITE pulse width
tWP
45
55
ns
3
WRITE pulse width HIGH
tWPH
10
10
ns
WRITE recovery time
tWR
0
0
ns
8
Note:
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
3. WE# Low time must be limited to tCEM (4µs).
33
8
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 16: Burst WRITE Cycle Timing Requirements
Parameter
104MHz
Symbol
Min
83MHz
Max
Min
66MHZ
Max
Min
Unit
Notes
1
Max
Address and ADV# LOW setup time
tAS
0
0
0
ns
Address HOLD from ADV# HIGH(fixed latency)
tAVH
2
2
2
ns
tCBPH
5
6
8
ns
2
4
µs
2
7.5
ns
CE# HIGH between subsequent burst or mixed mode
operations
Maximum CE# pulse width
tCEM
CE# LOW to WAIT valid
tCEW
1
4
7.5
4
1
7.5
1
Clock period
tCLK
9.62
12.5
15
ns
CE# setup to CLK active edge
tCSP
3
4
5
ns
Hold time from active CLK edge
tHD
2
2
2
ns
Chip disable to WAIT High-Z output
tHZ
8
8
8
ns
CLK rise or fall time
tKHKL
1.6
1.8
2.0
ns
Clock to WAIT valid
tKHTL
11
ns
7
9
CLK HIGH or LOW time
tKP
3
4
5
ns
Setup time to activate CLK edge
tSP
3
3
3
ns
Note:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
3. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
34
3
Preliminary
EMC646SP16J
4Mx16 CellularRAM
TIMING DIAGRAMS
Figure 23: Initialization Period
Vcc(MIN)
Vcc, VccQ = 1.7V
Device ready for
normal operation
tPU
Fitgure 24: DPD Entry and Exit Timing Parameters
tDPD
tDPDX
tPU
DPD Enabled
DPD EXIT
Device Initialization
CE#
Write
Device ready for
normal operation
RCR[4] = 0
Table 17: Initialization and DPD Timing Parameters
Symbol
Min
Max
tDPD
150
µs
tDPDX
10
µs
150
tPU
35
Unit
µs
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 25: Asynchronous READ
tRC
VIH
A[21:0]
Valid Address
VIL
tAA
VIH
ADV#
VIL
CE#
VIL
VIL
WE#
VIL
VIH
tOLZ
tBLZ
VIL
VOH
DQ[15:0]
VOL
tLZ
High-Z
VOL
Valid Output
tCEW
VOH
WAIT
tOHZ
tOE
VIH
OE#
tBHZ
tBA
VIH
LB#/UB#
tHZ
tCO
VIH
tHZ
High-Z
High-Z
Don’t Care
36
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 26: Asynchronous READ Using ADV#
A[21:0]
VIH
Valid Address
VIL
tAA
tAVH
tAVS
ADV#
CE#
VIH
tAADV
VIL
tVP
tCVS
VIH
tHZ
VIL
tCO
LB#/UB#
VIL
WE#
VIL
VIH
tOLZ
tBLZ
VIL
tLZ
VOH
DQ[15:0]
VOL
High-Z
Valid Output
tHZ
tCEW
VOH
WAIT
tOHZ
tOE
VIH
OE#
tBHZ
tBA
VIH
High-Z
High-Z
VOL
Don’t Care
37
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 27: PAGE MODE READ
tRC
VIH
A[21:4]
A[3:0]
Valid Address
VIL
VIH
ADV#
tAA
LB#/UB#
OE#
WE#
tCEM
tCO
tHZ
VIL
tBA
VIH
tBHZ
VIL
tOE
VIH
tOHZ
VIL
VIH
tOLZ
tAPA
tBLZ
VOL
Valid
Output
High-Z
tCEW
VOH
VOL
tOH
tLZ
VOH
WAIT
Valid
Address
tPC
VIL
VIL
DQ[15:0]
Valid
Address
VIH
VIH
CE#
Valid
Address
Valid Address
VIL
Valid
Output
Valid
Output
Valid
Output
tHZ
High-Z
High-Z
Don’t Care
38
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 28: Single-Access Burst READ Operation - Variable Latency
tCLK
tKP
tKP
VIH
CLK
VIL
tKHKL
tSP
tHD
VIH
A[21:0]
ADV#
Valid Address
VIL
tSP
VIH
tHD
tHD
VIL
CE#
tCEM
tHZ
tABA
tCSP
VIH
VIL
OE#
tOHZ
tBOE
VIH
VIL
tSP
tHD
tOLZ
VIH
WE#
VIL
LB#/UB#
VIL
VOL
tKHTL
tCEW
VOH
WAIT
tHD
tSP
VIH
High-Z
High-Z
tACLK
tKOH
VOH
DQ[15:0]
High-Z
Valid Output
High-Z
VOL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Note:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
39
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 29: 4-Word Burst READ Operation - Variable Latency
tKHKL
tCLK
tKP
tKP
VIH
CLK
VIL
tSP
tHD
VIH
A[21:0]
Valid Address
VIL
tSP
VIH
ADV#
VIL
tCEM
tCBPH
tHZ
VIL
tBOE
VIH
OE#
tHD
tABA
tCSP
VIH
CE#
tHD
VIL
tSP
tHD
tOHZ
tOLZ
VIH
WE#
VIL
LB#/UB#
VIL
tCEW
VOH
WAIT
VOL
VOL
tKHTL
High-Z
High-Z
tACLK
VOH
DQ[15:0]
tHD
tSP
VIH
tKOH
Valid
Output
High-Z
READ Burst Identified
(WE# = HIGH)
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
40
High-Z
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 30: Single-Access Burst READ Operation - Fixed Latency
tCLK
tKP
tKP
VIH
CLK
VIL
tKHKL
tSP
VIH
A[21:0]
ADV#
Valid Address
VIL
tAVH
tSP
VIH
tAA
tHD
tHD
tAADV
VIL
tCEM
CE#
OE#
tHZ
tCSP
VIH
VIL
tCO
tOHZ
tBOE
VIH
VIL
tSP
tHD
tOLZ
VIH
WE#
LB#/UB#
VIL
VIL
VOH
WAIT
DQ[15:0]
tHD
tSP
VIH
tKHTL
tCEW
High-Z
High-Z
VOL
VOH
tACLK
High-Z
tKOH
Valid Output
High-Z
VOL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Note:
1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
41
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 31. 4-Word Burst READ Operation - Fixed Latency
tKHKL
tCLK
CLK
VIL
A[21:0]
tSP
tHD
Valid Address
tSP
VIH
tAVH
tHD
tCSP
VIH
tCBPH
tHZ
tCO
tBOE
VIH
VIL
WE#
tHD
tCEM
VIL
OE#
tAA
tAADV
VIL
CE#
tKP
VIH
VIL
ADV#
tKP
VIH
tSP
tHD
tOHZ
tOLZ
VIH
VIL
LB#/UB#
tSP
VIH
VIL
WAIT
VOL
DQ[15:0]
tCEW
VOH
tHD
tKHTL
High-Z
High-Z
tACLK
VOH
VOL
tKOH
Valid
Output
High-Z
Valid
Output
READ Burst Identified
(WE# = HIGH)
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
42
Valid
Output
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Fogure 33. Burst READ at End-of-Row (Wrap Off)
CLK
VIH
VIL
A[21:0]
tCLK
VIH
VIL
VIH
ADV#
CE#
VIL
Note 2
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
VIH
LB#/UB#
tHZ
VIL
tKHTL
tHZ
VOH
WAIT
DQ[15:0]
High-Z
VOL
VOH
VOL
Valid
Output
Valid
Output
End of Row
Don’t Care
Note:
1. Non-default BCR settings for burst READ at end of row: fixed or variable latency; WAIT active LOW; WAIT asserted during delay.
2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with
BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).
43
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 32. READ Burst Suspend
tCLK
Note 2
VIH
CLK
A[21:0]
VIL
tSP
VIH
Valid
Address
VIL
ADV#
tHD
tSP
VIH
Valid
Address
tHD
CE#
tCSP
VIH
tHz
VIL
OE#
tOHZ
tOHZ
Note 3
VIH
VIL
WE#
tCBPH
tCEM
VIL
tSP
tHD
VIH
VIL
LB#/UB#
tSP
VIH
tOLZ
tBOE
tHD
VIL
WAIT
VOH
VOL
DQ[15:0]
High-Z
High-Z
tKOH
VOH
VOL
Valid
Output
High-Z
tBOE
Valid
Output
Valid
Output
Valid
Output
tOLZ
Valid
Output
Valid
Output
tACLK
Don’t Care
Note:
1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend.
3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
44
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 34. CE#-Controlled Asynchronous WRITE
tWC
A[21:0]
VIH
Valid Address
VIL
ADV#
CE#
tAW
tAS
tWR
VIH
VIL
tCPH
tCW
VIH
VIL
LB#/UB#
tBW
VIH
VIL
OE#
VIH
VIL
WE#
tWPH
tWP
VIH
VIL
DQ[15:0]
IN
VIH
DQ[15:0]
OUT
VOH
WAIT
tDW
High-Z
Valid Input
VIL
tLZ
tWHZ
VOL
VOL
tHZ
tCEW
VOH
tDH
High-Z
High-Z
Don’t Care
45
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 35. LB#/UB#-Controlled Asynchronous WRITE
tWC
A[21:0]
VIH
Valid Address
VIL
ADV#
tWR
tAW
VIH
tAS
VIL
CE#
tCW
VIH
VIL
LB#/UB#
tBW
VIH
VIL
OE#
VIH
VIL
WE#
tWPH
tWP
VIH
VIL
DQ[15:0]
IN
VIH
DQ[15:0]
OUT
VOH
WAIT
tDW
Valid Input
High-Z
VIL
tLZ
tWHZ
VOL
VOL
tHZ
tCEW
VOH
tDH
High-Z
High-Z
Don’t Care
46
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 36. WE#-Controlled Asynchronous WRITE
tWC
A[21:0]
VIH
Valid Address
VIL
ADV#
tAW
tWR
VIH
VIL
CE#
tCW
VIH
VIL
LB#/UB#
OE#
tBW
VIH
VIL
tAS
VIH
VIL
WE#
tWP
tWPH
VIH
VIL
DQ[15:0] VIH
IN VIL
DQ[15:0]
OUT
WAIT
tDW
High-Z
Valid Input
tWHZ
tLZ
VOH
tOW
VOL
VOL
tHZ
tCEW
VOH
tDH
High-Z
High-Z
Don’t Care
47
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 37. Asynchronous WRITE Using ADV#
A[21:0]
VIH
Valid Address
VIL
tAVS
tAVH
tVS
ADV#
tVP
VIH
tAS
tAS
VIL
tAW
tCVS
VIH
tCW
CE#
VIL
LB#/UB#
tBW
VIH
VIL
VIH
OE#
WE#
VIL
VIL
DQ[15:0]
IN
VIH
DQ[15:0]
VOH
OUT
VOL
WAIT
tWPH
tWP
VIH
tDW
High-Z
Valid Input
VIL
VOL
tWHZ
tLZ
tOW
tHZ
tCEW
VOH
tDH
High-Z
High-Z
Don’t Care
48
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 38. Burst WRITE Operation - Variable Latency Mode
tKHKL
tCLK
CLK
VIL
A[21:0]
tSP
tHD
Valid Address
3
tAS
tSP
VIH
VIL
CE#
tKP
VIH
VIL
ADV#
tKP
VIH
tAS3
VIH
tHD
tHD
tCSP
tCBPH
tCEM
VIL
OE#
VIH
VIL
WE#
tSP
tHD
VIH
VIL
LB#/UB#
tSP
VIL
WAIT
DQ[15:0]
tHD
VIH
VOL
tKHTL
tCEW
VOH
High-Z
tHZ
High-Z
Note 2
tSP
tHD
ViH
D1
D2
D3
D0
ViL
WRITE Burst Identified
(WE# = Low)
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW; WAIT
asserted during delay; burst length four; burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
49
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 40. Burst WRITE at End-of-Row (Wrap Off)
CLK
VIH
VIL
A[21:0]
tCLK
VIH
VIL
ADV#
VIH
VIL
LB#/UB#
VIH
VIL
WE#
VIH
VIL
OE#
VIH
VIL
Version A
CE#
Note 2
VIH
VIL
DQ[15:0]
VIH
VIL
tSP
tHD
Valid
Intput
Valid
Intput
End of Row
(A[6:0]=7Fh)
tHZ
WAIT
VOH
tKHTL
tHZ
High-Z
VOL
Note 3
Version B
CE#
VIL
VIH
DQ[15:0]
Note 2
VIH
VIL
tSP
tHD
Valid
Intput
Valid
Intput
Valid
Intput
End of Row
(A[6:0]=7Fh)
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT active LOW; WAIT asserted during delay.
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with
BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).
3. Devices from different CellularRAM vendors can assert WAIT so that the end-of-row data is input one cycle before WAIT asserts (DQ version A).
or the same cycle that asserts WAIT (DQ version B). This difference in behavior will not be noticed by controllers that monitor WAIT, or that use
WAIT to abort on an end-of-row condition.
50
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 39. Burst WRITE Operation - Fixed Latency Mode
tKHKL
tCLK
CLK
VIL
A[21:0]
tSP
Valid Address
tAS3
tSP
VIH
VIL
CE#
tKP
VIH
VIL
ADV#
tKP
VIH
tAS3
VIH
tHD
tAVH
tHD
tCSP
tCBPH
tCEM
VIL
OE#
VIH
VIL
WE#
tSP
tHD
VIH
VIL
LB#/UB#
tSP
VIL
WAIT
tKHTL
tCEW
tHZ
VOH
VOL
DQ[15:0]
tHD
VIH
High-Z
High-Z
Note 2
tSP
tHD
VIH
D1
D2
D3
D0
VIL
WRITE Burst Identified
(WE# = Low)
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
51
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 41. Burst WRITE Followed by Burst READ
tCLK
CLK
VIH
VIL
A[21:0]
VIH
VIL
ADV#
VIH
VIL
CE#
tSP tHD
tSP tHD
Valid
Address
Valid
Address
tSP tHD
tSP tHD
tHD tCBPH
tCSP
VIH
VIL
OE#
tOHZ
tSP tHD
tSP tHD
VIH
VIL
LB#/UB#
tCSP
VIH
VIL
WE#
Note 2
tHD
tSP
VIH
VIL
WAIT
tBOE
VOH
DQ[15:0]
IN/OUT
High-Z
High-Z
VOL
tSP
tHD
tACLK
VIH
VOH
High-Z
VIL
D0
D1
D2
D3
VOL
High-Z
tKOH
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain
LOW longer than tCEM. See burst interrupt diagrams for cases where CE# stays LOW between bursts.
52
Valid
Output
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 42. Burst READ Interrupted by Burst READ or WRITE
READ Burst interrupted with new READ or WRITE. See Note 2.
tCLK
CLK
VIH
VIL
A[21:0]
VIH
VIL
ADV#
VIH
VIL
CE#
tSP tHD
Valid
Address
Valid
Address
tSP tHD
tSP tHD
tCSP
tSP tHD
tSP tHD
VIH
VIL
WAIT
tKHTL
VOH
High-Z
VOL
OE#
tHD
tCEM (Note 3)
VIH
VIL
WE#
tSP tHD
VIH
tBOE
tCEW
tOHZ
tOHZ
tBOE
2nd Cycle READ VIL
LB#/UB#
VIH
2nd Cycle READ VIL
DQ[15:0] OUT
VOH
2nd Cycle READ VOL
tACLK
tKOH
Valid
Output
High-Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D1
D2
D3
tACLK
OE#
2nd Cycle Write
VIH
VIL
LB#/UB# VIH
2nd Cycle Write V
IL
DQ[15:0] IN
tSP tHD
VIH
High-Z
2nd Cycle Write VIL
D0
Don’t Care
Note:
1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three clocks); WAIT active
LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
53
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 43. Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode
WRITE Burst interrupted with new WRITE or READ. See Note 2.
tCLK
CLK
VIH
VIL
A[21:0]
tSP tHD
VIH
Valid
Address
VIL
ADV#
tSP tHD
tCSP
tSP tHD
tSP tHD
VIH
VIL
WAIT
tHD
tCEM (Note 3)
VIH
VIL
WE#
Valid
Address
tSP tHD
VIH
VIL
CE#
tSP tHD
VOH
tKHTL
High-Z
High-Z
VOL
tCEW
OE# VIH
2nd Cycle WRITE
LB#/UB#
2nd Cycle WRITE
DQ[15:0]
VIL
VIL
IN VIH
2nd Cycle WRITE
tSP tHD
VIH
High-Z
VIL
OE#
2nd Cycle READ
LB#/UB#
2nd Cycle READ
DQ[15:0] OUT
2nd Cycle READ
tSP tHD
tSP tHD
D0
D0
D2
D3
tOHZ
tBOE
VIH
VIL
D1
tSP
tHD
VIH
VIL
tACLK
VOH
VOH
VOL
VOL
High-Z
tKOH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
54
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 44. Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode
WRITE Burst interrupted with new WRITE or READ. See Note 2.
tCLK
CLK
VIH
VIL
A[21:0]
VIH
VIL
ADV#
Valid
Address
Valid
Address
tAVH
tSP tHD
tCSP
tSP tHD
tSP tHD
VIH
VIL
WAIT
OE#
2nd Cycle WRITE
LB#/UB#
2nd Cycle WRITE
DQ[15:0] IN
2nd Cycle WRITE
tHD
tCEM (Note 3)
VIH
VIL
WE#
tSP tHD
tSP tHD
VIH
VIL
CE#
tSP tHD
tKHTL
VOH
High-Z
High-Z
VOL
tCEW
VIH
VIL
tSP tHD
VIH
VIL
tSP tHD
tSP tHD
D0
D0
VIH
High-Z
VIL
OE#
2nd Cycle READ
LB#/UB#
2nd Cycle READ
DQ[15:0] OUT
2nd Cycle READ
D2
D3
tOHZ
tBOE
VIH
VIL
D1
tSP
tHD
VIH
VIL
tACLK
VOH
VOH
VOL
VOL
High-Z
tKOH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
55
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 45. Asynchronous WRITE Followed by Burst READ
tCLK
CLK
VIH
VIL
A[21:0]
OE#
tAVH
tAVS
VIH
tVP
VIL
tCVS
tCW
VIH
CE#
tSP
Valid Address
Valid Address
VIL
ADV#
tWC
tWC
tHD
VIH
tAW
tVS
Valid Address
tWR
tSP
tCBPH
tHD
tCSP
Note 2
VIL
tAS
tOHZ
VIH
VIL
tAS
tWC
tWP
tSP tHD
VIH
WE#
tWPH
VIL
LB#/UB#
VIL
tBOE
tCEW
VOH
WAIT
tHD
tSP
tBW
VIH
High-Z
VOL
DQ[15:0] VIH
IN/OUT VIL
tDH
tDW
tACLK
VOH
High-Z
Data
Data
High-Z
VOL
tKOH
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT
active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to
fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
56
Valid
Output
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 46. Asynchronous WRITE (ADV# LOW) Followed By Burst READ
tCLK
CLK
VIH
VIL
A[21:0]
tWC
Valid Address
Valid Address
VIL
ADV#
tAW
OE#
WE#
VIL
tSP
tCBPH
tCW
VIL
DQ[15:0]
IN/OUT
tCSP
Note 2
VIL
tOHZ
tSP tHD
tWC
tWP
VIH
tWPH
VIL
tBW
VIL
tBOE
tCEW
High-Z
VOL
tDH
tDW
tACLK
VIH
VIL
tHD
tSP
VOH
WAIT
tHD
VIH
VIH
LB#/UB#
tHD
Valid Address
tWR
VIH
VIH
CE#
tSP
tWC
VIH
High-Z
Data
VOH
Data
VOL
High-Z
tKOH
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Note:
1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: Fixed or variable latency; latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to
fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
57
Valid
Output
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 47. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
tCLK
CLK
VIH
VIL
A[21:0]
tSP
tHD
tWC
VIH
Valid Address
Valid Address
VIL
ADV#
tSP
VIH
VIL
CE#
tHZ
VIL
OE#
VIH
tSP
tHD
tCW
Note 2
tOHZ
tBOE
VIL
WE#
tCBPH
tHD
tCSP
VIH
tAS
tOLZ
tCEW
VOH
VOL
tKHTL
tHZ
tCEW
High-Z
High-Z
tACLK
tKOH
VOH
DQ[15:0]
tWPH
tBW
tSP
VIH
VIL
WAIT
tWP
VIH
VIL
LB#/UB#
tWR
tAW
tHD
tDW
VIH
High-Z
Valid Input
Valid Output
VOL
tDH
VIL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Note:
1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from
fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM.
A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
58
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 48. Burst READ Followed by Asynchronous WRITE Using ADV#
tCLK
CLK
VIH
VIL
A[21:0]
tSP
tHD
VIH
Valid Address
Valid Address
VIL
ADV#
tAVS
tSP
VIH
tHD
OE#
tAW
LB#/UB#
VIL
tSP
Note 2
tAS
tOLZ
tWP
tWPH
VIH
VIL
tCEW
VOH
tBW
tHD
tSP
VIH
VOL
DQ[15:0]
tHD
tCW
tOHZ
tBOE
VIH
tAS
tCBPH
tHZ
VIL
WAIT
tHD
tCSP
VIH
VIL
WE#
tVS
tVP
VIL
CE#
tAVH
tHZ
tCEW
tKHTL
High-Z
High-Z
tKOH
tACLK
VOH
tDW
tDH
VIH
High-Z
Valid Output
VOL
Valid Input
VIL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Note:
1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: Fixed or variable latency; latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from
fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM. A
refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
59
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 49. Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW
A[21:0]
VIH
Valid Address
Valid Address
VIL
ADV#
tAW
Note 1
tOE
tAS
tWP
tWC
tWPH
tBW
VIH
WAIT
VIL
tBHZ
tBLZ
tHZ
tHZ
VOH
VOL
DQ[15:0]
IN/OUT
tOHZ
VIH
VIL
LB#/UB#
tHZ
tLZ
VIH
VIL
WE#
tAA
tCPH
tCW
VIH
VIL
OE#
tWR
VIH
VIL
CE#
Valid Address
tDH
tOLZ
tDW
VIH
VOH
High-Z
Data
Data
High-Z
VIL
Valid Output
VOL
Don’t Care
Note:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh
interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.
60
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 50. Asynchronous WRITE Followed by Asynchronous READ
VIH
A[21:0]
Valid Address
Valid Address
VIL
tAVS
tAW
tAVH
Valid Address
tWR
tAA
VIH
ADV#
CE#
VIL
tVP
VIH
tVS
VIL
OE#
tCPH
tHZ
tLZ
tCW
Note 1
tAS
tOE
VIH
VIL
tAS tWP
tOHZ
tOLZ
tWC
VIH
WE#
LB#/UB#
tWPH
VIL
VIH
tCVS
tBHZ
tBLZ
tBW
VIL
VOH
WAIT
DQ[15:0]
IN/OUT
VOL
tDH
tDW
VOH
VIH
High-Z
Data
Data
VOL
VIL
Valid Output
High-Z
Don’t Care
Note:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh
interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.
61
Undefined
Preliminary
EMC646SP16J
4Mx16 CellularRAM
62
Preliminary
EMC646SP16J
4Mx16 CellularRAM
63
Preliminary
EMC646SP16J
4Mx16 CellularRAM
64
Preliminary
EMC646SP16J
4Mx16 CellularRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X X - XX XX
1. EMLSI Memory
12. Power
2. Device Type
11. Speed
3. Density
10. PKG
9. Option
4. Function
5. Technology
8. Version
6. Operating Voltage
7. Organization
8. Version
Blank ----------------- Mother die
A ----------------------- 2’nd generation
B ----------------------- 3’rd generation
C ----------------------- 4’th generation
D ----------------------- 5’th generation
1. Memory Component
2. Device Type
6 ---------------------- Low Power SRAM
7 ---------------------- STRAM
C ---------------------- CellularRAM
9. Option
Blank ---- No optional mode
H ----------- Demultiplexed with DPD
J ------------ Demultiplexed with DPD & RBC
K ------------ Multiplexed with RBC
L ------------ Multiplexed with DPD & RBC
3. Density
4 ----------------------- 4M
8 ----------------------- 8M
16 --------------------- 16M
32 --------------------- 32M
64 --------------------- 64M
28 --------------------- 128M
4. Function
2 ----Multiplexed async.
3-----Demultiplexed async. with page mode
4-----Demultiplexed async. with direct DPD
5-----Multiplexed sync.
6-----Optional mux/demuxed sync.
5. Technology
S ----------------------- Single Transistor & Trench Cell
10. Package
Blank ---------------------- Wafer
S
---------------------- 32 sTSOP1
T
---------------------- 32 TSOP1
U
---------------------- 44 TSOP2
P
---------------------- 48 FPBGA
Z
---------------------- 52 FPBGA
Y
---------------------- 54 FPBGA
V
---------------------- 90 FPBGA
11. Speed (@async.)
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
6. Operating Voltage
V ----------------------- 3.3V
U ----------------------- 3.0V
S ----------------------- 2.5V
R ----------------------- 2.0V
P ----------------------- 1.8V
L ----------------------- 1.5V
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
12. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power
(Pb-Free&Green)
L ---------------------- Low Power
65