TI SN74HC4066

SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
D
D
D
D
D
D
D
D
D
D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Wide Operating Voltage Range of 2 V to 6 V
Typical Switch Enable Time of 18 ns
Low Power Consumption, 20-µA Max ICC
Low Input Current of 1 µA Max
High Degree of Linearity
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Low On-State Impedance . . .
50-Ω TYP at VCC = 6 V
Individual Switch Controls
1A
1B
2B
2A
2C
3C
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
1C
4C
4A
4B
3B
3A
description/ordering information
The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital
signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction.
Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
PDIP – N
TOP-SIDE
MARKING
Tube of 25
SN74HC4066N
Tube of 50
SN74HC4066D
Reel of 2500
SN74HC4066DR
Reel of 250
SN74HC4066DT
SOP – NS
Reel of 2000
SN74HC4066NSR
HC4066
SSOP – DB
Reel of 2000
SN74HC4066DBR
HC4066
Tube of 90
SN74HC4066PW
Reel of 2000
SN74HC4066PWR
Reel of 250
SN74HC4066PWT
SOIC – D
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – PW
SN74HC4066N
HC4066
HC4066
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each switch)
INPUT
CONTROL
(C)
SWITCH
L
OFF
H
ON
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
logic diagram, each switch (positive logic)
A
VCC
VCC
B
C
One of Four Switches
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Control-input diode current, II (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I/O port diode current, II (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
recommended operating conditions (see Note 3)
VCC
VI/O
VIH
MIN
2†
Supply voltage
I/O port voltage
∆t/∆v
MAX
5
6
V
VCC
VCC
V
VCC
VCC
V
4.2
0
0.3
0
0.9
0
1.2
0
VCC = 2 V
VCC = 4.5 V
High-level input voltage, control inputs
1.5
3.15
VCC = 6 V
VCC = 2 V
VIL
NOM
Low-level input voltage, control inputs
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
Input transition rise/fall time
UNIT
V
1000
500
VCC = 4.5 V
VCC = 6 V
ns
400
TA
Operating free-air temperature
–40
85
°C
† With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
TA = 25_C
MIN
TYP
MAX
2V
150
IT = –1
1 mA,
A VI = 0 to
t VCC,
VC = VIH (see Figure 1)
4.5 V
50
PARAMETER
ron
On-state switch resistance
GND VC = VIH,
VI = VCC or GND,
IT = –1 mA
MAX
UNIT
85
106
Ω
170
215
Ω
±100
±1000
nA
6V
±0.1
±5
µA
±0.1
±5
µA
2
20
µA
10
10
6V
30
2V
320
4.5 V
70
ron(p)
( )
Peak on-state resistance
II
Control input current
Isoff
Off-state switch leakage current
Ison
On-state switch leakage current
VI = VCC or 0, VC = VIH
(see Figure 3)
6V
ICC
Supply current
VI = 0 or VCC,
6V
VC = 0 or VCC
VI = VCC or 0, VO = VCC or 0,
VC = VIL (see Figure 2)
IO = 0
A or B
Ci
Input capacitance
Cf
Feed-through
capacitance
A to B
Co
Output capacitance
A or B
6V
50
6V
±0.1
5V
C
VI = 0
5V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
9
3
pF
0.5
pF
9
pF
3
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range
PARAMETER
tPLH,
tPHL
Propagation
P
ti
delay time
tPZH,
tPZL
Switch
S
it h
turn-on time
tPLZ,
tPHZ
fI
Switch
S
it h
turn-off time
Control
input
frequency
Control
feed-through
noise
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
C
C
C
C
A or B
TEST
CONDITIONS
CL = 50 pF
F
(see Figure 4)
RL = 1 kΩ,
CL = 50 pF
(see Figure 5)
A or B
RL = 1 kΩ,
CL = 50 pF
(see Figure 5)
A or B
CL = 15 pF,
RL = 1 kΩ
kΩ,
VC = VCC or GND,
VO = VCC/2
(see Figure 6)
A or B
CL = 50 pF,
Rin = RL = 600 Ω,
VC = VCC or GND
GND,
fin = 1 MHz
(see Figure 7)
VCC
TA = 25_C
TYP
MAX
MIN
MIN
MAX
2V
10
60
75
4.5 V
4
12
15
6V
3
10
13
2V
70
180
225
4.5 V
21
36
45
6V
18
31
38
2V
50
200
250
4.5 V
25
40
50
6V
22
34
43
2V
15
4.5 V
30
6V
30
4.5 V
15
UNIT
ns
ns
ns
MHz
mV
(rms)
6V
20
operating characteristics, VCC = 4.5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
UNIT
Power dissipation capacitance per gate
CL = 50 pF,
f = 1 MHz
45
pF
Minimum through bandwidth, A to B or B to A† [20 log (VO/VI)] = –3 dB
CL = 50 pF,
VC = VCC
RL = 600 Ω,
(see Figure 8)
30
MHz
Crosstalk between any switches‡
CL = 10 pF,
fin = 1 MHz
RL = 50 Ω,
(see Figure 9)
45
dB
Feed through, switch off, A to B or B to A‡
CL = 50 pF,
fin = 1 MHz
RL = 600 Ω,
(see Figure 10)
42
dB
Amplitude distortion rate, A to B or B to A
CL = 50 pF,
fin = 1 kHz
RL = 10 kΩ,
(see Figure 11)
0.05%
† Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
‡ Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
4
TYP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VC = VIH
VCC
VI = VCC
VO
(ON)
GND
+
r on
1.0 mA
V
+ 10
I–O
–3
W
–
V
VI–O
Figure 1. On-State Resistance Test Circuit
VCC
VC = VIL
VCC
A
A
(OFF)
B
GND
VS = VA – VB
CONDITION 1: VA = 0, VB = VCC
CONDITION 2: VA = VCC, VB = 0
Figure 2. Off-State Switch Leakage-Current Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VC = VIH
VCC
A
A
B
(ON)
VCC
Open
GND
VA = VCC TO GND
Figure 3. On-State Leakage-Current Test Circuit
VCC
VC = VIH
VCC
VI
VO
(ON)
50 Ω
50 pF
GND
TEST CIRCUIT
tr
tf
VI
A or B
90%
50%
10%
VCC
90%
50%
10%
0V
tPLH
VO
B or A
tPHL
VOH
50%
50%
VOL
VOLTAGE WAVEFORMS
Figure 4. Propagation Delay Time, Signal Input to Signal Output
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VC
RL
VO 1 kΩ
VCC
VI
S2
S1
TEST
S1
S2
tPZL
tPZH
tPLZ
tPHZ
GND
VCC
GND
VCC
VCC
GND
VCC
GND
CL
50 pF
GND
TEST CIRCUIT
VCC
VCC
VC
50%
50%
0V
0V
tPZH
tPZL
VOH
VOH
VO
50%
50%
VOL
VOL
(tPZL, tPZH)
VCC
VCC
VC
50%
50%
0V
0V
tPHZ
tPLZ
VOH
VOH
VO
VOL
10%
90%
VOL
(tPLZ, tPHZ)
VOLTAGE WAVEFORMS
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
50 Ω
VC
VC
0V
VCC
VO
VI = VCC
GND
CL
15 pF
RL
1 kΩ
VCC/2
Figure 6. Control-Input Frequency
VCC
50 Ω
tr
VC
VCC
VCC
VI
GND
Rin
600 Ω
RL
600 Ω
90% 90%
VC
VO
10%
0V
CL
50 pF
tf
10%
(f = 1 MHz)
tr = tf = 6 ns
VCC/2
VCC/2
Figure 7. Control Feed-Through Noise
VCC
VC = VCC
0.1 µF
fin
50 Ω
VI
VCC
(ON)
GND
VI
VO
RL
600 Ω
CL
50 pF
VCC/2
Figure 8. Minimum Through Bandwidth
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
(VI = 0 dBm at f = 1 MHz)
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325G – MARCH 1996 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VC = VCC
VCC
(ON)
VI
fin
50 Ω
0.1 µF
Rin
600 Ω
VO1
GND
RL
600 Ω
CL
50 pF
VCC/2
VI
VCC
VC = GND
(VI = 0 dBm at f = 1 MHz)
VCC
(OFF)
VO2
GND
Rin
600 Ω
RL
600 Ω
CL
50 pF
VCC/2
Figure 9. Crosstalk Between Any Two Switches
VCC
VC = GND
0.1 µF
50 Ω
VCC
(OFF)
VI
fin
Rin
600 Ω
VI
VO
RL
600 Ω
GND
VCC/2
CL
50 pF
(VI = 0 dBm at f = 1 MHz)
VCC/2
Figure 10. Feed Through, Switch Off
VCC
VC = VCC
fin
VI
10 µF
VCC
(ON)
GND
VO
RL
10 kΩ
VI
CL
50 pF
(VI = 0 dBm at f = 1 kHz)
VCC/2
Figure 11. Amplitude-Distortion Rate
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HC4066D
ACTIVE
SOIC
D
14
SN74HC4066DBLE
OBSOLETE
SSOP
DB
14
SN74HC4066DBR
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DBRE4
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DBRG4
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066DTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC4066NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC4066NSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066NSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
SN74HC4066PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC4066PWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
50
Green (RoHS &
no Sb/Br)
TBD
Addendum-Page 1
Lead/Ball Finish
CU NIPDAU
Call TI
MSL Peak Temp (3)
Level-1-260C-UNLIM
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74HC4066PWTG4
ACTIVE
TSSOP
PW
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HC4066DBR
DB
14
SITE 41
330
16
8.2
6.6
2.5
12
16
Q1
SN74HC4066DR
D
14
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
SN74HC4066NSR
NS
14
SITE 41
330
16
8.2
10.5
2.5
12
16
Q1
SN74HC4066PWR
PW
14
SITE 41
330
12
7.0
5.6
1.6
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74HC4066DBR
DB
14
SITE 41
346.0
346.0
33.0
SN74HC4066DR
D
14
SITE 41
346.0
346.0
33.0
SN74HC4066NSR
NS
14
SITE 41
346.0
346.0
33.0
SN74HC4066PWR
PW
14
SITE 41
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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