Freescale Semiconductor Technical Data Document Number: MC13192 Rev. 3.3, 04/2008 MC13192 MC13192 Package Information Plastic Package Case 1311-03 (QFN-32) 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard Ordering Information 1 Introduction The MC13192 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192 contains a complete 802.15.4 physical layer (PHY) modem designed for the IEEE® 802.15.4 Standard which supports peer-to-peer, star, and mesh networking. The MC13192 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13192 can be used with Freescale’s IEEE 802.15.4 MAC and BeeStack, which is Freescale’s ZigBee 2006 compliant protocol stack. Device Device Marking Package MC13192FC 13192 QFN-32 MC13192FCR2 (Tape and reel) 13192 QFN-32 Contents 1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . 11 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14 Applications Information . . . . . . . . . . . . . . . 17 Packaging Information . . . . . . . . . . . . . . . . . 23 When combined with an appropriate microcontroller (MCU), the MC13192 provide a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee™ networking. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007, 2008. All rights reserved. Features For more detailed information about MC13192 operation, refer to the MC13192 Reference Manual, (MC13192RM). Applications include, but are not limited to, the following: • Remote control and wire replacement in industrial systems such as wireless sensor networks • Factory automation and motor control • Energy Management (lighting, HVAC, etc.) • Asset tracking and monitoring Potential consumer applications include: • Home automation and control (lighting, thermostats, etc.) • Human interface devices (keyboard, mice, etc.) • Remote control • Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2 Features • • • • • • • • • • • • • Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode (compatible with the 802.15.4 Standard) Operates on one of 16 selectable channels in the 2.4 GHz band RX sensitivity of <-92 dBm (typical) at 1.0% packet error rate 0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power Recommended power supply range: 2.0 to 3.4 V Buffered transmit and receive data packets for simplified use with low cost MCUs Three power down modes for power conservation: — < 1 µA Off current — 1 µA Typical Hibernate current — 35 µA Typical Doze current (no CLKO) Four internal timer comparators available to supplement MCU resource Programmable frequency clock output (CLKO) for use by MCU Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration. Seven general purpose input/output (GPIO) signals Operating temperature range: -40 °C to 85 °C Small form factor QFN-32 Package MC13192 Technical Data, Rev. 3.3 2 Freescale Semiconductor Features — — — — 2.1 RoHS compliant Meets moisture sensitivity level (MSL) 3 260 °C peak reflow temperature Meets lead-free requirements Software Features Freescale provides a wide range of software functionality to complement the MC13192 hardware. There are three levels of application solutions: 1. Simple proprietary wireless connectivity. 2. User networks built on the 802.15.4 MAC standard. 3. ZigBee-compliant network stack. 2.1.1 • • • • 2.1.2 • • • • 2.1.3 • • • Simple MAC (SMAC) Small memory footprint (about 3 Kbytes typical) Supports point-to-point and star network configurations Proprietary networks Source code and application examples provided 802.15.4 Standard-Compliant MAC Supports star, mesh and cluster tree topologies Supports beaconed networks Supports GTS for low latency Multiple power saving modes (idle doze, hibernate) ZigBee-Compliant Network Stack Supports ZigBee 1.0 specification Supports star, mesh and tree networks Advanced Encryption Standard (AES) 128-bit security MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 3 Block Diagrams 3 Block Diagrams Figure 1 shows a simplified block diagram of the MC13192 which is an 802.15.4 Standard compatible transceiver that provides the functions required in the physical layer (PHY) specification. R F IN + R F IN - V DDA A nalog R egulator M atc hed F ilter DC D CCA Symbol B as e band M ix e r Synch & Det 1 s t IF M ix er IF = 6 5 M Hz Dec im ation F ilter Correlator LN A 2nd IF M ix er IF = 1 M Hz P M A P ow er-U p C ontrol Lo gic P ac k et P roc e s s or VBAT T Digital R egulator L V DDIN T Digital R e gulato r H V DDD C ry s tal R egulator R ec eiv e P ac k e t R A M VC O R egulator R ec e iv e R A M A rbiter V DDV C O AGC 256 M Hz R XT XEN S equ enc e M ana ger (C o ntrol L ogic ) 24 B it E v ent T im er X T A L1 C ry s t a l O s c illa t or X T A L2 16 M Hz SERIAL PERIPHERAL 4 P ro gram m able T im er C o m parators INTERFACE (SPI) V DDLO 2 P ro gram m able P res c aler ÷4 T rans m it P ac k et R A M 1 2. 45 G Hz V CO PAO+ PAO- PA T rans m it R A M A rbite r IR Q A rbiter S y m bol G ene ra tion P has e S h ift M o dulato r IR Q C LK O MUX V DDLO 1 R ST G P IO 1 G P IO 2 G P IO 3 G P IO 4 G P IO 5 G P IO 6 G P IO 7 T rans m it P ac k et R A M 2 S y n th e size r CE M OSI M IS O S P IC L K ATT N FCS G e neratio n Heade r G ene ra tion Figure 1. MC13192 Simplified Block Diagram Figure 2 shows the basic system block diagram for the MC13192 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements. MC13192 Control Logic SPI and GPIO ROM (Flash) SPI Timer RAM Arbiter RAM IRQ Arbiter Frequency Generation Digital Transceiver Analog Receiver Timer Microcontroller CPU A/D Application Analog Transmitter Network Voltage Regulators Power Up Management Buffer RAM MAC PHY Driver Figure 2. System Level Block Diagram MC13192 Technical Data, Rev. 3.3 4 Freescale Semiconductor Data Transfer Modes 4 Data Transfer Modes The MC13192 has two data transfer modes: 1. Packet Mode — Data is buffered in on-chip RAM 2. Streaming Mode — Data is processed word-by-word The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources. 4.1 Packet Structure Figure 3 shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The MC13192 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data. 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes Preamble SFD FLI Payload Data FCS Figure 3. MC13192 Packet Structure 4.2 Receive Path Description In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM. If the MC13192 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. If the MC13192 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis. Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 5 Data Transfer Modes Reported Power Level (dBm) -50 -60 -70 802.15.4 Accuracy and range Requirements -80 -90 -100 -90 -80 -70 -60 -50 Input Pow er (dBm) Figure 4. Reported Power Level versus Input Power in Clear Channel Assessment Mode Figure 5 shows energy detection/LQI reported level versus input power. NOTE For both graphs the required 802.15.4 Standard accuracy and range limits are shown. -15 Reported Power Level (dBm) -25 -35 -45 -55 -65 802.15.4 Accuracy and Range Requirements -75 -85 -85 -75 -65 -55 -45 -35 -25 -15 Input Power Level (dBm) Figure 5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator MC13192 Technical Data, Rev. 3.3 6 Freescale Semiconductor Electrical Characteristics 4.3 Transmit Path Description For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. If the MC13192 is in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13192 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted. In streaming mode, the data is fed to the MC13192 on a word-by-word basis with an interrupt serving as a notification that the MC13192 is ready for more data. This continues until the whole packet is transmitted. 5 Electrical Characteristics 5.1 Maximum Ratings Table 1. Absolute Maximum Ratings Rating Symbol Value Unit VBATT, VDDINT -0.3 to 3.6 Vdc Vin -0.3 to (VDDINT + 0.3) Pmax 10 dBm Junction Temperature TJ 125 °C Storage Temperature Range Tstg -55 to 125 °C Power Supply Voltage Digital Input Voltage RF Input Power Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: ESD protection meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 7 Electrical Characteristics 5.2 Recommended Operating Conditions Table 2. Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit VBATT, VDDINT 2.0 2.7 3.4 Vdc Input Frequency fin 2.405 - 2.480 GHz Ambient Temperature Range TA -40 25 85 °C Logic Input Voltage Low VIL 0 - 30% VDDINT V Logic Input Voltage High VIH 70% VDDINT - VDDINT V SPI Clock Rate fSPI - - 8.0 MHz RF Input Power Pmax - - 10 dBm Power Supply Voltage (VBATT = VDDINT)1 Crystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 Standard.) 1 5.3 fref 16 MHz Only If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak. DC Electrical Characteristics Table 3. DC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Ileakage ICCH ICCD ICCI ICCT ICCR - 0.2 1.0 35 500 30 37 1.0 6.0 102 800 35 42 µA µA µA µA mA mA Input Current (VIN = 0 V or VDDINT) (All digital inputs) IIN - - ±1 µA Input Low Voltage (All digital inputs) VIL 0 - 30% VDDINT V Input High Voltage (all digital inputs) VIH 70% VDDINT - VDDINT V Output High Voltage (IOH = -1 mA) (All digital outputs) VOH 80% VDDINT - VDDINT V Output Low Voltage (IOL = 1 mA) (All digital outputs) VOL 0 - 20% VDDINT V Power Supply Current (VBATT + VDDINT) Off1 Hibernate1 Doze (No CLKO)1 2 Idle Transmit Mode (0 dBm nominal output power) Receive Mode 1 To attain specified low power current, all GPIO and other digital IO must be handled properly. See Section 8.4, “Low Power Considerations. 2 CLKO frequency at default value of 32.786 kHz. MC13192 Technical Data, Rev. 3.3 8 Freescale Semiconductor Electrical Characteristics 5.4 AC Electrical Characteristics NOTE All AC parameters measured with SPI Registers at default settings except where noted and the following registers over-programmed: Register 08 = 0xFFF7 and Register 11 = 0x20FF Table 4. Receiver AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. Parameters measured at connector J6 of evaluation circuit.) Characteristic Symbol Min Typ Max Unit SENSper - -92 - dBm - -92 -87 dBm - 10 - dBm Channel Rejection for 1% PER (desired signal -82 dBm) +5 MHz (adjacent channel) -5 MHz (adjacent channel) +10 MHz (alternate channel) -10 MHz (alternate channel) >= 15 MHz - 25 31 42 41 49 - dB dB dB dB dB Frequency Error Tolerance - - 200 kHz Symbol Rate Error Tolerance - - 80 ppm Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C) Sensitivity for 1% Packet Error Rate (PER) (+25 °C) Saturation (maximum input level) SENSmax Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. Parameters measured at connector J5 of evaluation circuit.) Characteristic Symbol Min Typ Max Unit Power Spectral Density (-40 to +85 °C) Absolute limit - -47 - dBm Power Spectral Density (-40 to +85 °C) Relative limit - 47 - -3 0 3 Nominal Output Power1 Pout Maximum Output Power2 4 Error Vector Magnitude dBm - 20 35 % Output Power Control Range (-27 dBm to +4 dBm typical) - 31 - dB Over the Air Data Rate - 250 - kbps 2nd Harmonic - -42 - dBc 3rd Harmonic - -44 - dBc 1 2 EVM dBm SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 programmed to 0x00FF which sets output power to maximum. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 9 Electrical Characteristics Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted. SPI timing parameters are referenced to Figure 8. Symbol Parameter Min Typ Max Unit T0 SPICLK period 125 nS T1 Pulse width, SPICLK low 50 nS T2 Pulse width, SPICLK high 50 nS T3 Delay time, MISO data valid from falling SPICLK 15 nS T4 Setup time, CE low to rising SPICLK 15 nS T5 Delay time, MISO valid from CE low 15 nS T6 Setup time, MOSI valid to rising SPICLK 15 nS T7 Hold time, MOSI valid from rising SPICLK 15 nS RST minimum pulse width low (asserted) 250 nS Figure 6 shows a typical AC parameter evaluation circuit. J5 SMA J6 SMA 2 Y1 [email protected] 1 1 2 4 2 + C1 220pF + C2 220pF C6 0.1uF L2 VDDA VBATT VDDVCO VDDLO1 VDDLO2 XTAL2 XTAL1 GPIO7 U1 6.8nH R2 200 L1 8.2nH 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 C8 10pF RFINRFIN+ GND GND PAO+ PAOGND GPIO4 MC13192 GPIO3 GPIO2 GPIO1 RST RXTXEN ATTN CLKO SPICLK C7 10pF J1 R1 47k GPIO6 GPIO5 VDDINT VDDD IRQ CE MISO MOSI 24 23 22 21 20 19 18 17 GPIO1 R3 10k + IRQ C3 220pF Baud SEL 9 10 11 12 13 14 15 16 4 2 3 T2 3 T1 2450BL15B200 2450BL15B200 C5 9pF 5 1 5 1 C4 9pF RTXENi MOSI CE VCC RTXENi GPIO2 R4 47k 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J3 PA2 1 2 RXD GPIO2 Wake Up J4 16 MHz CLK 2 1 MCU RESET ATTN SPI_CLK MISO CLOCK Sel J7 1 2 3 MCU Interface GPIO1 ABEL RESET CLKO RESET R5 47k 1 3 5 7 9 11 13 15 17 19 R6 47k J2 2 4 6 8 10 12 14 16 18 20 HEADER 10X2 Figure 6. Parameter Evaluation Circuit MC13192 Technical Data, Rev. 3.3 10 Freescale Semiconductor Functional Description 6 Functional Description 6.1 MC13192 Operational Modes The MC13192 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics. Table 7. MC13192 Mode Definitions and Transition Times Mode Off Definition Transition Time To or From Idle All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including 10 - 25 ms to Idle IRQ Hibernate Doze Idle Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained. 7 - 20 ms to Idle Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. (300 + 1/CLKO) µs to Idle Crystal Reference Oscillator On with CLKO output available. SPI active. Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle 6.2 Serial Peripheral Interface (SPI) The host microcontroller directs the MC13192, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13192 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13192 presents data to the master on the MISO output. A typical interconnection to a microcontroller is shown in Figure 7. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 11 Functional Description MCU MC13192 Shift Register Baud Rate Generator RxD MISO TxD MOSI Sclk SPICLK Chip Enable (CE) Shift Register CE Figure 7. SPI Interface Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. 6.2.1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13192 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8. SPI Burst CE 1 2 3 4 5 6 7 8 SPICLK T4 Valid T6 T5 T2 T1 T3 T0 T7 MISO MOSI Valid Valid Figure 8. SPI Single Burst Timing Diagram SPI digital timing specifications are shown in Table 6. MC13192 Technical Data, Rev. 3.3 12 Freescale Semiconductor Functional Description 6.2.2 SPI Transaction Operation Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13192 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13192 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13192 Reference Manual, (MC13192RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9. CE Clock Burst SPICLK MISO MOSI Valid Valid Valid Header Read data Figure 9. SPI Read Transaction Diagram MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 13 Pin Connections 7 Pin Connections Table 8. Pin Function Description Pin # Pin Name Type Description Functionality 1 RFIN- RF Input LNA negative differential input. 2 RFIN+ RF Input LNA positive differential input. 3 Not Used Tie to Ground. 4 Not Used Tie to Ground. 5 PAO+ RF Output /DC Input Power Amplifier Positive Output. Open drain. Connect to VDDA. 6 PAO- RF Output/DC Input Power Amplifier Negative Output. Open drain. Connect to VDDA. 7 SM 8 GPIO41 9 Test mode pin. Tie to Ground Tie to Ground for normal operation Digital Input/ Output General Purpose Input/Output 4. See Footnote 1 GPIO31 Digital Input/ Output General Purpose Input/Output 3. See Footnote 1 10 GPIO21 Digital Input/ Output General Purpose Input/Output 2. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” indicator. See Footnote 1 11 GPIO11 Digital Input/ Output General Purpose Input/Output 1. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” indicator. See Footnote 1 12 RST Digital Input Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. 13 RXTXEN2 Digital Input Active High. Low to high transition initiates RX or TX See Footnote 2 sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. 14 ATTN2 Digital Input Active Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle. 15 CLKO Digital Output Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. 16 SPICLK2 Digital Clock Input External clock input for the SPI interface. See Footnote 2 17 MOSI2 Digital Input Master Out/Slave In. Dedicated SPI data input. See Footnote 2 18 MISO3 Digital Output Master In/Slave Out. Dedicated SPI data output. See Footnote 3 19 CE2 Digital Input Active Low Chip Enable. Enables SPI transfers. See Footnote 2 See Footnote 2 MC13192 Technical Data, Rev. 3.3 14 Freescale Semiconductor Pin Connections Table 8. Pin Function Description (continued) Pin # Pin Name Type Description Functionality 20 IRQ Digital Output Active Low Interrupt Request. Open drain device. Programmable 40 kΩ internal pull-up. Interrupt can be serviced every 6 µs with <20 pF load. Optional external pull-up must be >4 kΩ. 21 VDDD Power Output Digital regulated supply bypass. Decouple to ground. 22 VDDINT Power Input Digital interface supply & digital regulator input. Connect to Battery. 2.0 to 3.4 V. Decouple to ground. 23 GPIO51 Digital Input/Output General Purpose Input/Output 5. See Footnote 1 24 GPIO61 Digital Input/Output General Purpose Input/Output 6. See Footnote 1 25 GPIO71 Digital Input/Output General Purpose Input/Output 7. See Footnote 1 26 XTAL1 Input Crystal Reference oscillator input. Connect to 16 MHz crystal and load capacitor. 27 XTAL2 Input/Output Crystal Reference oscillator output Note: Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13192 Reference Manual for details. Connect to 16 MHz crystal and load capacitor. 28 VDDLO2 Power Input LO2 VDD supply. Connect to VDDA externally. 29 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally. 30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 31 VBATT Power Input Analog voltage regulators Input. Connect to Battery. Decouple to ground. 32 VDDA Power Output Analog regulated supply Output. Connect to directly Decouple to ground. VDDLO1 and VDDLO2 externally and to PAO± through a frequency trap. Note: Do not use this pin to supply circuitry external to the chip. EP Ground External paddle / flag ground. Connect to ground. 1 The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. 3 By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 15 Pin Connections GPIO7 XTAL1 XTAL2 VDDLO2 VDDLO1 VDDVCO VBATT GPIO6 VDDD EP PAO+ IRQ MC13192 PAO- CE SM MISO GPIO4 9 10 11 12 13 14 15 SPICLK 8 25 NC CLKO 7 26 VDDINT ATTN 6 27 NC RXTXEN 5 28 RST 4 29 GPIO5 GPIO1 3 30 RFIN+ GPIO2 2 RFIN- GPIO3 1 31 VDDA 32 MOSI 24 23 22 21 20 19 18 17 16 Figure 10. Pin Connections (Top View) MC13192 Technical Data, Rev. 3.3 16 Freescale Semiconductor Applications Information 8 Applications Information This section provides application specific information regarding crystal oscillator reference frequency, a basic design example for interfacing the MC13192 to an MCU and recommended crystal usage. 8.1 Crystal Oscillator Reference Frequency The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13192 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. Freescale requires the use of a 16 MHz crystal with a <9 pF load capacitance. The MC13192 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13192 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately ±15%. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 17 Applications Information Since the MC13192 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis. A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the 802.15.4 Standard. 8.2 Design Example Figure 11 shows a basic application schematic for interfacing the MC13192 with an MCU. Table 9 lists the Bill of Materials (BOM). The MC13192 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design. The 16 MHz crystal should be mounted close to the MC13192 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table 10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. Other crystals are listed in Section 8.3, “Crystal Requirements. VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13192. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO. When the MC13192 is used in Stream Mode, as with 802.15.4 MAC/PHY software, the MC13192 GPIO1 functions as an “Out of Idle” indicator and GPIO2 functions as a “CRC Valid” / Clear Channel Assessment (CCA) result indicator and are not available for general purpose use. MC13192 Technical Data, Rev. 3.3 18 Freescale Semiconductor Freescale Semiconductor MCU CLK GPIO GPIO GPIO GPIO GPIO GPIO 3V0_RF R1 470K C1 1μF C2 100nF VDDA C3 100nF C4 100nF EP 32 29 28 21 30 31 22 15 14 13 12 20 IRQ 3V0_BB 19 18 17 16 SS MISO MOSI SCLK MC13192 GND VDDA VDDLO1 VDDLO2 VDDD VDDVCO VBATT VDDINT CLKO ATTNB RXTXEN RSTB IRQB CEB MISO MOSI SPICLK GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 IC1 XTAL2 XTAL1 Not Used PAO_M PAO_P Not Used Not Used RIN_P RIN_M 27 26 7 6 5 4 3 2 1 16.000MHz X1 100_Ohm4 100_Ohm3 100_Ohm2 100_Ohm1 C6 6.8pF C5 6.8pF L2 8.2nH L1 6.8nH 3 2 4 C8 10pF VDDA C7 10pF 1 50_Ohm1 1 5 6 50_Ohm2 LDB212G4020C-001 Z2 LDB212G4020C-001 5 6 3 Z1 2 4 C10 10pF 2 50_Ohm3 3 50_Ohm4 1 C9 10pF μPG 2012TK-E2 OUT2 VDD OUT1 IN GND VCONT IC2 6 4 5 10pF C11 L3 8.2nH 50_Ohm6 C12 0.5pF R3 0 J1 SMA Receptacle, Female 2 3 4 5 ANT1 F_Antenna 50_Ohm7 R2 0 1 11 10 9 8 23 24 25 Applications Information Figure 11. MC13192 Configured With a MCU MC13192 Technical Data, Rev. 3.3 19 Applications Information Table 9. MC13192 to MCU Bill of Materials (BOM) 8.3 Item Quantity Reference Part Manufacturer 1 1 ANT1 F_Antenna Printed wire 2 1 C1 1 μF 3 3 C2, C3, C4 100 nF 4 2 C5, C6 6.8 pF 5 5 C7, C8, C9, C10, C11 10 pF 6 1 C12 0.5 pF 7 1 IC1 MC13192 Freescale Semiconductor 8 1 IC2 μPG2012TK-E2 NEC 9 1 J1 SMA Receptacle, Female 10 1 L1 6.8 nH 11 2 L2, L3 8.2 nH 12 1 R1 470 kΩ 13 2 R2, R3 0Ω 14 1 X1 16.000 MHz, Type DSX321G, ZD00882 KDS, Daishinku Corp 15 2 Z1, Z2 LDB212G4020C-001 Murata Crystal Requirements The suggested crystal specification for the MC13192 is shown in Table 10. A number of the stated parameters are related to desired package, desired temperature range and use of crystal capacitive load trimming. For more design details and suggested crystals, see application note AN3251, Reference Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x. Table 10. MC13192 Crystal Specifications1 Parameter Frequency Frequency tolerance (cut tolerance)2 Frequency stability (temperature drift)3 Aging 4 Equivalent series resistance5 Load capacitance 6 Value Unit Condition 16.000000 MHz ± 10 ppm at 25 °C ± 15 ppm Over desired temperature range ±2 ppm max 43 Ω max 5-9 pF MC13192 Technical Data, Rev. 3.3 20 Freescale Semiconductor Applications Information Table 10. MC13192 Crystal Specifications1 (continued) Parameter Shunt capacitance Value Unit <2 pF Mode of oscillation 1 2 3 4 5 6 8.4 • Condition max fundamental User must be sure manufacturer specifications apply to the desired package. A wider frequency tolerance may acceptable if application uses trimming at production final test. A wider frequency stability may be acceptable if application uses trimming at production final test. A wider aging tolerance may be acceptable if application uses trimming at production final test. Higher ESR may be acceptable with lower load capacitance. Lower load capacitance can allow higher ESR and is better for low temperature operation in Doze mode. Low Power Considerations Program and use the modem IO pins properly for low power operation — All unused modem GPIOx signals must be used one of 2 ways: – If the Off mode is to be used as a long term low power mode, unused GPIO should be tied to ground. The default GPIO mode is an input and there will be no conflict. – If only Hibernate and/or Doze modes are used as long term low power modes, the GPIO should programmed as outputs in the low state. — When modem GPIO are used as outputs: – Pullup resistors should be provided (can be provided by the MCU IO pin if tied to the MCU) if the modem Off condition is to be used as a long term low power mode. – During Hibernate and/or Doze modes, the GPIO will retain its programmed output state. — If the modem GPIO is used as an input, the GPIO should be driven by its source during all low power modes or a pullup resistor should be provided. — Digital outputs IRQ, MISO, and CLKO: – MISO - is always an output. During Hibernate, Doze, and active modes, the default condition is for the MISO output to go to tristate when CE is de-asserted, and this can cause a problem with the MCU because one of its inputs can float. Program Control_B Register 07, Bit 11, miso_hiz_en = 0 so that MISO is driven low when CE is de-asserted. As a result, MISO will not float when Doze or Hibernate Mode is enabled. – IRQ - is an open drain output (OD) and should always have a pullup resistor (typically provided by the MCU IO). IRQ acts as the interrupt request output. NOTE It is good practice to have the IRQ interrupt input to the MCU disabled during the hardware reset to the modem. After releasing the modem hardware reset, the interrupt request input to the MCU can then be enabled to await the IRQ that signifies the modem is ready and in Idle mode; this can prevent a possible extraneous false interrupt request. – CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 21 Applications Information • If the MCU is also going to be used in low power modes, be sure that all unused IO are programmed properly for low power operation (typically best case is as outputs in the low state). The MC13192 is commonly used with the Freescale MC9S08GT/GB 8-bit devices. For these MCUs: — Use only STOP2 and STOP3 modes (not STOP1) with these devices where the GPIO states are retained. The MCU must retain control of the MC13192 IO during low power operation. — As stated above all unused GPIO should be programmed as outputs low for lowest power and no floating inputs. — MC9S08GT devices have IO signals that are not pinned-out on the package. These signals must also be initialized (even though they cannot be used) to prevent floating inputs. MC13192 Technical Data, Rev. 3.3 22 Freescale Semiconductor Packaging Information 9 Packaging Information PIN 1 INDEX AREA 0.1 0.1 C 2X 5 A M C 0.1 2X C G 1.0 0.8 1.00 0.75 0.05 C 5 5 (0.25) 0.05 0.00 (0.5) C SEATING PLANE DETAIL G VIEW ROTATED 90° CLOCKWISE M B 0.1 C A DETAIL M PIN 1 INDEX 3.25 2.95 EXPOSED DIE ATTACH PAD 25 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12°. B 32 24 1 0.25 3.25 2.95 0.1 A C B 0.217 0.137 16 32X 0.5 8 17 32X 0.3 VIEW M-M 0.217 0.137 N 9 0.5 28X 0.30 0.18 (0.25) 0.1 M C 0.05 M C A (0.1) B DETAIL S PREFERRED BACKSIDE PIN 1 INDEX (45 5) 32X 0.065 0.015 DETAIL S 0.60 0.24 (1.73) 0.60 0.24 (0.25) DETAIL N DETAIL N PREFERRED CORNER CONFIGURATION DETAIL M PREFERRED BACKSIDE PIN 1 INDEX CORNER CONFIGURATION OPTION 4 4 5 1.6 1.5 DETAIL T BACKSIDE PIN 1 INDEX (90 ) 0.475 0.425 2X R DETAIL M BACKSIDE PIN 1 INDEX OPTION 0.39 0.31 0.25 0.15 DETAIL M BACKSIDE PIN 1 INDEX OPTION 2X 0.1 0.0 DETAIL T BACKSIDE PIN 1 INDEX OPTION Figure 12. Outline Dimensions for QFN-32, 5x5 mm (Case 1311-03, Issue E) MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 23 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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