FREESCALE 68HC705PL4

Freescale Semiconductor, Inc...
Freescale Semiconductor
HC05PL4GRS/H
REV 2.0
68HC05PL4
68HC05PL4B
68HC705PL4
68HC705PL4B
SPECIFICATION
(General Release)
April 30, 1998
Consumer Systems Group
Semiconductor Products Sector
© Freescale Semiconductor, Inc., 2004. All rights reserved.
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Freescale Semiconductor, Inc.
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April 30, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
FEATURES ...................................................................................................... 1-1
MCU BLOCK DIAGRAM .................................................................................. 1-2
PIN ASSIGNMENTS ........................................................................................ 1-3
PIN DESCRIPTIONS ....................................................................................... 1-4
VDD, VSS .................................................................................................... 1-4
OSC1, OSC2 ............................................................................................... 1-4
RESET......................................................................................................... 1-4
LED/IRQ ...................................................................................................... 1-4
PA0, PA1/DTMF, PA2/TCAP, PA3/TCMP, PA4-PA6 .................................. 1-5
PB0/KBI0-PB3/KBI3, PB4-PB7.................................................................... 1-5
PC0-PC7...................................................................................................... 1-6
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
2.5
MEMORY MAP ................................................................................................ 2-1
I/O REGISTERS .............................................................................................. 2-2
RAM ................................................................................................................. 2-2
ROM................................................................................................................. 2-2
COP WATCHDOG REGISTER (COPR).......................................................... 2-2
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A) ....................................................................................... 3-2
INDEX REGISTER (X) ..................................................................................... 3-2
STACK POINTER (SP) .................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-2
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
Half Carry Bit (H-Bit) .................................................................................... 3-3
Interrupt Mask (I-Bit) .................................................................................... 3-3
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-3
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
4.4.1
INTERRUPT VECTORS .................................................................................. 4-1
INTERRUPT PROCESSING ........................................................................... 4-2
SOFTWARE INTERRUPT ............................................................................... 4-4
EXTERNAL INTERRUPT ................................................................................ 4-4
LED/IRQ Pin ................................................................................................ 4-4
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TABLE OF CONTENTS
Section
Page
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4.4.2
Miscellaneous Control and Status Register................................................. 4-5
4.5
16-BIT TIMER INTERRUPTS .......................................................................... 4-6
4.5.1
Input Capture Interrupt................................................................................. 4-6
4.5.2
Output Compare Interrupt............................................................................ 4-6
4.5.3
Timer Overflow Interrupt .............................................................................. 4-6
4.6
8-BIT TIMER INTERRUPT .............................................................................. 4-6
4.7
KEYBOARD INTERRUPT ............................................................................... 4-7
SECTION 5
RESETS
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.5
POWER-ON RESET ........................................................................................ 5-1
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS ........................................................................................ 5-2
Power-On Reset (POR) ............................................................................... 5-3
Computer Operating Properly (COP) Reset ................................................ 5-3
Illegal Address Reset................................................................................... 5-4
RESET STATES OF SUBSYSTEM IN MCU ................................................... 5-5
CPU ............................................................................................................. 5-5
I/O Registers................................................................................................ 5-5
8-Bit Timer ................................................................................................... 5-5
16-Bit Programmable Timer......................................................................... 5-5
Keyboard Interrupt Interface ........................................................................ 5-6
6-bit DAC Subsystem .................................................................................. 5-6
System Clock Option Subsystem ................................................................ 5-6
Miscellaneous Subsystem ........................................................................... 5-6
RESET CHARACTERISTICS .......................................................................... 5-7
SECTION 6
OPERATING MODES
6.1
OPERATING MODES...................................................................................... 6-1
6.1.1
Single-chip (Normal) Mode .......................................................................... 6-1
6.1.2
Self-check Mode .......................................................................................... 6-1
6.2
LOW POWER MODES .................................................................................... 6-2
6.2.1
STOP Mode ................................................................................................. 6-2
6.2.2
WAIT Mode.................................................................................................. 6-2
SECTION 7
INPUT/OUTPUT PORTS
7.1
PARALLEL PORTS ......................................................................................... 7-1
7.1.1
Port Data Registers ..................................................................................... 7-2
7.1.2
Port Data Direction Registers ...................................................................... 7-2
7.2
PORT A............................................................................................................ 7-2
7.3
PORT B............................................................................................................ 7-3
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TABLE OF CONTENTS
Section
7.4
7.5
Page
PORT C ........................................................................................................... 7-3
SUMMARY OF PORT A AND PORT B SHARED PINS .................................. 7-3
SECTION 8
SYSTEM CLOCKS
8.1
SYSTEM CLOCK SOURCE AND FREQUENCY OPTION.............................. 8-1
Freescale Semiconductor, Inc...
SECTION 9
16-BIT PROGRAMMABLE TIMER
9.1
9.2
9.3
9.4
9.5
9.5.1
9.6
9.7
9.8
TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4
INPUT CAPTURE REGISTERS ...................................................................... 9-5
OUTPUT COMPARE REGISTERS ................................................................. 9-6
TIMER CONTROL REGISTER (TCR) ............................................................. 9-8
Miscellaneous Control and Status Register for Timer16 ............................. 9-9
TIMER STATUS REGISTER (TSR)............................................................... 9-10
16-BIT TIMER OPERATION DURING WAIT MODE ..................................... 9-11
16-BIT TIMER OPERATION DURING STOP MODE .................................... 9-11
SECTION 10
8-BIT TIMER
10.1
10.2
10.3
10.4
10.5
10.6
OVERVIEW.................................................................................................... 10-1
TIMER8 CONTROL AND STATUS REGISTER (T8CSR) ............................. 10-2
TIMER8 COUNTER REGISTER (T8CNTR) .................................................. 10-3
COMPUTER OPERATING PROPERLY (COP) WATCHDOG ...................... 10-3
8-BIT TIMER OPERATION DURING WAIT MODE ....................................... 10-4
8-BIT TIMER OPERATION DURING STOP MODE ...................................... 10-4
SECTION 11
DIGITAL TO ANALOG CONVERTER
11.1
11.2
11.3
11.4
DAC CONTROL AND DATA REGISTER ...................................................... 11-1
DAC OPERATION DURING WAIT MODE .................................................... 11-1
DAC OPERATION DURING STOP MODE.................................................... 11-1
DAC CHARACTERISTICS ............................................................................ 11-2
SECTION 12
INSTRUCTION SET
12.1 ADDRESSING MODES ................................................................................. 12-1
12.1.1 Inherent...................................................................................................... 12-1
12.1.2 Immediate .................................................................................................. 12-1
12.1.3 Direct ......................................................................................................... 12-2
12.1.4 Extended.................................................................................................... 12-2
12.1.5 Indexed, No Offset..................................................................................... 12-2
12.1.6 Indexed, 8-Bit Offset .................................................................................. 12-2
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TABLE OF CONTENTS
Section
Freescale Semiconductor, Inc...
12.1.7
12.1.8
12.1.9
12.1.10
12.1.11
12.1.12
12.1.13
12.1.14
12.1.15
Page
Indexed, 16-Bit Offset ................................................................................ 12-3
Relative...................................................................................................... 12-3
Instruction Types ....................................................................................... 12-3
Register/Memory Instructions .................................................................... 12-4
Read-Modify-Write Instructions ................................................................. 12-5
Jump/Branch Instructions .......................................................................... 12-5
Bit Manipulation Instructions...................................................................... 12-7
Control Instructions.................................................................................... 12-7
Instruction Set Summary ........................................................................... 12-8
SECTION 13
ELECTRICAL SPECIFICATIONS
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
MAXIMUM RATINGS..................................................................................... 13-1
OPERATING TEMPERATURE RANGE ........................................................ 13-1
THERMAL CHARACTERISTICS ................................................................... 13-1
SUPPLY CURRENT CHARACTERISTICS ................................................... 13-2
DC ELECTRICAL CHARACTERISTICS (4V)................................................ 13-3
DC ELECTRICAL CHARACTERISTICS (2V)................................................ 13-4
CONTROL TIMING (4V)................................................................................ 13-5
CONTROL TIMING (2V)................................................................................ 13-5
SECTION 14
MECHANICAL SPECIFICATIONS
14.1
14.2
14.3
28-PIN PDIP (CASE 710) .............................................................................. 14-1
28-PIN SOIC (CASE 751F)............................................................................ 14-1
28-PIN SSOP ................................................................................................. 14-2
APPENDIX A
MC68HC705PL4
A.1
A.2
A.3
A.4
A.4.1
A.4.2
A.5
A.6
INTRODUCTION .............................................................................................A-1
MEMORY .........................................................................................................A-1
BOOTLOADER MODE ....................................................................................A-1
EPROM PROGRAMMING ...............................................................................A-1
EPROM Program Control Register (PCN)...................................................A-2
Programming Sequence ..............................................................................A-3
EPROM PROGRAMMING SPECIFICATIONS ................................................A-3
SUPPLY CURRENT CHARACTERISTICS .....................................................A-6
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GENERAL RELEASE SPECIFICATION
LIST OF FIGURES
Freescale Semiconductor, Inc...
Figure
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
7-1
8-1
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
10-1
10-2
10-3
11-1
Title
Page
MC68HC05PL4 Block Diagram ....................................................................... 1-2
MC68HC05PL4 Pin Assignment ...................................................................... 1-3
MC68HC05PL4B Pin Assignment ................................................................... 1-3
Oscillator Connections ..................................................................................... 1-4
Miscellaneous Control and Status Register (MICSR) ...................................... 1-5
MC68HC05PL4 Memory Map .......................................................................... 2-1
COP Watchdog Register (COPR) .................................................................... 2-2
I/O Registers $0000-$000F.............................................................................. 2-3
I/O Registers $0010-$001F.............................................................................. 2-4
MC68HC05 Programming Model ..................................................................... 3-1
Interrupt Stacking Order................................................................................... 4-2
Interrupt Flowchart ........................................................................................... 4-3
External Interrupt Logic .................................................................................... 4-5
Miscellaneous Control and Status Register (MICSR) ...................................... 4-5
Pull-Up Enable Register (PUER) ..................................................................... 4-7
Keyboard Interrupt Enable Register (KIER) ..................................................... 4-7
Keyboard Interrupt Flag Register (KIFR) ......................................................... 4-7
Reset Sources ................................................................................................. 5-1
Miscellaneous Control and Status Register (MICSR) ...................................... 5-2
COP Watchdog Block Diagram........................................................................ 5-3
COP Watchdog Register (COPR) .................................................................... 5-3
Miscellaneous Control and Status Register (MICSR) ...................................... 5-4
Stop Recovery Timing Diagram ....................................................................... 5-7
Internal Reset Timing Diagram ........................................................................ 5-8
STOP/WAIT Flowchart..................................................................................... 6-3
Port Input/Output Circuitry ............................................................................... 7-1
System Clock Control Register (SYSCR) ........................................................ 8-1
Programmable Timer Block Diagram ............................................................... 9-1
Timer Counter and Register Block Diagram .................................................... 9-2
Programmable Timer Registers (TMRH, TMRL).............................................. 9-3
Alternate Counter Block Diagram .................................................................... 9-4
Alternate Counter Registers (ACRH, ACRL) ................................................... 9-4
Timer Input Capture Block Diagram................................................................. 9-5
Input Capture Registers (ICRH, ICRL)............................................................. 9-6
Timer Output Compare Block Diagram ............................................................ 9-7
Output Compare Registers (OCRH, OCRL) .................................................... 9-7
Timer Control Register (TCR) .......................................................................... 9-8
Miscellaneous Control and Status Register (MISCR) ...................................... 9-9
Timer Status Registers (TSR) ........................................................................ 9-10
Timer8 Block Diagram ................................................................................... 10-1
Timer8 Control and Status Register............................................................... 10-2
Timer8 Counter Register................................................................................ 10-3
DAC Control and Data Register ..................................................................... 11-1
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REV 2.0
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LIST OF FIGURES
Figure
Page
MC68HC705PL4B Memory Map .....................................................................A-2
EPROM Programming Sequence ....................................................................A-4
MC68HC705PL4 Pin Assignment ....................................................................A-5
MC68HC705PL4B Pin Assignment .................................................................A-5
Freescale Semiconductor, Inc...
A-1
A-2
A-3
A-4
Title
MC68HC05PL4
REV 2.0
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LIST OF TABLES
Freescale Semiconductor, Inc...
Table
1-1
4-1
5-1
6-1
7-1
7-2
8-1
8-2
9-1
12-1
12-2
12-3
12-4
12-5
12-6
12-7
A-1
A-2
Title
Page
MC68HC05PL4 and MC68HC05PL4B Differences ......................................... 1-1
Vector Address for Interrupts and Reset.......................................................... 4-1
Reset Characteristics ....................................................................................... 5-7
Operation Mode Condition After Reset ............................................................ 6-1
I/O Pin Functions ............................................................................................. 7-2
Port A and Port B Shared Pins ........................................................................ 7-3
System Clock Divider Select ............................................................................ 8-1
System Clock Source Select............................................................................ 8-1
Output Compare Initialization Example............................................................ 9-8
Register/Memory Instructions ........................................................................ 12-4
Read-Modify-Write Instructions ..................................................................... 12-5
Jump and Branch Instructions ....................................................................... 12-6
Bit Manipulation Instructions .......................................................................... 12-7
Control Instructions ........................................................................................ 12-7
Instruction Set Summary .............................................................................. 12-8
Opcode Map ................................................................................................ 12-14
MC68HC705PL4 and MC68HC705PL4B Differences .....................................A-1
EPROM Programming Electrical Characteristics .............................................A-3
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LIST OF TABLES
Title
Page
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Table
MC68HC05PL4
REV 2.0
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GENERAL RELEASE SPECIFICATION
SECTION 1
GENERAL DESCRIPTION
Freescale Semiconductor, Inc...
The MC68HC05PL4 HCMOS microcontroller is a member of the M68HC05 Family of low-cost single-chip microcontroller units (MCUs). This MCU is designed
speci cally f or the handset and base set of cost-sensitive CT0/1 analog cordless
phones.
References to MC68HC05PL4 apply
MC68HC05PL4B, unless otherwise stated.
to
both
MC68HC05PL4
and
Table 1-1. MC68HC05PL4 and MC68HC05PL4B Differences
Device
Pin 27
MC68HC05PL4
MC68HC05PL4B
1.1
PA0
OSC2
FEATURES
•
Industry standard 8-bit M68HC05 CPU core
•
Bus frequency: 2.56MHz @ 4V and 1MHz @ 2V
•
Built-in low-frequency RC oscillator (500kHz and 20kHz)
•
OSC input pin (OSC output pin on MC68HC05PL4B)
•
256 bytes of user RAM
•
4k-bytes of user ROM
•
ROM security
•
23 (22 for MC68HC05PL4B) bidirectional I/O lines with:
– 4 keyboard interrupts with pull-up resistor
– 6 high current sink pins
•
Open-drain output for LED drive
•
Multiplexed DTMF output with built-in 6-bit D/A
•
16-bit programmable timer with input capture and output compare
functions
•
Reloadable 8-bit event timer
•
COP watchdog reset
•
Power saving STOP and WAIT modes
•
Available in 28-pin PDIP, SOIC, and SSOP packages
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REV 2.0
GENERAL DESCRIPTION
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1-1
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1.2
April 30, 1998
MCU BLOCK DIAGRAM
USER ROM - 4k BYTES
4
DDR B
PORT B
KEYBOARD
INTERRUPT
USER RAM - 256 BYTES
7
15
ACCUMULATOR
0
INDEX REGISTER
12
5
0
0 0 0 0 0 1 1
STACK POINTER
4
0
PB4- PB7
PA6
PA5
PA4
PA3/TCMP
PA2/TCAP
PA1/DTMF
PA0†
DDR A
PORT A
7
4
0
DTMF
MODULE
PROGRAM COUNTER
7
0
1 1 1 H I N Z C
CONDITION CODE REGISTER
RESET
OSC1
††
OSC2
LED
DRIVE
VERY LOW
OSC
FREQUENCY OSC
(÷ N OPTIONAL) (RC: 500kHz or 20kHz)
LED/IRQ
16-BIT
PROGRAMMABLE TIMER
8-BIT RELOADABLE
EVENT TIMER
VDD
VSS
WATCHDOG
SYSTEM
POWER
DDR C
PORT C
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M68HC05
CPU
PB0/KBI0
PB1/KBI1
PB2/KBI2
PB3/KBI3
†Available on MC68HC05PL4 only.
††Available on MC68HC05PL4B only.
8
PC0 - PC7
Figure 1-1. MC68HC05PL4 Block Diagram
NOTE
A line over a signal name indicates an active low signal. Any reference to voltage,
current, or frequency speci ed in the following sections will refer to the nominal
values. The exact values and their tolerance or limits are speci ed in Electr ical
Speci cations section.
1-2
GENERAL DESCRIPTION
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PIN ASSIGNMENTS
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1.3
GENERAL RELEASE SPECIFICATION
VSS
1
28
OSC1
VDD
2
27
PA0
PC7
3
26
PC0
PC6
4
25
PC1
RESET
5
24
PA1/DTMF
PB7
6
23
PA2/TCAP
PB6
7
22
PA3/TCMP
PB5
8
21
PA4
PB4
9
20
PA5
PB3/KBI3
10
19
PA6
PC5
11
18
PC2
PC4
12
17
PC3
PB2/KBI2
13
16
LED/IRQ
PB1/KBI1
14
15
PB0/KBI0
Figure 1-2. MC68HC05PL4 Pin Assignment
VSS
1
28
OSC1
VDD
2
27
OSC2
PC7
3
26
PC0
PC6
4
25
PC1
RESET
5
24
PA1/DTMF
PB7
6
23
PA2/TCAP
PB6
7
22
PA3/TCMP
PB5
8
21
PA4
PB4
9
20
PA5
PB3/KBI3
10
19
PA6
PC5
11
18
PC2
PC4
12
17
PC3
PB2/KBI2
13
16
LED/IRQ
PB1/KBI1
14
15
PB0/KBI0
Figure 1-3. MC68HC05PL4B Pin Assignment
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1.4
April 30, 1998
PIN DESCRIPTIONS
The following paragraphs give a description of each functional pin.
1.4.1 VDD, VSS
Power is supplied to the MCU using these pins. VDD is the positive supply and
VSS is the ground pin.
1.4.2 OSC1, OSC2
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OSC2 is only available on MC68HC05PL4B.
The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the
following con gur ations are available:
1. A crystal or ceramic resonator as shown in Figure 1-4(a).
2. An external clock signal as shown in Figure 1-4(b).
The external oscillator clock frequency, fOSC, is divided by two to produce the
internal operating frequency, fOP.
MCU
MCU
2 MΩ
OSC1
OSC2
OSC1
OSC2
UNCONNECTED
EXTERNAL CLOCK
(a) Crystal or
Ceramic Resonator
Connections
(c) External
Clock Source
Connection
Figure 1-4. Oscillator Connections
1.4.3 RESET
This active low input-only pin is used to reset the MCU to a known start-up state.
The RESET pin has an Schmitt trigger circuit as part of its input to improve noise
immunity.
1.4.4 LED/IRQ
This pin has two functions, con gured b y the IRQEN bit in the Miscellaneous Control and Status Register, at $1C (MISCR).
When this pin is IRQ, it drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function uses the IRQS bit in the MISCR to provide either
only negative edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering. If the MISCR bit is set to enable level-sensitive
1-4
GENERAL DESCRIPTION
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GENERAL RELEASE SPECIFICATION
triggering, the LED/IRQ pin requires an external resistor to VDD for “wired-OR”
operation. If the LED/IRQ is not used, it must be tied to the VDD supply. The
contains an internal Schmitt trigger as part of its input to improve noise immunity.
When this pin is LED, the LED bit in the MISCR controls the on/off function of the
connected LED. This LED pin sinks current via an internal pulldown resistor.
MICSR
R
$001C
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
IRQEN
IRQS
TCMPEN
TCAPEN
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
LED
COPON
POR
0
0
0
0
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Figure 1-5. Miscellaneous Control and Status Register (MICSR)
IRQEN — External Interrupt Request Enable
0 = LED/IRQ pin con gured as LED dr ive pin.
1 = LED/IRQ pin con gured as IRQ input pin, for external interrupts.
LED — LED Drive Output Control
1 = Enable internal pulldown resistor, pin is logic low.
0 = Disable internal pulldown resistor, pin is in high impedance state.
1.4.5 PA0, PA1/DTMF, PA2/TCAP, PA3/TCMP, PA4-PA6
These eight I/O lines comprise port A, a general purpose bidirectional I/O port.
The state of any pin is software programmable and all port B lines are con gured
as inputs during power-on or reset.
PA0 is only available on MC68HC05PL4.
PA1 is shared with DTMF output of the DAC subsystem. This pin is con gured as
an output pin for DTMF.
PA2 is shared with TCAP input of the 16-bit timer. This pin is con gured as an
input pin for TCAP.
PA3 is shared with TCMP output of the 16-bit timer. This pin is con gured as an
output pin for TCMP.
PA5 and PA6 have high current sinking capability; see Electrical Speci cations
section for values.
1.4.6 PB0/KBI0-PB3/KBI3, PB4-PB7
These eight I/O lines comprise port B, a general purpose bidirectional I/O port.
The state of any pin is software programmable and all port B lines are con gured
as inputs during power-on or reset.
All port B pins have internal pullups which can be individually enabled by software.
PB0-PB3 also have keyboard interrupt capability, which can be individually
enabled.
MC68HC05PL4
REV 2.0
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1.4.7 PC0-PC7
These eight I/O lines comprise port C, a general purpose bidirectional I/O port.
The state of any pin is software programmable and all port C lines are con gured
as inputs during power-on or reset.
Freescale Semiconductor, Inc...
PC4-PC7 have high current sinking capability; see Electrical Speci cations section for values.
1-6
GENERAL DESCRIPTION
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SECTION 2
MEMORY
This section describes the organization of the memory on the MC68HC05PL4.
Freescale Semiconductor, Inc...
2.1
MEMORY MAP
The CPU can address 8k-bytes of memory space as shown in Figure 2-1. The
ROM portion of the memory holds the program instructions, xed data, user
de ned v ectors, and interrupt service routines. The RAM portion of memory holds
variable data. I/O registers are memory mapped so that the CPU can access their
locations in the same way that it accesses all other memory locations.
$0000
$001F
$0020
$00C0
$00FF
$011F
$0120
I/O REGISTERS
32 BYTES
USER RAM
BYTES
STACK 256
64 BYTES
UNUSED
$0DFF
$0E00
USER ROM
4096 BYTES
$1DFF
$1E00
$1FEF
$1FF0
$1FFF
SELF-CHECK ROM
496 BYTES
USER VECTORS
16 BYTES
RESERVED
$1FF0-$1FF1
RESERVED
$1FF2-$1FF3
KEYBOARD
$1FF4-$1FF5
8-BIT TIMER
$1FF6-$1FF7
16-BIT TIMER
$1FF8-$1FF9
IRQ
$1FFA-$1FFB
SWI
$1FFC-$1FFD
RESET
$1FFE-$1FFF
Figure 2-1. MC68HC05PL4 Memory Map
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I/O REGISTERS
The rst 32 addresses of the memor y space, $0000-$001F, are the I/O section.
One I/O register is located outside the 32-byte I/O section, which is the Computer
Operating Properly (COP) register mapped at $1FF0.
The bit assignment of each I/O register is described in the respective sections and
summarized in Figure 2-3 and Figure 2-4.
Freescale Semiconductor, Inc...
2.3
RAM
The 256 addresses from $0020 to $01FF serve as both user RAM and the stack
RAM. The CPU uses v e RAM bytes to save all CPU register contents before processing an interrupt. During a subroutine call, the CPU uses two bytes to store the
return address. The stack pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The CPU
may overwrite data in the RAM during a subroutine or during the interrupt stacking
operation.
2.4
ROM
The 4096 bytes of user ROM is located from address $0E00 to $1DFF.
Addresses $1FF0 to $1FFF contain 16 bytes of ROM reserved for user vectors.
2.5
COP WATCHDOG REGISTER (COPR)
Writing “0” to the COPC bit in the COP watchdog register ($1FF0) resets the COP
watchdog timer. This is a write only register; writing a “1” to COPC has no effect.
COPR
R
$1FF0
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
U
U
U
U
U
U
U
BIT 0
COPC
U
Figure 2-2. COP Watchdog Register (COPR)
2-2
MEMORY
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ADDR
$0000
$0001
Freescale Semiconductor, Inc...
$0002
REGISTER
ACCESS
Port A Data
R
PORTA
W
Port B Data
R
PORTB
W
Port C Data
R
PORTC
W
$0003
RESERVED
$0004
RESERVED
$0005
$0006
$0007
$000A
$000B
$000C
$000D
$000E
$000F
BIT 3
BIT 2
BIT 1
BIT 0
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
PUL7
PUL6
PUL5
PUL4
PUL3
PUL2
PUL1
PUL0
KIE3
KIE2
KIE1
KIE0
KIF3
KIF2
KIF1
KIF0
T8EN
PS2
PS1
PS0
W
DDRA
Port B Data Direction
R
DDRB
W
Port C Data Direction
R
DDRC
W
RESERVED
BIT 4
R
R
$0009
BIT 5
R
W
RESERVED
BIT 6
W
Port A Data Direction
$0008
BIT 7
GENERAL RELEASE SPECIFICATION
R
W
R
W
Pull-up Enable
R
PUER
W
Keyboard Int. Enable
R
KIER
W
Keyboard Int. Flag
R
KIFR
W
Timer 8 Ctrl/Status
R
T8CSR
W
Timer 8 Counter
R
T8CNTR
W
DAC Ctrl and Data
R
DACDR
W
T8IF
0
T8IFR
T8IE
T8CNT7 T8CNT6 T8CNT5 T8CNT4 T8CNT3 T8CNT2 T8CNT1 T8CNT0
DACEN
DA5
DA4
DA3
DA2
DA1
DA0
Figure 2-3. I/O Registers $0000-$000F
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ADDR
$0010
RESERVED
$0011
RESERVED
$0012
$0013
$0014
Freescale Semiconductor, Inc...
REGISTER
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
ACCESS
BIT 4
BIT 3
ICIE
OCIE
TOIE
ICF
OCF
TOF
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRL7
ICRL6
ICRL5
ICRL4
OCRH7
OCRH6
OCRH5
OCRL7
OCRL6
TMRH7
BIT 2
BIT 1
BIT 0
IEDG
OLVL
ICRH2
ICRH1
ICRH0
ICRL3
ICRL2
ICRL1
ICRL0
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
IRQEN
IRQS
LED
COPON
POR
SYSDIV1
SYSDIV2
OSCF
RCF
W
TCR
Timer Status
R
TSR
W
Input Capture High
R
ICRH
W
Input Capture Low
R
ICRL
W
Output Compare High
R
OCRH
W
Output Compare Low
R
OCRL
W
Timer Counter High
R
TMRH
W
Timer Counter Low
R
TMRL
W
Alt. Counter High
R
ACRH
W
Alt. Counter Low
R
ACRL
W
Misc. Control/Status
R
MICSR
W
System Clock Control
R
SYSCR
W
RESERVED
BIT 5
R
R
$001F
BIT 6
W
W
RESERVED
BIT 7
R
Timer Control
$001E
April 30, 1998
TCMPEN TCAPEN
CKSEL1 CKSEL2 FMODE
CKOSC
R
W
R
W
Figure 2-4. I/O Registers $0010-$001F
2-4
MEMORY
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GENERAL RELEASE SPECIFICATION
SECTION 3
CENTRAL PROCESSING UNIT
Freescale Semiconductor, Inc...
The MC68HC05PL4 has an 8k-bytes memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1
REGISTERS
The MCU contains v e registers which are hard-wired within the CPU and are not
part of the memory map. These ve registers are shown in Figure 3-1 and are
described in the following paragraphs.
7
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
1
6
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
PC
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1. MC68HC05 Programming Model
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ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
or non-arithmetic operations. The accumulator is not affected by a reset of the
device.
3.3
INDEX REGISTER (X)
Freescale Semiconductor, Inc...
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU nds the oper and address by adding the
index register content to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU nds the operand address by adding the index register
content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary
storage. The index register is not affected by a reset of the device.
3.4
STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with
memory space less than 64k-bytes the unimplemented upper address lines are
ignored. The stack pointer contains the address of the next free location on the
stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to $00FF. The stack pointer is then decremented as data is pushed onto the
stack and incremented as data is pulled off the stack.
When accessing memory, the ten most signi cant bits are permanently set to
0000000011. The six least signi cant register bits are appended to these ten x ed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the
stack pointer wraps around and overwrites the previously stored information. A
subroutine call occupies two locations on the stack and an interrupt uses ve
locations.
3.5
PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices
with memory space less than 64k-bytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
3-2
CENTRAL PROCESSING UNIT
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Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
Freescale Semiconductor, Inc...
3.6
CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fth bit is the interrupt
mask. These bits can be individually tested by a program, and speci c actions can
be taken as a result of their states. The condition code register should be thought
of as having three additional upper bits that are always ones. Only the interrupt
mask is affected by a reset of the device. The following paragraphs explain the
functions of the lower v e bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested ag b y assigning the
ag to bit 7 of a register or memor y location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the ag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
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3.6.5 Carry/Borrow Bit (C-Bit)
Freescale Semiconductor, Inc...
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
3-4
CENTRAL PROCESSING UNIT
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SECTION 4
INTERRUPTS
Freescale Semiconductor, Inc...
The CPU can be interrupted by ve different sources – one software and four
hardware:
4.1
•
Non-maskable Software Interrupt Instruction (SWI)
•
External Asynchronous Interrupt (IRQ)
•
16-Bit Timer
•
8-Bit Timer
•
Keyboard Interrupt
INTERRUPT VECTORS
Table 4-1 summarizes the reset and interrupt sources and vector assignments
Table 4-1. Vector Address for Interrupts and Reset
Function
Reset
Source
Local
Mask
Power-On Logic
None
Global
Mask
Priority
(1=Highest)
Vector
Address
None
1
$1FFE-$1FFF
RESET Pin
None
COP Watchdog
COPON1
SWI
User Code
None
None
Same Priority
As Instruction
$1FFC-$1FFD
External IRQ
IRQ Pin
IRQEN
I Bit
2
$1FFA-$1FFB
ICF Bit
ICIE
TCF Bit
TCIE
I Bit
3
$1FF8-$1FF9
OCF Bit
OCIE
T8IF Bit
T8IE
I Bit
4
$1FF6-$1FF7
KIF3 Bit
KIE3
KIF2 Bit
KIE2
KIF1 Bit
KIE1
I Bit
5
$1FF4-$1FF5
KIF0 Bit
KIE0
Reserved
—
—
—
—
$1FF2-$1FF3
Reserved
—
—
—
—
$1FF0-$1FF1
16-Bit Timer
8-Bit Timer
Keyboard
NOTES:
1. COPON enables/disables the COP watchdog timer.
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NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt rst. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
Freescale Semiconductor, Inc...
The CPU does the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in
Figure 4-1
•
Sets the I bit in the condition code register to prevent further interrupts
•
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt is shown in the o w chart in Figure 4-2
$0020
$0021
$00BE
$00BF
$00C0
$00C1
$00C2
n
n+1
n+2
n+3
n+4
$00FD
$00FE
$00FF
(Bottom of RAM)
(Bottom of Stack)
Condition Code Register
Accumulator
Index Register
Program Counter (High Byte)
Program Counter (Low Byte)
5
4
3
2
1
⇑
Stacking
Order
Unstacking
Order
⇓
1
2
3
4
5
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
4-2
INTERRUPTS
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FROM
RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
Freescale Semiconductor, Inc...
NO
16-BIT TIMER
INTERRUPT?
YES
NO
8-BIT TIMER
INTERRUPT?
YES
NO
KEYBOARD
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL.
NO
EXECUTE INSTRUCTION.
Figure 4-2. Interrupt Flowchart
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April 30, 1998
SOFTWARE INTERRUPT
The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.4
EXTERNAL INTERRUPT
The LED/IRQ pin is the source that generates external interrupt. Setting the I bit in
the condition code register or clearing the IRQEN bit in the miscellaneous control/
status register disables this external interrupt.
4.4.1 LED/IRQ Pin
Freescale Semiconductor, Inc...
This pin is an open drain pin and setting the IRQEN bit in Miscellaneous Control/
Status Register (MICSR) will set this pin for external interrupt input pin.
An interrupt signal on the LED/IRQ pin latches an external interrupt request. To
help clean up slow edges, the input from the LED/IRQ pin is processed by a
Schmitt trigger gate. When the CPU completes its current instruction, it tests the
IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQEN bit in the MICSR. If the I bit is clear and the IRQEN bit is
set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt request can
be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request.
Figure 4-3 shows the logic for external interrupts.
The LED/IRQ pin can be negative edge-triggered only or negative edge- and lowlevel-triggered. External interrupt sensitivity is programmed with the IRQS bit.
With the edge- and level-sensitive trigger option, a falling edge or a low level on
the LED/IRQ pin latches an external interrupt request. The edge- and level-sensitive trigger option allows connection to the LED/IRQ pin of multiple wired-OR
interrupt sources. As long as any source is holding the LED/IRQ low, an external
interrupt request is present, and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the LED/IRQ pin
latches an external interrupt request. A subsequent interrupt request can be
latched only after the voltage level on the LED/IRQ pin returns to a logic one and
then falls again to logic zero.
NOTE
To use the external interrupt function to exit from WAIT or STOP, it must be
enabled prior entering either of the power saving modes.
4-4
INTERRUPTS
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Edge and Level Sensitive
Power On Reset
External Reset
External Interrupt
Being Serviced
(Read of Vectors)
VDD
IRQS
D
R
Freescale Semiconductor, Inc...
INTERRUPT
Q
LED/IRQ
D
PH2
BIH,BIL instruction
Q
LED IRQEN
Figure 4-3. External Interrupt Logic
4.4.2 Miscellaneous Control and Status Register
MICSR
R
$001C
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
IRQEN
IRQS
TCMPEN
TCAPEN
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
LED
COPON
POR
0
0
0
0
Figure 4-4. Miscellaneous Control and Status Register (MICSR)
IRQEN — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset clears the IRQEN bit.
0 = External interrupt processing disabled. LED/IRQ pin return to
normal LED function
1 = External interrupt processing enabled. LED/IRQ pin set to IRQ
function
IRQS— External Interrupt Sensitivity
This bit makes the external interrupt inputs level-triggered as well as edge-triggered.
0 = IRQ negative edge-triggered and low level-triggered.
1 = IRQ negative edge-triggered only.
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16-BIT TIMER INTERRUPTS
The 16-bit programmable Timer can generate an interrupt whenever the following
events occur:
•
Input capture
•
Output compare
•
Timer counter over o w
Freescale Semiconductor, Inc...
Setting the I bit in the condition code register disables Timer interrupts. The controls for these interrupts are in the Timer control register (TCR) located at $0012
and in the status bits are in the Timer status register (TSR) located at $0013.
The 16-bit programmable Timer interrupts can wake up MCU from WAIT Mode.
4.5.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture ag (ICF) becomes set while
the input capture interrupt enable bit (ICIE) is also set. The ICF ag bit is in the
TSR; and the ICIE enable bit is located in the MICSR. The ICF ag bit is cleared
by a read of the TSR with the ICF ag bit is set; and then followed by a read of the
LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset.
4.5.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare ag (OCF) becomes set
while the output compare interrupt enable bit (OCIE) is also set. The OCF ag bit
is in the TSR and the OCIE enable bit is in the MICSR. The OCF ag bit is cleared
by a read of the TSR with the OCF ag bit set; and then followed by an access to
the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.5.3 Timer Overflow Interrupt
A Timer over ow interrupt occurs if the Timer over ow ag (TOF) becomes set
while the Timer over o w interrupt enable bit (TOIE) is also set. The TOF ag bit is
in the TSR and the TOIE enable bit is in the TCR. The TOF ag bit is cleared b y a
read of the TSR with the TOF ag bit set; and then followed by an access to the
LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected
by reset.
4.6
8-BIT TIMER INTERRUPT
The 8-bit Timer can generate an interrupt when the Timer8 Counter Register
(T8CNTR) decrements from preset value to zero and the interrupt enable bit is
set. Setting the I bit in the condition code register disables this Timer interrupts.
The control bit for this interrupt and status bit are in the Timer 8 control register
(T8CSR) located at $000D.
The 8-Bit timer interrupt can wake up MCU from WAIT Mode.
4-6
INTERRUPTS
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4.7
GENERAL RELEASE SPECIFICATION
KEYBOARD INTERRUPT
Port B has internal pull-up resistors (typically 100KΩ) and are enabled individually
by setting the corresponding bit in the Pull-Up Enable Register (PUER).
PUER
R
$000A
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PUL7
PUL6
PUL5
PUL4
PUL3
PUL2
PUL1
PUL0
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
Figure 4-5. Pull-Up Enable Register (PUER)
PB0 to PB3 have keyboard interrupt functions, with individual enable and ag bits
in registers $000B and $000C.
A falling edge on any one of the keyboard interrupt pins sets the corresponding
KIF ag in the Keyboard Interrupt Flag Register (KIFR) located at $000C. If the
associated KIE bit in the Keyboard Interrupt Enable Register (KIER) located at
$000B is also set, a keyboard interrupt is generated to the processor.
BIT 7
KIER
R
$000B
W
RESET
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
KIE3
KIE2
KIE1
KIE0
0
0
0
0
Figure 4-6. Keyboard Interrupt Enable Register (KIER)
BIT 7
KIFR
R
$000C
W
RESET
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
KIF3
KIF2
KIF1
KIF0
0
0
0
0
Figure 4-7. Keyboard Interrupt Flag Register (KIFR)
KIFx can be cleared by writing “1” to the bit. Resets clear both KIFR and KIER.
Keyboard Interrupt can wake up the MCU from WAIT mode or STOP mode.
NOTE
Since the Keyboard Interrupt function is associated with PB0-PB3, any falling
edge on these pins sets the corresponding KIF ag in the K eyboard Interrupt Flag
Register. Therefore, PB0-PB3 should be connected to internal or external pullups, and KIFR cleared before these port pins switch from I/O to keyboard
application.
To use the keyboard interrupt function to exit from WAIT or STOP, it must be
enabled prior entering either of the power saving modes.
MC68HC05PL4
REV 2.0
INTERRUPTS
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Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
4-8
INTERRUPTS
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MC68HC05PL4
REV 2.0
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April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
•
Initial power-up of device (power-on reset)
•
A logic zero applied to the RESET pin (external reset)
•
Time-out of the COP watchdog (COP reset)
•
Fetch of an opcode from an address not in the memory map
(illegal address reset)
COPON
Freescale Semiconductor, Inc...
This section describes the four reset sources and how they initialize the MCU. A
reset immediately stops the operation of the instruction being executed, initializes
certain control bits, and loads the program counter with a user de ned reset v ector address. The following conditions produce a reset:
COP WATCHDOG
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
D
RESET
LATCH
RESET
RST
TO CPU
AND
SUBSYSTEMS
R
4-CYCLE
COUNTER
INTERNAL
CLOCK
Figure 5-1. Reset Sources
5.1
POWER-ON RESET
A positive transition on the VDD pin generates a power on reset. The power-on
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
MC68HC05PL4
REV 2.0
RESETS
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GENERAL RELEASE SPECIFICATION
April 30, 1998
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If the RESET pin is at logic zero at the end of the
multiple tCYC time, the MCU remains in the reset condition until the signal on the
RESET pin goes to a logic one.
MICSR
R
$001C
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
IRQEN
IRQS
TCMPEN
TCAPEN
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
LED
COPON
POR
0
0
0
0
Freescale Semiconductor, Inc...
Figure 5-2. Miscellaneous Control and Status Register (MICSR)
POR - Power on Reset Flag
The POR bit is set each time the device is powered on. It allows the user to
make a software distinction between a power-on and an external reset. POR
can be cleared by software by writing a ‘0’ to the bit. It cannot be set by software.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5tCYC generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. The external
reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripherals.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3-4 cycles of the
internal clock, fOP, or as long as the internal reset source is asserted. When the
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some power
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3-4 internal clock cycles, whichever is longer.
5-2
RESETS
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GENERAL RELEASE SPECIFICATION
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles after the oscillator becomes
active.
Freescale Semiconductor, Inc...
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 4096 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop
below VPOR in order for the internal POR circuit to detect the next rise of VDD.
5.3.2 Computer Operating Properly (COP) Reset
The COP watchdog system consist of a divide by 8 counter with clock source from
the 8-bit Timer (Timer8). Hence, a COP watchdog time-out occurs on the 8th
Timer8 clock pulse. A COP watchdog time-out generates a COP reset to the CPU.
Figure 5-3 shows a block diagram of the COP watchdog logic.
From Timer8 Counter
S
÷ 8 Counter
COPON
To Reset Logic
R
R
Logic
Write “1” to COPC
COP Reset
Latch
From Reset Logic
Figure 5-3. COP Watchdog Block Diagram
The COP watchdog is part of a software error detection system and must be
cleared periodically to start a new time-out period. To clear the COP watchdog
and prevent a COP reset, write a logic “1” to the COPC bit in the COP register at
location $1FF0. The COP register, shown in Figure 5-4, is a write-only register
that returns the content of a ROM location when read.
COPR
R
$1FF0
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
U
U
U
U
U
U
U
BIT 0
COPC
U
Figure 5-4. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic one to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = Reset COP watchdog timer.
0 = No effect on COP watchdog timer.
MC68HC05PL4
REV 2.0
RESETS
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GENERAL RELEASE SPECIFICATION
April 30, 1998
Use the following formula to calculate the COP time-out period:
COP Time-out Period = (prescaler x 256 x 8) ÷ fBUS
where prescaler is the Timer8 prescaler value
The clock input to the watchdog system is derived from the output of the Timer8,
therefore a reset or preset of Timer8 may affect the COP watchdog time-out
period.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for 3-4 cycles of the internal bus clock.
Freescale Semiconductor, Inc...
The COP reset can be enable or disable by the COPON bit in MISCR. The MISCR
is in Figure 5-5.
MICSR
R
$001C
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
IRQEN
IRQS
TCMPEN
TCAPEN
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
LED
COPON
POR
0
0
0
0
Figure 5-5. Miscellaneous Control and Status Register (MICSR)
COPON — COP On
Since the COP Watchdog system is derived from the 8-bit Timer system, the
T8EN bit in the Timer8 Control and Status register (bit3 of $0D) must be set for
COPON bit to have any affect.
COPON can be set to enable the COP watchdog system. Once set, the watchdog system cannot be disabled other than by a power-on reset or external
reset. After a reset the COPON bit is cleared and the COP watchdog system is
disabled.
1 = COP Watchdog enabled.
0 = COP Watchdog disabled.
NOTE
The COP Watchdog system is not designed to operate in STOP mode, therefore it
should be disabled before entering STOP mode by clearing the COPON bit.
Entering STOP mode with COP watchdog enabled will cause an internal reset of
the MCU.
5.3.3 Illegal Address Reset
An opcode fetch from an address that is not in the ROM (locations $0E00–$1DFF
and $1FF0-$1FFF) or the RAM (locations $0020–$011F) generates an illegal
address reset. The illegal address reset will assert the pulldown device to pull the
RESET pin low for 3-4 cycles of the internal bus clock.
5-4
RESETS
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April 30, 1998
5.4
GENERAL RELEASE SPECIFICATION
RESET STATES OF SUBSYSTEM IN MCU
The following paragraphs describe how a reset initializes various sub-systems.
5.4.1 CPU
Freescale Semiconductor, Inc...
A reset has the following effects on the CPU:
•
Loads the stack pointer with $FF.
•
Sets the I bit in the condition code register, inhibiting interrupts.
•
Loads the program counter with the user de ned reset vector from
locations $1FFE and $1FFF.
•
Clears the stop latch, enabling the CPU clock.
•
Clears the wait latch, bringing the CPU out of the wait mode.
5.4.2 I/O Registers
A reset has the following effects on I/O registers:
•
Clears bits in data direction registers con gur ing pins as inputs:
– DDRA6–DDRA0 in DDRA for port A.
– DDRB7–DDRB0 in DDRB for port B.
– DDRC7–DDRC0 in DDRC for port C.
•
Has no effect on port A, B, C data registers.
5.4.3 8-Bit Timer
A reset has the following effects on the 8-Bit Timer:
•
Timer 8 system disabled (T8EN bit cleared)
•
Timer 8 interrupt request disabled
•
Timer 8 Pre-scalar preset to divide the internal bus clock by ratio 16
•
Timer 8 Counter register preset to $FF
Therefore disables the timer 8 interrupt and preset the counter for POR cycle
delay.
5.4.4 16-Bit Programmable Timer
A reset has the following effects on the 16-bit programmable Timer:
•
Initializes the timer counter registers (TMRH, TMRL) to a value of
$FFFC.
•
Initializes the alternate timer counter registers (ACRH, ACRL) to a value
of $FFFC.
•
Clears all the interrupt enables and the output level bit (OLVL) in the
timer control register (TCR).
MC68HC05PL4
REV 2.0
RESETS
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GENERAL RELEASE SPECIFICATION
April 30, 1998
•
Does not affect the input capture edge bit (IEDG) in the TCR.
•
Does not affect the interrupt ags in the timer status register (TSR).
•
Does not affect the input capture registers (ICRH, ICRL).
•
Does not affect the output compare registers (OCRH, OCRL).
Therefore con gure the por t A pins PA2,PA3 as general I/O function. However the
timer is free running for interrupt process.
5.4.5 Keyboard Interrupt Interface
Freescale Semiconductor, Inc...
A reset has the following effects on the Keyboard Interrupt interface:
•
Clears all bits in Keyboard interrupt enable register (KIER) and
Keyboard interrupt disable
•
Clears all bits in Keyboard interrupt ag register (KIFR)
•
Clears all bits in Pull-Up enable register (PUER)
Therefore disables the Keyboard interrupt and leaves the shared port B pins as
general I/O. Any pending interrupt ag is cleared and the K eyboard interrupt is disabled.
5.4.6 6-bit DAC Subsystem
A reset has the following effects on the DAC subsystem:
•
Clears all bits in DAC control Register, hence DAC subsystem is
disabled.
Therefore con gure the por t A pin PA1 as general I/O function.
5.4.7 System Clock Option Subsystem
At reset has the following effects on OSC clock subsystem
•
The internal RC is enabled and oscillating at around 500kHz
•
Internal clock divider selected to divide by 2 for bus frequency
5.4.8 Miscellaneous Subsystem
A P reset has the following effects on IRQ subsystem
•
IRQ is disabled and reset the IRQ selection as negative edge-triggered
and low level-triggered, hence the LED/IRQ pin function as LED output
pin
Therefore also disable the LED driver output, hence the LED/IRQ pin is in high
impedance state.
5-6
RESETS
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REV 2.0
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April 30, 1998
5.5
GENERAL RELEASE SPECIFICATION
RESET CHARACTERISTICS
Table 5-1. Reset Characteristics
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Typ
Max
Unit
POR Recovery Voltage2
VPOR
0
—
100
mV
POR VDD Slew Rate2
Rising2
Falling2
SVDDR
SVDDF
—
—
—
—
0.1
0.05
V/ms
V/ms
RESET Pulse Width (when bus clock active)
tRL
1.5
—
—
tCYC
RESET Pulldown Pulse Width (from internal reset)
tRPD
3
—
4
tCYC
Note:
1.
2.
+2.0 ≤ VDD ≤ +4.0 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
By design, not tested.
OSC11
tRL
RESET
4096
Internal
Clock3
Internal
Address
Bus3
1FFE
Internal
Data
Bus3
NOTES:
1.
2.
3.
NEW
PCH
1FFF
NEW PCH NEW PCL
NEW
PCL
Op
code
Represents the internal gating of the OSC1 pin
Normal delay of 4064 tCYC
Internal timing signal and data information not available externally.
Figure 5-6. Stop Recovery Timing Diagram
MC68HC05PL4
REV 2.0
RESETS
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GENERAL RELEASE SPECIFICATION
April 30, 1998
Internal
Reset1
RESET
Pin
tRPD
4096
Freescale Semiconductor, Inc...
Internal
Clock3
Internal
Address
Bus3
1FFE
Internal
Data
Bus3
NOTES:
1.
2.
3.
1FFF
NEW
PCH
NEW PCH NEW PCL
NEW
PCL
Represents the internal reset from low voltage reset, illegal opcode fetch or COP Watchdog timeout.
Normal delay of 4064 tCYC
Internal timing signal and data information not available externally.
Figure 5-7. Internal Reset Timing Diagram
5-8
RESETS
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 6
OPERATING MODES
This section describes the various operating modes of the MC68HC05PL4.
Freescale Semiconductor, Inc...
6.1
OPERATING MODES
The MC68HC05PL4 has two operating modes: Single-Chip (Normal) Mode and
Self-Check Mode.
At the rising edge of the RESET, the device latches the states of LED/IRQ and
PB0/KBI0 pins and places itself in the speci ed mode . RESET must be held low
for the prede ned po wer-on reset cycles of the internal PH2 clock after POR, or
for a time tRL for any other reset.
The conditions required to enter each mode are shown in Table 6-1. The mode of
operation is determined by the voltages on the LED/IRQ and PB0/KBI0 pins on
the rising edge of the external RESET pin.
Table 6-1. Operation Mode Condition After Reset
RESET Pin
LED/IRQ
PB0/KBI0
MODE
VSS to VDD
VSS to VDD
Single-Chip (Normal)
VTST
VDD
Self-Check
VTST = 2 x VDD
6.1.1 Single-chip (Normal) Mode
The Single-Chip Mode is the normal operating mode, and it allows the device to
function as a self-contained microcontroller, with maximum use of the pins for onchip peripheral functions.
In the Single-Chip Mode all address and data activity occurs within the MCU and
is not available externally. Single-Chip Mode is entered if the LED/IRQ pin is within
the normal operating voltage range when the rising edge of a RESET occurs. In
Single-Chip Mode, all I/O port pins are available.
6.1.2 Self-check Mode
The self-check program is mask at location $1E00 to $1FEF, and is used for
checking device functionality under minimum hardware support.
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REV 2.0
OPERATING MODES
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6.2
April 30, 1998
LOW POWER MODES
In each of its con gur ation modes the MC68HC05PL4 is capable of running in one
of two low-power operating modes. The WAIT and STOP instructions provide two
modes that reduce the power required for the MCU by stopping various internal
clocks and/or the oscillator. The o w of the STOP, and WAIT modes are shown in
Figure 6-1.
6.2.1 STOP Mode
Freescale Semiconductor, Inc...
Execution of the STOP instruction places the MCU in its lowest power
consumption mode.
The MCU can exit from the STOP by an IRQ or Keyboard interrupt (KBIx), or an
externally generated RESET. When exiting the STOP mode the internal oscillator
will resume after 4064 internal processor clock cycles oscillator stabilization delay.
6.2.2 WAIT Mode
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode.
The WAIT mode may be exited by an external IRQ, a keyboard interrupt, 16-bit
timer interrupt, 8-bit timer interrupt, or by an external RESET.
6-2
OPERATING MODES
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GENERAL RELEASE SPECIFICATION
STOP
WAIT
External Oscillator Active
and
Internal Timer Clock Active
Freescale Semiconductor, Inc...
Stop External Oscillator,
Stop Internal Timer Clock,
Reset Start-up Delay
Stop Internal Processor Clock,
Clear I-Bit in CCR,
and set IRQEN in MICSR
Stop Internal Processor Clock,
Clear I-Bit in CCR,
and set IRQEN in MICSR
External
RESET?
Y
Y
N
N
IRQ
External
Interrupt?
Y
Y
N
IRQ
External
Interrupt?
N
N
Keyboard
Interrupt?
External
RESET?
Y
Y
Restart External Oscillator,
start Stabilization Delay
End
of Stabilization
Delay?
N
16-bit
Timer
Interrupt?
N
Y
8-bit
Timer
Interrupt?
N
Y
Y
Restart
Internal Processor Clock
Keyboard
Interrupt?
N
1. Fetch Reset Vector
or
2. Service Interrupt
a. Stack
b. Set I-Bit
c. Vector to Interrupt Routine
Figure 6-1. STOP/WAIT Flowchart
MC68HC05PL4
REV 2.0
OPERATING MODES
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GENERAL RELEASE SPECIFICATION
6-4
OPERATING MODES
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 7
INPUT/OUTPUT PORTS
In the MC68HC05PL4, 23 bidirectional I/O lines are available, arranged as one
7-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C).
In the MC68HC05PL4B, 22 bidirectional I/O lines are available, arranged as one
6-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C).
NOTE
To avoid generating a glitch on an I/O port pin, data should be written to the I/O
port data register before writing a “1” (for output) to the corresponding data
direction register.
7.1
PARALLEL PORTS
Port A, B, and C are bidirectional ports. Each port pin is controlled by the
corresponding bits in a data direction register and a data register as shown in
Figure 7-1. The functions of the I/O pins are summarized in Table 7-1.
Read/Write DDR
Internal Data Bus
Freescale Semiconductor, Inc...
This section describes the general purpose I/O ports on the MC68HC05PL4 and
MC68HC05PL4B MCUs.
Write Data
Data Direction
Register Bit
Data
Register Bit
OUTPUT
I/O PIN
Read Data
RESET
(RST)
Figure 7-1. Port Input/Output Circuitry
MC68HC05PL4
REV 2.0
INPUT/OUTPUT PORTS
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Table 7-1. I/O Pin Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
Freescale Semiconductor, Inc...
7.1.1 Port Data Registers
Each port I/O pin has a corresponding bit in the Port Data Register. When a port
I/O pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin.
When a port pin is programmed as an input, any read of the Port Data Register
will return the logic state of the corresponding I/O pin. The locations of the Data
Registers for Port A, B, and C are at $0000, $0001 and $0002. The Port Data
Registers are unaffected by reset.
7.1.2 Port Data Direction Registers
Each port I/O pin may be programmed as an input by clearing the corresponding
bit in the DDR, or programmed as an output by setting the corresponding bit in the
DDR. The DDR for Port A, B, and C are located at $0005, $0006 and $0007. The
DDRs are cleared by reset.
NOTE
A “glitch” can be generated on an I/O pin when changing it from an input to an
output unless the data register is rst preconditioned to the desired state bef ore
changing the corresponding DDR bit from a zero to a one.
7.2
PORT A
Port A is an 7-bit bidirectional port, with pins shared with other modules. The
Port A Data Register is at address $0000 and the Data Direction Register is at
address $0005. Port pins PA5 and PA6 are high current sink pins; see Electrical
Speci cations section f or values.
Pin PA0 is only available on MC68HC05PL4. OSC2 replaces PA0 on
MC68HC05PL4B.
Pin PA1 becomes the DTMF output from the DAC when the DACEN bit is set in
the DAC Control and Data Register ($000F).
Pins PA2 and PA3 become the 16-bit timer TCAP and TCMP respectively, when
TCAPEN and TCMPEN are set in the Miscellaneous Control/Status Register
($001C).
7-2
INPUT/OUTPUT PORTS
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7.3
GENERAL RELEASE SPECIFICATION
PORT B
Port B is an 8-bit bidirectional port, with pins PB0-PB3 shared with keyboard interrupt functions. The Port B Data Register is at address $0001 and the Data Direction Register is at address $0006.
Pins PB0 to PB3 keyboard interrupt functions have individual enable and ag bits
in registers $000B and $000C.
7.4
PORT C
Freescale Semiconductor, Inc...
Port C is an 8-bit bidirectional port. The Port C Data Register is at address $0002
and the Data Direction Register is at address $0007. Port pins PC0 to PC3 are
high current sink pins; see Electrical Speci cations section f or values.
7.5
SUMMARY OF PORT A AND PORT B SHARED PINS
Table 7-2 below shows a summary of port pins shared with other on-chip modules.
Table 7-2. Port A and Port B Shared Pins
Port
Port A
Port B
Port Pin
Control
Pin Name
Shared Functions
PA0
—
PA0 or OSC2
PA0 on MC68HC05PL4
OSC2 on MC68HC05PL4B
PA1
DACEN
PA1/DTMF
DAC DTMF Output
PA2
TCAPEN
PA2/TCAP
16-bit Timer Input Capture
PA3
TCMPEN
PA3/TCMP
16-bit Timer Output Compare
PB3-PB0
KBIE3-KBIE0
PUL3-PUL0
PB3/KBI3-PB0/KBI0
Keyboard Interrupt
MC68HC05PL4
REV 2.0
INPUT/OUTPUT PORTS
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Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
7-4
INPUT/OUTPUT PORTS
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 8
SYSTEM CLOCKS
This section describes the system clock options for the MC68HC05PL4.
Freescale Semiconductor, Inc...
8.1
SYSTEM CLOCK SOURCE AND FREQUENCY OPTION
The operating bus frequency of the MCU is dependent on the clock source (OSC1
or internal RC) and the clock divider ratio. These are selected in the System Clock
Control Register (SYSCR).
BIT 7
SYSCR
R
$001D
W
BIT 6
SYSDIV1 SYSDIV2
POR
0
0
BIT 5
BIT 4
BIT 3
CKSEL1
CKSEL2
FMODE
1
0
1
BIT 2
BIT 1
OSCF
RCF
0
1
BIT 0
CKOSC
0
Figure 8-1. System Clock Control Register (SYSCR)
SYSDIV1,SYSDIV2 — System Clock Divider Select
The SYSDIV1 and SYSDIV2 bits select the divide ratio for the clock source.
After power-on-reset, the default setting is divide by 2. Table 8-1 shows the
divide ratios.
Table 8-1. System Clock Divider Select
SYSDIV1
SYSDIV2
DIV
0
0
2
0
1
4
1
0
8
1
1
16
CKSEL1,CKSEL2 — System Clock Source Select
The CKSEL1 and CKSEL2 bits select the system clock source for the MCU. After
power-on-reset, the default setting is internal RC. Table 8-2 shows the system
clock source options.
Table 8-2. System Clock Source Select
MC68HC05PL4
REV 2.0
CKSEL1
CKSEL2
Select Option
0
0
External from OSC1
0
1
External from OSC1
1
0
Internal RC
1
1
External from OSC1 (with RC enabled)
SYSTEM CLOCKS
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Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
FMODE — Fast Mode RC select
FMODE selects the oscillating frequency of the internal RC. After power-onreset, the default setting is 500kHz.
1 = Internal RC oscillates at 500kHz
0 = Internal RC oscillates at 20kHz
OSCF — OSC running Flag
This bit is set when the external clock (External/crystal) from OSC1 is on.
See also CKOSC bit below.
Freescale Semiconductor, Inc...
RCF — RC Running Flag
This bit is set when the internal RC clock is on.
CKOSC — ChecK OSC
The CKOSC bit enables the internal logic for external clock selection. The procedure below should be followed when switching from RC to external clock.
1. Set the CKSEL1 and CKSEL2 bits for external clock source.
2. If crystal option is used — set the 8-bit timer for counting crystal
stabilization delay (typically 4064 clock cycles).
3. Write a “1” to the CKOSC bit and check for OSCF bit set.
4. If the OSCF bit is not set, no external clock is available, the internal RC
clock will be used as the system clock, irrespective of the setting for
CKSEL1 and CKSEL2.
8-2
SYSTEM CLOCKS
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 9
16-BIT PROGRAMMABLE TIMER
Freescale Semiconductor, Inc...
The MC68HC05PL4 MCU contains a 16-bit programmable Timer with an Input
Capture function and an Output Compare function as shown by the block diagram
in Figure 9-1.
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
TMRH ($0018)
TMRL ($0019)
IEDG
ICF
PA2
TCAP
ACRH ($001A) ACRL ($001B)
16-BIT COUNTER
÷4
OVERFLOW (TOF)
16-BIT COMPARATOR
D Q
OCRL ($0017)
PA3
TCMP
OLVL
C
OCF
OCRH ($0016)
INTERNAL
CLOCK
(XTAL ÷ 2)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TOF
OCF
ICF
OLVL
IEDG
TOIE
OCIE
ICIE
RESET
TIMER STATUS REGISTER
$0013
INTERNAL DATA BUS
Figure 9-1. Programmable Timer Block Diagram
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
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GENERAL RELEASE SPECIFICATION
April 30, 1998
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a speci c timer function allo ws full control of that function; however, an access of the
high byte inhibits that speci c timer function until the lo w byte is also accessed.
Because the counter is 16 bits long and preceded by a x ed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4 MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt ags can be read from the timer status register (TSR) located at
$0013.
9.1
TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 9-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
LATCH
READ
TMRH
READ
RESET
($FFFC)
READ
TMRL
TMRL ($0019)
TMRH ($0018)
TMR LSB
÷4
16-BIT COUNTER
OVERFLOW (TOF)
INTERNAL
CLOCK
(XTAL ÷2)
TIMER
INTERRUPT
REQUEST
TOF
TOIE
Freescale Semiconductor, Inc...
The basis of the capture/compare Timer is a 16-bit free-running counter which
increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and
output compare functions provide a means to latch the times at which external
events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at
any time without affect the counter sequence.
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-2. Timer Counter and Register Block Diagram
9-2
16-BIT PROGRAMMABLE TIMER
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REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
Freescale Semiconductor, Inc...
The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations
which contain the current high and low bytes of the 16-bit free-running counter.
Writing to the timer registers has no effect. Reset of the device presets the timer
counter to $FFFC.
BIT 7
TMRH
R TMRH7
$0018
W
reset:
1
BIT 6
TMRH6
BIT 5
TMRH5
BIT 4
TMRH4
BIT 3
TMRH3
BIT 2
TMRH2
BIT 1
TMRH1
BIT 0
TMRH0
1
1
1
1
1
1
1
TMRL
R TMRL7
$0019
W
reset:
1
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
0
0
Figure 9-3. Programmable Timer Registers (TMRH, TMRL)
The TMRL latch is a transparent read of the LSB until the a read of the TMRH
takes place. A read of the TMRH latches the LSB into the TMRL location until the
TMRL is again read. The latched value remains x ed even if multiple reads of the
TMRH take place before the next read of the TMRL. Therefore, when reading the
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a xed divide-by-four prescaler, the value in the counter repeats
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer over o w
ag bit (T OF) is set in the TSR. When the TOF is set, it can generate an interrupt if
the timer over o w interrupt enable bit (TOIE) is also set in the TCR. The TOF ag
bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF ags , reading the TMRH and TMRL in any
order or any number of times does not have any effect on the 16-bit free-running
counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and TMRL,
set the I bit in the condition code register (CCR) before reading TMRH and clear
the I bit after reading TMRL.
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
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GENERAL RELEASE SPECIFICATION
9.2
April 30, 1998
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF ag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
Freescale Semiconductor, Inc...
LATCH
READ
ACRH
READ
RESET
($FFFC)
READ
ACRL
ACRL ($001B)
TMR LSB
ACRH ($001A)
INTERNAL
CLOCK
(XTAL ÷ 2)
÷4
16-BIT COUNTER
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
BIT 7
ACRH
R ACRH7
$001A
W
reset:
1
BIT 6
ACRH6
BIT 5
ACRH5
BIT 4
ACRH4
BIT 3
ACRH3
BIT 2
ACRH2
BIT 1
ACRH1
BIT 0
ACRH0
1
1
1
1
1
1
1
ACRL
R ACRL7
$001B
W
reset:
1
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
0
0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains x ed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a xed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF ag bit.
9-4
16-BIT PROGRAMMABLE TIMER
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REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
INPUT CAPTURE REGISTERS
The input capture function is a technique whereby an external signal (connected
to PA2/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possible to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
When the input capture circuitry detects an active edge on the selected source, it
latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal.
INTERNAL
DATA
BUS
READ
ICRH
ICRH ($0014)
16-BIT COUNTER
READ
ICRL
÷4
INPUT CAPTURE (ICF)
TIMER CONTROL REG.
RESET
ICRL ($0015)
INTERNAL
CLOCK
(XTAL ÷ 2)
TIMER
INTERRUPT
REQUEST
ICF
LATCH
IEDG
IEDG
TCAP
($FFFC)
EDGE
SELECT
& DETECT
LOGIC
ICIE
Freescale Semiconductor, Inc...
9.3
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-6. Timer Input Capture Block Diagram
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt
trigger to improve noise immunity. The edge that triggers the counter transfer is
de ned b y the input edge bit (IEDG) in the TCR. Reset does not affect the contents of the input capture registers.
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
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Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
Freescale Semiconductor, Inc...
ICRH
R
$0014
W
reset:
BIT 7
ICRH7
BIT 6
ICRH6
BIT 5
ICRH5
BIT 4
ICRH4
BIT 3
ICRH3
BIT 2
ICRH2
BIT 1
ICRH1
BIT 0
ICRH0
U
U
U
U
U
U
U
U
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
U
U
U
U
U
U
ICRL
R ICRL7
ICRL6
$0015
W
reset:
U
U
U = UNAFFECTED BY RESET
Figure 9-7. Input Capture Registers (ICRH, ICRL)
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF ag bit. does
not inhibit transfer of the free-running counter. There is no con ict betw een reading the ICRL and transfers from the free-running timer counters. The input capture
registers always contain the free-running timer counter value which corresponds
to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and ICRL, set
the I bit in the condition code register (CCR) before reading ICRH and clear the I
bit after reading ICRL.
9.4
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an output signal when the
16-bit timer counter reaches a selected value as shown in Figure 9-8. Software
writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the timer transfers the output
level (OLVL) from the timer control register (TCR) to the TCMP.
Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of speci c duration or a pulse train of
speci c frequency and duty cycle on the TCMP.
9-6
16-BIT PROGRAMMABLE TIMER
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REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
The planned action on the TCMP depends on the value stored in the OLVL bit in
the TCR, and it occurs when the value of the 16-bit free-running timer counter
matches the value in the output compare registers shown in Figure 9-3. These
registers are read/write bits and are unaffected by reset.
R/W
OCRH
R/W
OCRL
OCRL ($0017)
OCRH ($0016)
EDGE
SELECT
DETECT
LOGIC
OLVL
16-BIT COMPARATOR
($FFFC)
TIMER
INTERRUPT
REQUEST
OCF
OLVL
OUTPUT COMPARE
(OCF)
RESET
TCMP
INTERNAL
CLOCK
(XTAL ÷ 2)
÷4
16-BIT COUNTER
OCIE
Freescale Semiconductor, Inc...
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TCR will clear
the output compare ag bit (OCF). The output compare OLVL state will be clocked
to its output latch regardless of the state of the OCF.
TIMER STATUS REG.
TIMER CONTROL REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-8. Timer Output Compare Block Diagram
OCRH
$0016
reset:
BIT 7
R
OCRH7
W
U
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
U
U
U
U
U
U
U
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
U
U
U
U
U
U
OCRL
R
OCRL7 OCRL6
$0017
W
reset:
U
U
U = UNAFFECTED BY RESET
Figure 9-9. Output Compare Registers (OCRH, OCRL)
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
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GENERAL RELEASE SPECIFICATION
April 30, 1998
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
clears the OCF ag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 9-1.
Freescale Semiconductor, Inc...
Table 9-1. Output Compare Initialization Example
9B
...
...
B7
B6
BF
...
...
9A
9.5
SEI
...
...
STA
LDA
STX
...
...
CLI
16
13
17
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
OCRH
TSR
OCRL
TIMER CONTROL REGISTER (TCR)
The timer control register shown in Figure 9-10 performs the following functions:
•
Enables input capture interrupts.
•
Enables output compare interrupts.
•
Enables timer over o w interrupts.
•
Con gure the I/O P ort Pin PA2 as input pin for TCAP signal
•
Con gure the I/O P ort Pin PA3 as output pin for TCMP signal
•
Control the active edge polarity of the TCAP signal.
•
Controls the active level of the TCMP output.
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
TCR
R
$0012
W
reset:
BIT 7
BIT 6
BIT 5
ICIE
OCIE
TOIE
0
0
0
BIT 4
0
BIT 3
0
BIT 2
0
0
0
0
BIT 1
BIT 0
IEDG
OLVL
U
0
Figure 9-10. Timer Control Register (TCR)
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB1/
TCAP pin or from CPF2 ag bit of the analog subsystem v oltage comparator 2.
Reset clears the ICIE bit.
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
9-8
16-BIT PROGRAMMABLE TIMER
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GENERAL RELEASE SPECIFICATION
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the TCMP
pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
Freescale Semiconductor, Inc...
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer over o w. Reset clears
the TOIE bit.
1 = Timer over o w interrupts enabled.
0 = Timer over o w interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin triggers a transfer of the contents of the timer register to
the input capture register. Resets have no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT
The state of this read/write bit determines whether a logic one or a logic zero
appears on the TCMP when a successful output compare occurs. Resets clear
the OLVL bit.
1 = TCMP goes high on output compare.
0 = TCMP goes low on output compare.
9.5.1 Miscellaneous Control and Status Register for Timer16
The Miscellaneous Control and Status Register shown in Figure 9-11 performs
the following functions:
•
Con gure the I/O por t pin PA2 as input pin for TCAP signal
•
Con gure the I/O por t pin PA3 as output pin for TCMP signal
BIT 7
MICSR
R
IRQEN
$001C
W
reset:
0
BIT 6
IRQS
0
BIT 5
BIT 4
TCMPEN TCAPEN
0
0
BIT 3
0
BIT 2
BIT 1
BIT 0
LED
COPON
POR
0
0
0
1
Figure 9-11. Miscellaneous Control and Status Register (MISCR)
TCAPEN - TIMER INPUT CAPTURE ENABLE
The bit con gures por t pin PA2 for Timer16 input capture function (TCAP). At
power-on-reset, this bit is cleared, PA2 is a standard I/O port pin, TCAP to the
Timer16 is pulled high.
1 = PA2 pin con gured as TCAP for timer input capture
0 = PA2 pin as standard I/O port pin
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GENERAL RELEASE SPECIFICATION
April 30, 1998
TCMPEN - TIMER OUTPUT COMPARE ENABLE
The bit con gures por t pin PA3 for Timer16 output compare function (TCMP).
At power-on-reset, this bit is cleared, PA3 is a standard I/O port pin, TCMP signal to PA3 is disabled from Timer16.
1 = PA3 pin con gured as TCMP for timer output compare
0 = PA3 pin as standard I/O port pin
9.6
TIMER STATUS REGISTER (TSR)
Freescale Semiconductor, Inc...
The timer status register (TSR) shown in Figure 9-12 contains ags f or the following events:
•
An active signal on the PA2/TCAP pin transferring the contents of the
timer registers to the input capture registers.
•
A match between the 16-bit counter and the output compare registers,
transferring the OLVL bit to the TCMP.
•
An over o w of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the ag bits in the TSR.
BIT 7
ICF
BIT 6
OCF
TSR
R
$0013
W
reset:
U
U
U = UNAFFECTED BY RESET
BIT 5
TOF
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
U
0
0
0
0
0
Figure 9-12. Timer Status Registers (TSR)
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PA2/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Resets have no effect on ICF.
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Resets have no effect on OCF.
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Resets have no effect on TOF.
9-10
16-BIT PROGRAMMABLE TIMER
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
9.7
GENERAL RELEASE SPECIFICATION
16-BIT TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the WAIT mode.
9.8
16-BIT TIMER OPERATION DURING STOP MODE
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When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
time the counter resumes from its stopped value as if nothing had happened. If
STOP mode is exited via an external reset (logic low applied to the RESET pin)
the counter is forced to timer interrupt vector.
If a valid input capture edge occurs at the PA2/TCAP pin during the STOP mode
the input capture detect circuitry will be armed. This action does not set any ags
or “wake up” the MCU, but when the MCU does “wake up” there will be an active
input capture ag (and data) from the rst v alid edge. If the STOP mode is exited
by an external reset, no input capture ag or data will be present e ven if a valid
input capture edge was detected during the STOP mode.
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
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9-11
Freescale Semiconductor, Inc.
April 30, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
9-12
16-BIT PROGRAMMABLE TIMER
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 10
8-BIT TIMER
This section describes the 8-bit count down timer module.
OVERVIEW
Freescale Semiconductor, Inc...
10.1
Timer8 Counter Register ($0E)
8
8
8-bit count-down timer counter
To COP
Watchdog
Circuit
7-bit prescaler counter
Internal Bus
Internal
Bus Clock
8
Overflow
Detect
Circuit
Interrupt Circuit
8
T8IF T8IFR T8IE
Prescaler
Select
Logic
(8 to 1 MUX)
T8EN PS2 PS1 PS0
Timer8 Control and Status Register ($0D)
Figure 10-1. Timer8 Block Diagram
As shown in Figure 10-1 this timer contains a single 8-bit software programmable
countdown timer counter with a 3-bit software control prescaler. The counter’s
value may be preset under software control and counts down to zero. When the
counter decrements to zero, the timer8 interrupt request bit (T8IF in T8CR) is set.
Then if the timer interrupt is enabled (T8IE in T8CR is set) and the I-bit of the condition code register are is cleared, the processor receives an interrupt. After completion of the current instruction, the processor proceeds to store the appropriate
registers on the stack and then fetches the timer8 interrupt vector in order to begin
serving the interrupt.
MC68HC05PL4
REV 2.0
8-BIT TIMER
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10-1
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GENERAL RELEASE SPECIFICATION
April 30, 1998
Freescale Semiconductor, Inc...
The counter continues to count after it reaches zero, allowing the software to
determine the number of internal or external clocks since the timer interrupt
request bit (T8IF) was set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter become stable prior to
the read portion of a cycle and do not change during the read. The timer interrupt
request bit (T8IF) remains set until cleared by writing a “1” to the T8IFR bit in the
T8CR. If writing to the timer 8 counter register (T8CNTR) occurs before the timer
interrupt is served, the interrupt is lost. The T8IF bit may also be used as a
scanned status bit in a non-interrupt mode of operation.
The 3-bit control prescaler is a 7-bit divider which is used to extend the maximum
length of the timer. Bit 0, bit 1 and bit 2 (PS0, PS1 and PS2) of T8CR are programmed to choose the appropriate prescaler output which is used as the counter
input.
10.2
TIMER8 CONTROL AND STATUS REGISTER (T8CSR)
The T8CSR at address $000D enables the software to control the operation of the
8-bit timer.
T8CSR R
$000D
W
reset:
BIT 7
T8IF
0
BIT 6
0
T8IFR
0
BIT 5
T8IE
0
BIT 4
0
0
BIT 3
BIT 2
BIT 1
BIT 0
T8EN
PS2
PS1
PS0
0
1
0
0
Figure 10-2. Timer8 Control and Status Register
T8IF - Timer8 Interrupt Flag
T8IF is set when Timer8 Counter Register counts down to zero. A CPU interrupt
request will be generated if T8IE is set. Writing a "1" to the T8IFR bit clears the
T8IF bit. Writing a "0" to this bit has no effect. Reset clears T8IF.
1 = Timer8 has count down to zero
0 = Timer8 has not count down to zero
T8IFR - Timer8 Interrupt Flag Reset
The T8IFR bit is a write-only bit, which clears the T8IF ag b y writing “1” to this bit
when the T8IF bit is set. Writing a "0" has no effect. Reset does not affect this bit
1 = Clear T8IF ag bit
0 = No effect on T8IF ag bit
T8IE - Interval Timer Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the T8IF bit is set.
Reset clears this bit.
1 = 8-Bit Timer Interrupt enabled
0 = 8-Bit Timer Interrupt disabled
10-2
8-BIT TIMER
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
T8EN - Timer8 Enable
This read/write bit enables the Timer8. Reset clears this bit.
1 = Timer8 enabled
0 = Timer8 disabled
PS2-PS0 - Prescaler select
Freescale Semiconductor, Inc...
These read/write bits is used to select the clock frequency to drive the 8-bit timer
counter. The counter will be driven by a internal bus clock (E-clock) through this
prescaler ratio. Upon reset and power on reset, the value of prescaler is set to a
default value of divided by 16.
10.3
PS2
PS1
PS0
DIVIDE RATIO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16 (default after reset)
32
64
128
TIMER8 COUNTER REGISTER (T8CNTR)
The T8CNTR is a read/write register which contains the current value of the 8-bit
timer counter. Reading this register enables the software to calculate the number
of internal and external clocks since the timer interrupt request ag (T8IF) was
set. Reading this address does not disturb the counter operation.
BIT 7
T8CNTR R
$000E
W
reset:
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
U
U
U
Timer 8 Counter Register
U
U
U
U
U
Figure 10-3. Timer8 Counter Register
NOTE
This timer is used during the power-on sequence to time out the POR signal. The
timer is con gured at po wer-on, with a prescaler division ratio of 16 and set to $FF
in Timer counter register. Also the clock source for the COP watchdog system is
derived from the output of this timer, hence a reset or preset of the prescaler and
timer counter register may affect the frequency of the watchdog timeout.
10.4
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
Please refer to section on RESETS for details.
MC68HC05PL4
REV 2.0
8-BIT TIMER
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10-3
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GENERAL RELEASE SPECIFICATION
10.5
April 30, 1998
8-BIT TIMER OPERATION DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
10.6
8-BIT TIMER OPERATION DURING STOP MODE
The timer ceases counting in STOP mode. When STOP is exited by an external
interrupt or an external reset, the internal oscillator will resume its operation, followed by internal processor stabilization delay. The timer is then cleared to zero
and resumes its operation.
Freescale Semiconductor, Inc...
NOTE
The T8IF bit in T8CSR will be set after MCU exit from STOP mode. To avoid
generation of the timer 8 interrupt when exiting STOP mode, it is recommended to
clear T8IE bit prior entering STOP mode. After exiting STOP mode T8IF bit must
be cleared before setting T8IE bit.
10-4
8-BIT TIMER
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 11
DIGITAL TO ANALOG CONVERTER
This section describes Digital-to-Analog module used for DTMF generation.
Freescale Semiconductor, Inc...
11.1
DAC CONTROL AND DATA REGISTER
BIT 7
DACDR R
DACEN
$000F
W
reset:
0
BIT 6
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DA5
DA4
DA3
DA2
DA1
DA0
0
0
0
0
0
0
0
Figure 11-1. DAC Control and Data Register
DACEN - DAC Channel Enable
Ths read/write bit enables/disables the DAC module for DTMF output.
1 = Enable DAC module and con gure P A1/DTMF as DTMF output pin.
0 = Disable DAC module and con gure PA1/DTMF as general purpose
PA1 pin.
DA5-DA0
These bits determine the output voltage of the DAC channel. The output voltage value is determined by:
VOUT = (VDD x DA[0:5]) x 26
There are 64 evenly spaced voltage levels available between VDD and VSS. The
lowest voltage is VSS and the highest voltage is 63/64VDD.
11.2
DAC OPERATION DURING WAIT MODE
In WAIT mode, the DAC continues to output a x ed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if further power saving is required in WAIT mode.
11.3
DAC OPERATION DURING STOP MODE
In STOP mode, the DAC continues to output a x ed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if further power saving is required in STOP mode.
MC68HC05PL4
REV 2.0
DIGITAL TO ANALOG CONVERTER
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11-1
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GENERAL RELEASE SPECIFICATION
11.4
April 30, 1998
DAC CHARACTERISTICS
(VDD = 4.0V ±10%, VSS = 0 Vdc, TA = TL°C to TH°C, unless otherwise noted)
Characteristic
Symbol
Min
Unit
—
6
6
Bits
Absolute Accuracy
4.0V
2.0V
Vout
Vout
0
±VDD/64
V
DAC Output Resistance
Rdac
7600
15600
Ω
Freescale Semiconductor, Inc...
Resolution
Max
11-2
DIGITAL TO ANALOG CONVERTER
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 12
INSTRUCTION SET
This section describes the addressing modes and instruction types.
Freescale Semiconductor, Inc...
12.1
ADDRESSING MODES
The CPU uses eight addressing modes for exibility in accessing data. The
addressing modes de ne the manner in which the CPU nds the data required to
execute an instruction. The eight addressing modes are the following:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, No Offset
•
Indexed, 8-Bit Offset
•
Indexed, 16-Bit Offset
•
Relative
12.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry ag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
12.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the rst b yte, and the
immediate data value is the second byte.
MC68HC05PL4
REV 2.0
INSTRUCTION SET
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GENERAL RELEASE SPECIFICATION
April 30, 1998
12.1.3 Direct
Direct instructions can access any of the rst 256 memor y addresses with two
bytes. The rst b yte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
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12.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
rst b yte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Freescale assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
12.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the rst 256 memor y locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
12.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the rst 511 memor y locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the rst 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
12-2
INSTRUCTION SET
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
12.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The rst byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Freescale Semiconductor, Inc...
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler determines the
shortest form of indexed addressing.
12.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU nds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and veri es that it
is within the span of the branch.
12.1.9 Instruction Types
The MCU instructions fall into the following v e categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
MC68HC05PL4
REV 2.0
INSTRUCTION SET
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GENERAL RELEASE SPECIFICATION
April 30, 1998
12.1.10 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU nds the other oper and in memory.
Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Freescale Semiconductor, Inc...
Instruction
12-4
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
INSTRUCTION SET
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MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
12.1.11 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modi ed v alue back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
12.1.12 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the rst 256 memor y locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU nds the conditional br anch destination by adding the
MC68HC05PL4
REV 2.0
INSTRUCTION SET
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GENERAL RELEASE SPECIFICATION
April 30, 1998
third byte to the program counter if the speci ed bit tests tr ue. The bit to be tested
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
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Instruction
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
Branch Never
BRN
Branch if Bit Set
12-6
Mnemonic
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
INSTRUCTION SET
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REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
12.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the rst 256 b ytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the rst 256 b ytes of memory. The CPU can also test and branch based on
the state of any bit in any of the rst 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Freescale Semiconductor, Inc...
Instruction
Clear Bit
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
12.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
MC68HC05PL4
REV 2.0
Mnemonic
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
INSTRUCTION SET
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12.1.15 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
◊ — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
◊ — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
38
48
58
68
78
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
— — — — —
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
0
b7
b0
C
b7
b0
PC ← (PC) + 2 + rel ? C = 0
ff
ff
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 12-6. Instruction Set Summary
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
12-8
Mn ← 0
INSTRUCTION SET
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GENERAL RELEASE SPECIFICATION
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Branch if Half-Carry
Bit Set
BHI rel
Branch if Higher
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Cycles
BHCS rel
H I N Z C
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
Description
PC ← (PC) + 2 + rel ? H = 1
Effect on
CCR
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
MC68HC05PL4
REV 2.0
Branch Never
20
rr
3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ◊
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ◊
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
PC ← (PC) + 2 + rel ? 1 = 0
INSTRUCTION SET
For More Information On This Product,
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REL
12-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
CLI
Clear Interrupt Mask
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
12-10
Cycles
Set Bit n
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
C←0
— — — — 0
INH
98
I←0
— 0 — — —
INH
9A
— — 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
— — ◊ ◊ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — ◊ ◊ 1
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
— — ◊ ◊ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
Effect on
CCR
H I N Z C
BSET n opr
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Description
Mn ← 1
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
INSTRUCTION SET
For More Information On This Product,
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Address
Mode
Operation
Operand
Freescale Semiconductor, Inc...
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
3C
4C
5C
6C
7C
dd
— — ◊ ◊ —
DIR
INH
INH
IX1
IX
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
— — 0 ◊ ◊
DIR
INH
INH
IX1
IX
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
Negate Byte
(Two’s Complement)
NOP
No Operation
MC68HC05PL4
REV 2.0
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
Freescale Semiconductor, Inc...
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
X ← (M)
C
0
b7
b0
0
C
b7
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
INH
42
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
30
40
50
60
70
— — — — —
INH
9D
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
5
3
3
6
5
2
12-11
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
39
49
59
69
79
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
Effect on
CCR
Description
H I N Z C
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
C
b7
b0
ff
Cycles
Opcode
Freescale Semiconductor, Inc...
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
2
3
4
5
4
3
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
◊ ◊ ◊ ◊ ◊
INH
80
6
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
A ← (A) – (M) – (C)
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
C
b7
b0
ff
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ◊ ◊ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — ◊ ◊ —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
12-12
Store Index
Register In Memory
M ← (A)
M ← (X)
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
2
3
4
5
4
3
Subtract Memory
Byte from
Accumulator
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Software Interrupt
INH
83
10
TAX
Transfer
Accumulator to
Index Register
— — — — —
INH
97
2
(M) – $00
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
A ← (X)
— — — — —
INH
9F
2
— ◊ — — —
INH
8F
2
A ← (A) – (M)
X ← (A)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock and
Enable
Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
MC68HC05PL4
REV 2.0
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
dd
ff
Cycles
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
Freescale Semiconductor, Inc...
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
12-13
12-14
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
REL 2
3
BRA
2
REL
5
5
DIR 1
5
ASR
DIR 1
5
ROR
DIR 1
LSR
DIR 1
5
COM
1
3
11
3
INH 1
3
ASRA
INH 1
3
RORA
INH 1
LSRA
INH 1
3
COMA
INH
3
MUL
INH 1
NEGA
4
3
3
3
INH 2
3
ASRX
INH 2
3
RORX
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
5
INH
6
6
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
5
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
3
INH 1
CLRA
INH 1
TSTA
INH 1
3
INCA
3
INH 1
DECA
INH 1
3
ROLA
INH 1
3
3
INH 2
CLRX
INH 2
TSTX
INH 2
3
INCX
3
INH 2
DECX
INH 2
3
ROLX
INH 2
3
IX1 1
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
6
IX1 1
DEC
IX1 1
6
ROL
ASR
ROR
LSR
COM
NEG
7
IX
5
5
IX
5
IX
5
5
IX
IX 1
5
IX
IX
4
5
IX
IX
5
9
10
2
1
1
1
1
1
1
1
INH 1
WAIT
INH
2
STOP
INH
SWI
INH
RTS
INH
6
RTI
8
2
2
2
2
2
2
2
2
INH
TXA
2
2
MSB
0
4
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
SUB
IX2 2
5
IX2 2
6
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
IX2 2
5
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
BIT
5
IX2 2
5
SUB
D
IX2
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
5 Number of Cycles
DIR Number of Bytes/Addressing Mode
4
IX1 1
4
SUB
E
IX1
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
C
EXT
Register/Memory
DIR 3
3
SUB
B
DIR
BRSET0 Opcode Mnemonic
3
2
IMM 2
LDX
REL 2
2
BSR
6
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
0
2
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
A
IMM
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
INH
2
TAX
9
INH
Control
INH
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
1
IX 1
5
1
IX 1
ASL/LSL
IX1 1
6
ASR
IX1 1
6
ROR
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
Read-Modify-Write
INH
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
NEG
3
DIR
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
BSET0
1
DIR
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
DIR 2
BRCLR7
3
F
DIR 2
5
BRSET7
3
E
DIR 2
5
BRCLR6
3
D
DIR 2
5
BRSET6
3
C
DIR 2
5
BRCLR5
3
B
DIR 2
5
BRSET5
3
A
DIR 2
5
BRCLR4
3
9
DIR 2
5
BRSET4
3
8
DIR 2
5
BRCLR3
3
7
DIR 2
5
BRSET3
3
6
DIR 2
5
BRCLR2
3
5
DIR 2
5
BRSET2
3
4
DIR 2
5
BRCLR1
3
3
DIR 2
5
BRSET1
3
2
DIR 2
5
BRCLR0
3
1
5
DIR 2
5
BRSET0
0
3
0
MSB
LSB
DIR
Bit Manipulation Branch
Table 12-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 13
ELECTRICAL SPECIFICATIONS
This section contains
MC68HC05PL4.
Freescale Semiconductor, Inc...
13.1
the
electrical
and
timing
speci
cations or
f
the
MAXIMUM RATINGS
Maximum ratings are the extreme limits the device can be exposed to without
causing permanent damage to the chip. The device is not intended to operate at
these conditions. The MCU contains circuitry that protects the inputs against damage from high static voltages; however, do not apply voltages higher than those
shown below. Keep VIN and VOUT within the range from VSS to VDD. Connect
unused inputs to the appropriate logical voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Bootloader/Self-Check Mode (IRQ Pin Only)
VIN
VSS –0.3 to 17
V
I
25
mA
TJ
+150
°C
TSTG
–65 to +150
°C
Symbol
Value
Unit
TA
TL to TH
–40 to +80
°C
Current Drain Per Pin Excluding VDD and VSS
Operating Junction Temperature
Storage Temperature Range
13.2
OPERATING TEMPERATURE RANGE
Characteristic
Operating Temperature Range
MC68HC05PL4
13.3
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
SOIC
PDIP
MC68HC05PL4
REV 2.0
Symbol
Value
Unit
θJA
θJA
60
60
°C/W
°C/W
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
13-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.4
SUPPLY CURRENT CHARACTERISTICS
Characteristic
Freescale Semiconductor, Inc...
VDD = 4.4 to 3.6 V
Internal RC (about 500kHz)
Run
Wait
Stop
External Crystal/Ceramic Resonator @ 5.12MHz
Run
Wait
Stop
VDD = 2.5 to 2.0 V
Internal RC (about 500kHz)
Run
Wait
Stop
External Crystal/Ceramic Resonator @ 2MHz
Run
Wait
Stop
NOTES:
1.
2.
3.
4.
5.
6.
7.
13-2
April 30, 1998
Symbol
Min
Typ
Max
Unit
IDD
IDD
IDD
—
—
—
394
36
5
—
—
—
µA
µA
µA
IDD
IDD
IDD
—
—
—
2.816
348
5
—
—
—
mA
µA
µA
IDD
IDD
IDD
—
—
—
128
16
3
—
—
—
µA
µA
µA
IDD
IDD
IDD
—
—
—
560
66
3
—
—
—
µA
µA
µA
VDD as indicated, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
All values shown re ect a verage measurements.
Typical values at midpoint of voltage range, 25°C only.
Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 VDC from either supply rail (VDD or VSS); no DC loads, less than 50 pF on
all outputs, CL = 20pF on OSC2.
Wait, Stop IDD: All ports con gured as inputs , VIL = 0.2 VDC, VIH = VDD – 0.2 VDC.
Stop IDD measured with OSC1 = VDD.
Wait IDD is affected linearly by the OSC2 capacitance.
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
13.5
DC ELECTRICAL CHARACTERISTICS (4V)
Characteristic
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
Symbol
Min
Typ
Max
Unit
Output Voltage
Iload = 10µA
Iload = –10µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
V
Output High Voltage (Iload = –0.8 mA)
PA0:6, PB0:7, PC0:7, PD0:3, RESET
VOH
VDD –0.8
—
—
V
Output Low Voltage
(Iload = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET
(Iload = 10 mA) LED/IRQ/VPP
VOL
VOL
—
—
0.15
0.20
0.4
0.4
V
V
High Sink Current (VOL = 0.4)
Sink current per pin, PA5, PA6
Sink current total for PC4:7 pins
IOL
IOL
—
—
9
9
10
10
mA
mA
Input High Voltage
PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0:6, PB0:7, PC0:7,PD0:3, RESET,LED/IRQ/VPP
VIL
VSS
—
0.3 x VDD
V
Input Current (with pulldowns disabled)
PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP
IIN
—
—
±1
µA
I/O Ports High-Z Leakage Current
PA0:6, PB0:7, PC0:7, PD0:3
IOZ
—
—
±10
µA
Input Pulldown Current (VDD = 4.0V)
PB0:7
IIL
—
34
60
µA
Internal Pull-Up for PB0:7
R
—
110
—
kΩ
NOTES:
1.
2.
3.
VDD = 4.0V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
All values shown re ect a verage measurements.
Typical values at midpoint of voltage range, 25°C only.
MC68HC05PL4
REV 2.0
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
13-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.6
April 30, 1998
DC ELECTRICAL CHARACTERISTICS (2V)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
Iload = 10µA
Iload = –10µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
V
Output High Voltage (Iload = –0.8 mA)
PA0:6, PB0:7, PC0:7, PD0:3, RESET
VOH
VDD –0.3
—
—
V
Output Low Voltage
(Iload = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET
(Iload = 10 mA) LED/IRQ/VPP
VOL
VOL
—
—
0.15
0.30
—
—
V
V
High Sink Current (VOL = 0.4)
Sink current per pin, PA5, PA6
Sink current total for PC4:7 pins
IOL
IOL
—
—
3
3
4
4
mA
mA
Input High Voltage
PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0:6, PB0:7, PC0:7,PD0:3, RESET,LED/IRQ/VPP
VIL
VSS
—
0.2 x VDD
V
Input Current (with pulldowns disabled)
PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP
IIN
—
—
±1
µA
I/O Ports High-Z Leakage Current
PA0:6, PB0:7, PC0:7, PD0:3
IOZ
—
—
±10
µA
Input Pulldown Current (VDD = 4.0V)
PB0:7
IIL
—
6
11
µA
Internal Pull-Up for PB0:7
R
—
330
—
kΩ
NOTES:
1.
2.
3.
13-4
VDD = 2.0V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
All values shown re ect a verage measurements.
Typical values at midpoint of voltage range, 25°C only.
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
13.7
CONTROL TIMING (4V)
Characteristic
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
Symbol
Min
Max
Unit
Frequency of Oscillation (OSC)
RC Oscillator Option
Crystal Oscillator Option
External Clock Source
fOSC
fOSC
fOSC
200
0.1
DC
500
5.12
5.12
kHz
MHz
MHz
Internal Operating Frequency, Crystal or External Clock (fOSC/2)
RC Oscillator Option
Crystal Oscillator Option
External Clock Source
fOP
fOP
fOP
100
0.05
DC
250
2.56
2.56
kHz
MHz
MHz
Cycle Time
RC Oscillator Option
External oscillator or clock source
tCYC
tCYC
4
0.39
—
—
µs
µs
OSC1 Pulse Width (external clock input)
tOH,tOL
195
—
ns
Timer
Resolution
Input Capture (TCAP) pulse width
tRESL
tTH, tTL
4
284
—
—
tCYC
ns
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
284
—
ns
Interrupt Pulse Period
tILIL
see note 2
—
tCYC
NOTES:
1. VDD = 4.0V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
2. The minimum period TILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 21 tCYC.
13.8
CONTROL TIMING (2V)
Characteristic
Symbol
Min
Max
Unit
Frequency of Oscillation (OSC)
RC Oscillator Option
Crystal Oscillator Option
External Clock Source
fOSC
fOSC
fOSC
200
0.1
DC
500
2
2
kHz
MHz
MHz
Internal Operating Frequency, Crystal or External Clock (fOSC/2)
RC Oscillator Option
Crystal Oscillator Option
External Clock Source
fOP
fOP
fOP
100
0.05
DC
250
1
1
kHz
MHz
MHz
Cycle Time
RC Oscillator Option
External oscillator or clock source
tCYC
tCYC
4
1
—
—
µs
µs
OSC1 Pulse Width (external clock input)
tOH,tOL
5
—
ns
Timer
Resolution
Input Capture (TCAP) pulse width
tRESL
tTH, tTL
4
284
—
—
tCYC
ns
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
284
—
ns
Interrupt Pulse Period
tILIL
see note 2
—
tCYC
NOTES:
1. VDD = 2.0V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
2. The minimum period TILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 21 tCYC.
MC68HC05PL4
REV 2.0
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
13-5
Freescale Semiconductor, Inc.
April 30, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
13-6
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 14
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the 28-pin PDIP, 28-pin
SOIC, and 28-pin SSOP packages.
Freescale Semiconductor, Inc...
14.1
28-PIN PDIP (CASE 710)
28
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
15
B
1
14
A
L
C
N
H
G
D
F
14.2
M
K
J
°
°
°
°
28-PIN SOIC (CASE 751F)
-A28
! ! %
! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
R X 45°
C
-T26X
-T-
G
K
F
J
MC68HC05PL4
REV 2.0
MECHANICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
°
°
°
°
14-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
14.3
April 30, 1998
28-PIN SSOP
D/2
1.00
3
2
2.36
DIA. PIN
1.00 DIA.
1
H +
0.20
M E
M
E/2
1.00
I NE
HI L
I PP
S- P
N
Freescale Semiconductor, Inc...
6
TOP VIEW
BOTTOM VIEW
12-16°
+
e
0.12
M T
E
D
S
b 8
A2
A
-C3
-T-
0.076
C
7
-E-
A1
-D-
SEATING
PLANE
4
4
SEE
DETAIL "A"
SIDE VIEW
END VIEW
0.235 MIN
b1
WITH LEAD FINISH
0° MIN.
GAUGE PLANE
PARTING LINE
c
c1
R
G
8
0.25 BSC
M
b
L
G
5
SECTION G-G
SEATING PLANE
L1
BASE METAL
10
DETAIL 'A'
NOTES:
1. MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES).
2. DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982.
3. "T" IS A REFERENCE DATUM.
4. "D" & "E" ARE REFERENCE DATUMS AND DO NOT
INCLUDE MOLD FLASH OR PROTRUSIONS, BUT
DO INCLUDE MOLD MISMATCH AND ARE MEASURED
AT THE PARTING LINE, MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE.
5. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
6. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY.
7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN
EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE
THAN 0.07mm AT LEAST MATERIAL CONDITION.
9. CONTROLLING DIMENSION: MILLIMETERS.
10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS.
11. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH
JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN
14-2
S
Y
M
B
O
L
A
A1
A2
b
b1
c
c1
D
E
e
H
L
L1
N
M
R
DIMENSIONS IN MM
MIN.
MAX.
NOM.
1.73
0.05
1.68
0.25
0.25
0.09
0.09
10.07
5.20
7.65
0.63
0
0.09
1.86
0.13
1.73
—
0.30
—
0.15
10.20
5.30
0.65 BSC
7.80
0.75
1.25 REF.
28
4
0.15
1.99
0.21
1.78
0.38
0.33
0.20
0.16
10.33
5.38
DIMENSIONS IN INCH
MIN.
NOM.
MAX.
.068
.002
.066
.010
.010
.004
.004
.397
.205
7.90
0.95
.301
.025
8
0
.004
MECHANICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
.073
.005
.068
—
.012
—
.006
.402
.209
.0256 BSC
.307
.030
.049 REF.
28
4
.006
N
O
T
E
.078
.008
.070
.015
.013
.008
.006
.407
.212
8,10
10
10
10
4
4
.311
.037
5
6
8
MC68HC05PL4
REV 2.0
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
APPENDIX A
MC68HC705PL4
Freescale Semiconductor, Inc...
This appendix describes the MC68HC705PL4 and MC68HC705PL4B, the emulation parts for MC68HC05PL4 and MC68HC05PL4B respectively. The entire
MC68HC05PL4 data sheet applies to the MC68HC705PL4 and
MC68HC705PL4B, with exceptions outlined in this appendix.
References to MC68HC705PL4 in this appendix refers to both
MC68HC705PL4 and MC68HC705PL4B devices, unless otherwise stated.
A.1
the
INTRODUCTION
The MC68HC705PL4 is an EPROM version of the MC68HC705PL4, and the
MC68HC705PL4B is an EPROM version of the MC68HC705PL4B. Both HC705
parts are used as the emulation part for their MC68HC05 counterparts. Both
MC68HC705 parts are functionally identical to their MC68HC05 counterparts,
with the exception of the 4k-bytes user ROM is replaced by 4k-bytes user
EPROM.
Table A-1. MC68HC705PL4 and MC68HC705PL4B Differences
Device
MC68HC705PL4
MC68HC705PL4B
A.2
Pin27
PA0
OSC2
MEMORY
The MC68HC705PL4 memory map is shown on Figure A-1.
A.3
BOOTLOADER MODE
Bootloader mode is entered upon the rising edge of RESET if LED/IRQ/VPP pin is
at VTST and PB0/KBI0 at VDD. The Bootloader program is masked in the ROM
area from $1E00 to $1FEF. This program handles copying of user code from an
external EPROM into the on-chip EPROM. The bootload function has to be done
from an external EPROM. The bootloader performs one programming pass at
1ms per byte then does a verify pass.
A.4
EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control Register located at address $001E.
Please contact Freescale for programming board availability.
MC68HC05PL4
REV 2.0
A-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
$0000
$001F
$0020
$00C0
$00FF
$011F
$0120
April 30, 1998
I/O REGISTERS
32 BYTES
USER RAM
BYTES
STACK 256
64 BYTES
Freescale Semiconductor, Inc...
UNUSED
$0DFF
$0E00
USER EPROM
4096 BYTES
$1DFF
$1E00
$1FEF
$1FF0
$1FFF
BOOTSTRAP ROM
496 BYTES
USER VECTORS
16 BYTES
RESERVED
$1FF0-$1FF1
RESERVED
$1FF2-$1FF3
KEYBOARD
$1FF4-$1FF5
8-BIT TIMER
$1FF6-$1FF7
16-BIT TIMER
$1FF8-$1FF9
IRQ
$1FFA-$1FFB
SWI
$1FFC-$1FFD
RESET
$1FFE-$1FFF
Figure A-1. MC68HC705PL4B Memory Map
A.4.1 EPROM Program Control Register (PCN)
This register is provided for programming the on-chip EPROM in the
MC68HC705PL4.
bit-7
PCR
$001E
bit-6
Read
bit4
bit-3
bit-2
RESERVED
Write
Reset
bit-5
0
0
0
0
0
0
bit1
bit-0
ELAT
PGM
0
0
ELAT – EPROM LATch control
0 = EPROM address and data bus con gured f or normal reads
1 = EPROM address and data bus con gured for programming (writes
to EPROM cause address and data to be latched). EPROM is in
programming mode and cannot be read if ELAT is 1. This bit should
not be set when no programming voltage is applied to the VPP pin.
MC68HC05PL4
REV 2.0
A-2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
PGM – EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT ≠ 1,
then PGM = 0.
A.4.2 Programming Sequence
The EPROM programming sequence is:
Freescale Semiconductor, Inc...
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure A-2 shows the o w required to successfully program the EPROM.
A.5
EPROM PROGRAMMING SPECIFICATIONS
Table A-2. EPROM Programming Electrical Characteristics
(VDD = 4V ±10%, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic
Programming Voltage
Programming Current
Programming Time per byte
Symbol
Min
Typ
Max
Unit
VPP
—
12.5
—
V
IPP
—
5
10
mA
tEPGM
—
1
—
ms
MC68HC05PL4
REV 2.0
A-3
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GENERAL RELEASE SPECIFICATION
April 30, 1998
START
ELAT=1
Write EPROM byte
Freescale Semiconductor, Inc...
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write
additional
byte?
N
END
Figure A-2. EPROM Programming Sequence
MC68HC05PL4
REV 2.0
A-4
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Freescale Semiconductor, Inc...
April 30, 1998
GENERAL RELEASE SPECIFICATION
VSS
1
28
OSC1
VDD
2
27
PA0
PC7
3
26
PC0
PC6
4
25
PC1
RESET
5
24
PA1/DTMF
PB7
6
23
PA2/TCAP
PB6
7
22
PA3/TCMP
PB5
8
21
PA4
PB4
9
20
PA5
PB3/KBI3
10
19
PA6
PC5
11
18
PC2
PC4
12
17
PC3
PB2/KBI2
13
16
LED/IRQ/VPP
PB1/KBI1
14
15
PB0/KBI0
Figure A-3. MC68HC705PL4 Pin Assignment
VSS
1
28
OSC1
VDD
2
27
OSC2
PC7
3
26
PC0
PC6
4
25
PC1
RESET
5
24
PA1/DTMF
PB7
6
23
PA2/TCAP
PB6
7
22
PA3/TCMP
PB5
8
21
PA4
PB4
9
20
PA5
PB3/KBI3
10
19
PA6
PC5
11
18
PC2
PC4
12
17
PC3
PB2/KBI2
13
16
LED/IRQ/VPP
PB1/KBI1
14
15
PB0/KBI0
Figure A-4. MC68HC705PL4B Pin Assignment
MC68HC05PL4
REV 2.0
A-5
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GENERAL RELEASE SPECIFICATION
A.6
SUPPLY CURRENT CHARACTERISTICS
Characteristic
VDD = 4.4 V to 3.6V
Internal RC (about 500kHz)
Run
Wait
Stop
External Crystal/Ceramic Resonator @ 5.12MHz
Run
Wait
Stop
NOTES:
1.
2.
3.
4.
Freescale Semiconductor, Inc...
April 30, 1998
5.
6.
7.
Symbol
Min
Typ
Max
Unit
IDD
IDD
IDD
—
—
—
966
486
4
—
—
—
µA
µA
µA
IDD
IDD
IDD
—
—
—
4.398
922
5
—
—
—
mA
µA
µA
VDD as indicated, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted.
All values shown re ect a verage measurements.
Typical values at midpoint of voltage range, 25°C only.
Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 VDC from either supply rail (VDD or VSS); no DC loads, less than 50 pF on all
outputs, CL = 20pF on OSC2.
Wait, Stop IDD: All ports con gured as inputs , VIL = 0.2 VDC, VIH = VDD – 0.2 VDC.
Stop IDD measured with OSC1 = VDD.
Wait IDD is affected linearly by the OSC2 capacitance.
MC68HC05PL4
REV 2.0
A-6
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Freescale Semiconductor, Inc...
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HC05PL4GRS/H