MICROCHIP 93C86A

93AA86A/B/C, 93LC86A/B/C,
93C86A/B/C
16K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
VCC Range
ORG Pin
PE Pin
Word Size
Temp Ranges
Packages
93AA86A
1.8-5.5
No
No
8-bit
I
OT
93AA86B
1.8-5-5
No
No
16-bit
I
OT
93LC86A
2.5-5.5
No
No
8-bit
I, E
OT
93LC86B
2.5-5.5
No
No
16-bit
I, E
OT
93C86A
4.5-5.5
No
No
8-bit
I, E
OT
93C86B
4.5-5.5
No
No
16-bit
I, E
OT
93AA86C
1.8-5.5
Yes
Yes
8 or 16-bit
I
P, SN, ST, MS, MC
93LC86C
2.5-5.5
Yes
Yes
8 or 16-bit
I, E
P, SN, ST, MS, MC
93C86C
4.5-5.5
Yes
Yes
8 or 16-bit
I, E
P, SN, ST, MS, MC
Features:
Description:
•
•
•
•
•
The Microchip Technology Inc. 93XX86A/B/C devices
are 16K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX86C are dependent upon external logic
levels driving the ORG pin to set word size. In the
SOT-23 package, the 93XX86A devices provide
dedicated 8-bit memory organization, while the
93XX86B devices provide dedicated 16-bit memory
organization. A Program Enable (PE) pin allows the
user to write-protect the entire memory array.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory applications.
The entire 93XX Series is available in standard
packages including 8-lead PDIP and SOIC, and
advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free
(Pure Matte Sn) finish is available.
•
•
•
•
•
•
•
•
•
Low-power CMOS technology
ORG pin to select word size for ‘86C’ version
2048 x 8-bit organization ‘A’ devices (no ORG)
1024 x 16-bit organization ‘B’ devices (no ORG)
Program Enable pin to write-protect the entire
array (‘86C’ version only)
Self-timed erase/write cycles (including
auto-erase)
Automatic ERAL before WRAL
Power-on/off data protection circuitry
Industry standard 3-wire serial I/O
Device Status signal (Ready/Busy)
Sequential read function
1,000,000 E/W cycles
Data retention > 200 years
Temperature ranges supported:
- Industrial (I)
-40°C to +85°C
Package Types (not to scale)
PDIP/SOIC
(P, SN)
- Automotive (E) -40°C to +125°C
Pin Function Table
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
PE
Program Enable
ORG
Memory Configuration
VCC
Power Supply
© 2005 Microchip Technology Inc.
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
SOT-23
(OT)
VCC
PE
ORG
VSS
DO
VSS
1
6
VCC
2
5
CS
DI
3
4
CLK
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
DFN
(MC)
CS
CLK
PE
DI
ORG DO
VSS
VCC
1
2
3
4
8
7
6
5
VCC
PE
ORG
VSS
DS21797G-page 1
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
Symbol
No.
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Min
Typ
Max
Units
Conditions
D1
VIH1
VIH2
High-level input voltage
2.0
0.7 VCC
—
—
VCC +1
VCC +1
V
V
VCC ≥ 2.7V
VCC < 2.7V
D2
VIL1
VIL2
Low-level input voltage
-0.3
-0.3
—
—
0.8
0.2 VCC
V
V
VCC ≥ 2.7V
VCC < 2.7V
D3
VOL1
VOL2
Low-level output voltage
—
—
—
—
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 μA, VCC = 2.5V
D4
VOH1
VOH2
High-level output voltage
2.4
VCC - 0.2
—
—
—
—
V
V
IOH = -400 μA, VCC = 4.5V
IOH = -100 μA, VCC = 2.5V
D5
ILI
Input leakage current
—
—
±1
μA
VIN = VSS or VCC
D6
ILO
Output leakage current
—
—
±1
μA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance (all inputs/
outputs)
—
—
7
pF
VIN/VOUT = 0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D8
ICC write Write current
—
—
—
500
3
—
mA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 2.5V
D9
ICC read Read current
—
—
—
—
—
100
1
500
—
mA
μA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10
ICCS
Standby current
—
—
—
—
1
5
μA
μA
I – Temp
E – Temp
CLK = CS = 0V
ORG = DI
PE = VSS or VCC
(Note 2) (Note 3)
D11
VPOR
VCC voltage detect
—
—
1.5
3.8
—
—
V
V
Note 1:
2:
3:
(Note 1)
93AA86A/B/C, 93LC86A/B/C
93C86A/B/C
This parameter is periodically sampled and not 100% tested.
ORG and PE pin not available on ‘A’ or ‘B’ versions.
Ready/Busy status must be cleared from DO, see Section 3.4 “Data Out (DO)”.
DS21797G-page 2
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
Symbol
No.
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Min
Max
Units
Conditions
A1
FCLK
Clock frequency
—
3
2
1
MHz
MHz
MHz
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A2
TCKH
Clock high time
200
250
450
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A3
TCKL
Clock low time
100
200
450
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A4
TCSS
Chip Select setup time
50
100
250
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A5
TCSH
Chip Select hold time
0
—
ns
1.8V ≤ VCC < 5.5V
A6
TCSL
Chip Select low time
250
—
ns
1.8V ≤ VCC < 5.5V
A7
TDIS
Data input setup time
50
100
250
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A8
TDIH
Data input hold time
50
100
250
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A9
TPD
Data output delay time
—
100
250
400
ns
ns
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
A10
TCZ
Data output disable time
—
100
200
ns
ns
4.5V ≤ VCC < 5.5V, (Note 1)
1.8V ≤ VCC < 4.5V, (Note 1)
A11
TSV
Status valid time
—
200
300
500
ns
ns
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
A12
TWC
Program cycle time
—
5
ms
Erase/Write mode (AA and LC
versions)
A13
TWC
—
2
ms
Erase/Write mode
(93C versions)
A14
TEC
—
6
ms
ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15
TWL
—
15
ms
WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16
—
1M
—
Note 1:
2:
Endurance
cycles 25°C, VCC = 5.0V, (Note 2)
This parameter is periodically sampled and not 100% tested.
This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site
at www.microchip.com.
© 2005 Microchip Technology Inc.
DS21797G-page 3
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
FIGURE 1-1:
CS
SYNCHRONOUS DATA TIMING
VIH
TCSS
VIL
TCKH
TCKL
TCSH
VIH
CLK
VIL
TDIS
TDIH
VIH
DI
VIL
DO
(Read)
DO
(Program)
Note:
TCZ
TPD
TPD
VOH
VOL
TCZ
TSV
VOH
Status Valid
VOL
TSV is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX86B OR 93XX86C WITH ORG = 1)
Instruction
SB
Opcode
Address
READ
1
10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
EWEN
1
00
ERASE
1
11
ERAL
1
00
WRITE
1
01
WRAL
1
00
0
1
X
X
X
X
X
X
X
X
EWDS
1
00
0
0
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
X
X
X
X
X
X
X
X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data In
Data Out
Req. CLK
Cycles
—
D15-D0
29
—
HighZ
13
—
(RDY/BSY)
13
—
(RDY/BSY)
13
D15-D0
(RDY/BSY)
29
D15-D0
(RDY/BSY)
29
—
High-Z
13
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX86A OR 93XX86C WITH ORG = 0)
Instruction
SB
Opcode
Address
READ
1
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
EWEN
1
00
ERASE
1
11
ERAL
1
00
WRITE
1
01
WRAL
1
00
0
1
X
X
X
X
X
X
X
X
X
EWDS
1
00
0
0
X
X
X
X
X
X
X
X
X
—
DS21797G-page 4
1
1
X
X
X
X
Data In
X
X
X
X
X
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
X
X
X
X
X
X
X
X
X
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
Req. CLK
Cycles
—
D7-D0
22
—
High-Z
14
—
(RDY/BSY)
14
—
(RDY/BSY)
14
D7-D0
(RDY/BSY)
22
D7-D0
(RDY/BSY)
22
High-Z
14
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.0
FUNCTIONAL DESCRIPTION
2.2
Data In/Data Out (DI/DO)
When the ORG pin (93XX86C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
2.1
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
© 2005 Microchip Technology Inc.
2.3
Data Protection
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS
command should be performed after
every write operation and an external 10
kΩ pull-down protection resistor should be
added to the CS pin.
After power-up the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Note:
To prevent accidental writes to the array in
the 93XX86C devices, set the PE pin to a
logic low.
DS21797G-page 5
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
Block Diagram
VCC
VSS
Memory
Array
Address
Decoder
Address
Counter
Data Register
Output
Buffer
DO
DI
ORG*
CS
Mode
Decode
Logic
PE*
CLK
Clock
Register
*ORG and PE inputs are not available on
A/B devices.
DS21797G-page 6
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.4
Erase
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
Note:
FIGURE 2-1:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
ERASE TIMING
TCSL
CS
Check Status
CLK
1
DI
1
1
AN
AN-1 AN-2
•••
A0
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TWC
© 2005 Microchip Technology Inc.
DS21797G-page 7
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.5
Erase All (ERAL)
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
FIGURE 2-2:
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
ERAL TIMING
TCSL
CS
Check Status
CLK
DI
1
0
0
1
0
x
•••
x
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TEC
DS21797G-page 8
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device.
The 93XX86A/B/C powers up in the Erase/Write
Disable (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
FIGURE 2-3:
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all Erase/Write
functions and should follow all programming
operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
EWDS TIMING
TCSL
CS
CLK
1
DI
FIGURE 2-4:
0
0
0
0
•••
x
x
EWEN TIMING
TCSL
CS
CLK
2.7
0
1
DI
0
1
1
•••
x
Read
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string.
FIGURE 2-5:
x
READ TIMING
CS
CLK
DI
DO
1
1
0
High-Z
© 2005 Microchip Technology Inc.
An
•••
A0
0
Dx
•••
D0
Dx
•••
D0
Dx
•••
D0
DS21797G-page 9
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.8
Write
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
The WRITE instruction is followed by 8 bits (If ORG is
low or A-version devices) or 16 bits (If ORG pin is high
or B-version devices) of data which are written into the
specified address. The self-timed auto-erase and
programming cycle is initiated by the rising edge of CLK
on the last data bit.
FIGURE 2-6:
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO
WRITE TIMING
TCSL
CS
CLK
DI
1
0
1
An
•••
A0
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
High-Z
TWC
DS21797G-page 10
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.9
Write All (WRAL)
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command does include an automatic ERAL cycle for
the device. Therefore, the WRAL instruction does not
require an ERAL instruction, but the chip must be in the
EWEN status.
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-7:
WRAL TIMING
TCSL
CS
CLK
DI
1
0
0
0
1
x
•••
x
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
High-Z
TWL
© 2005 Microchip Technology Inc.
DS21797G-page 11
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
3.1
PIN DESCRIPTIONS
Name
SOIC/PDIP/
MSOP/TSSOP/
DFN
SOT-23
CS
1
5
Chip Select
CLK
2
4
Serial Clock
DI
3
3
Data In
DO
4
1
Data Out
VSS
5
2
Ground
ORG
6
—
Organization / 93XX86C
PE
7
—
Program Enable
VCC
8
6
Power Supply
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
Function
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
DS21797G-page 12
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data, synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status
information is available on the DO pin if CS is brought
high after being low for minimum Chip Select low time
(TCSL), and an erase or write operation has been
initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
3.5
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX86A devices are always x8 organization and
93XX86B devices are always x16 organization.
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
3.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is tied
to VCC, the device can be programmed. If the PE pin is
tied to VSS, programming will be inhibited. This pin
cannot be floated, it must be tied to VCC or VSS. PE is
not available on 93XX86A or 93XX86B. On those
devices, programming is always enabled.
© 2005 Microchip Technology Inc.
DS21797G-page 13
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
6-Lead SOT-23
XXNN
8-Lead PDIP
3L86CI
5281L7
Example:
5EL7
Example:
XXXXXXXX
T/XXXNNN
YYWW
93LC86C
I/P e3 1L7
0528
8-Lead SOIC
Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
TYWW
NNN
DS21797G-page 14
Example:
SOT23 Marking Codes
Device
93AA86A
93AA86B
93LC86A
93LC86B
93C86A
93C86B
I-temp
5BNN
5LNN
5ENN
5PNN
5HNN
5TNN
E-temp
–
–
5FNN
5RNN
5JNN
5UNN
Pb-free topside mark is same; Pb-free
noted only on carton label.
93LC86CI
SN e3 0528
1L7
Example:
L86C
I528
1L7
8-Lead 2x3 DFN
Example:
XXX
YWW
NN
3E4
528
L7
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1st Line Marking Codes
Part Number
DFN
TSSOP
93AA86C
MSOP
A86C
I Temp.
E Temp.
3A86CT
3E1
—
93LC86C
L86C
3L86CT
3E4
3E5
93C86C
C86C
3C86CT
3E7
3E8
Note:
T = Temperature grade (I, E)
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
© 2005 Microchip Technology Inc.
DS21797G-page 15
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
Pitch
.026 BSC
A
.043
Overall Height
A2
Molded Package Thickness
.030
.033
.037
A1
.000
.006
Standoff
E
Overall Width
.193 TYP.
E1
.118 BSC
Molded Package Width
D
.118 BSC
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
0°
8°
Foot Angle
c
.003
.006
.009
Lead Thickness
B
.009
.012
.016
Lead Width
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21797G-page 16
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
6-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
B
p1
n
D
1
α
c
A
A2
φ
L
β
Units
Dimension Limits
n
p
MIN
A1
INCHES*
NOM
MAX
MILLIMETERS
NOM
6
0.95
1.90
0.90
1.18
0.90
1.10
0.00
0.08
2.60
2.80
1.50
1.63
2.80
2.95
0.35
0.45
0
5
0.09
0.15
0.35
0.43
0
5
0
5
MIN
Number of Pins
6
Pitch
.038
p1
Outside lead pitch (basic)
.075
Overall Height
A
.035
.046
.057
Molded Package Thickness
.035
.043
.051
A2
Standoff
.000
.003
.006
A1
Overall Width
E
.102
.110
.118
Molded Package Width
.059
.064
.069
E1
Overall Length
D
.110
.116
.122
Foot Length
L
.014
.018
.022
φ
Foot Angle
0
5
10
c
Lead Thickness
.004
.006
.008
Lead Width
B
.014
.017
.020
α
Mold Draft Angle Top
0
5
10
β
Mold Draft Angle Bottom
0
5
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
© 2005 Microchip Technology Inc.
DS21797G-page 17
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21797G-page 18
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2005 Microchip Technology Inc.
DS21797G-page 19
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
INCHES
NOM
MAX
8
.026
.033
.002
.246
.169
.114
.020
0
.004
.007
0
0
.035
.004
.251
.173
.118
.024
4
.006
.010
5
5
.043
.037
.006
.256
.177
.122
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
8
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
2.90
3.00
3.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21797G-page 20
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
b
D
p
n
L
K
E2
E
EXPOSED
METAL
PAD
(NOTE 2)
PIN 1
ID INDEX
AREA
(NOTE 1)
2
DETAIL
ALTERNATE
CONTACT
CONFIGURATION
TOP VIEW
A1
MIN
n
MILLIMETERS*
INCHES
Units
Number of Pins
BOTTOM VIEW
EXPOSED
TIE BAR
(NOTE 3)
A
A3
Dimension Limits
1
D2
MAX
NOM
MIN
MAX
NOM
8
8
Pitch
e
Overall Height
A
.031
.035
.039
0.80
0.90
1.00
Standoff
A1
.000
.001
.002
0.00
0.02
0.05
Contact Thickness
A3
.008 REF.
0.20 REF.
Overall Length
D
.079 BSC
2.00 BSC
Overall Width
E
.118 BSC
0.50 BSC
.020 BSC
3.00 BSC
Exposed Pad Length
D2
.051
–
.069
1.30**
–
1.75
Exposed Pad Width
E2
.059
–
.075
1.50**
–
1.90
L
.012
K
.008
b
.008
Contact Length §
Contact-to-Exposed Pad
Contact Width
§
.016
.020
–
.010
–
.012
* Controlling Parameter
** Not within JEDEC parameters
§ Significant Characteristic
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exposed pad may vary according to die attach paddle size.
3. Package may have one or more exposed tie bars at ends.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent MO-229 VCED-2
DWG No. C04-123
© 2005 Microchip Technology Inc.
0.30
0.20
0.20
0.40
0.50
–
–
0.25
0.30
Revised 09-12-05
DS21797G-page 21
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
APPENDIX A:
REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
Revision D
Corrections to Device Selection Table, Table 1-1, Table
1-2, Section 2.4, Section 2.5, Section 2.8 and Section
2.9. Added note to Figure 2-7.
Revision E
Added DFN package.
Revision F
Added notes throughout.
Revision G
Revised note in Sections 2.8 and 2.9.
Replaced DFN package drawing.
DS21797G-page 22
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2005 Microchip Technology Inc.
DS21797G-page 23
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
Literature Number: DS21797G
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21797G-page 24
© 2005 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
PART NO.
Device
Tape & Reel Temperature
Range
Device:
/XX
X
Package
X
Lead Finish
93AA86A: 16K 1.8V Microwire Serial EEPROM (x8)
93AA86B: 16K 1.8V Microwire Serial EEPROM (x16)
93AA86C: 16K 1.8V Microwire Serial EEPROM w/ORG
93LC86A: 16K 2.5V Microwire Serial EEPROM (x8)
93LC86B: 16K 2.5V Microwire Serial EEPROM (x16)
93LC86C: 16K 2.5V Microwire Serial EEPROM w/ORG
Examples:
a)
b)
c)
93AA86CT-I/MS: 16K, 2048x8 or 1024x16
Serial EEPROM, MSOP package, tape and
reel, 1.8V
a)
93LC86C-I/MS: 16K, 2048x8, 1024x16 Serial
EEPROM, MSOP package, 2.5V
93LC86BT-I/OT:
16K,
1024x16
Serial
EEPROM, SOT-23 package, tape and reel,
2.5V
b)
93C86A:
93C86B:
93C86C:
16K 5.0V Microwire Serial EEPROM (x8)
16K 5.0V Microwire Serial EEPROM (x16)
16K 5.0V Microwire Serial EEPROM w/ORG
a)
Tape & Reel:
Blank =
T
=
Standard packaging
Tape & Reel
Temperature Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
Package:
MS
OT
P
SN
ST
MC
=
=
=
=
=
=
Plastic MSOP (Micro Small outline, 8-lead)
SOT-23, 6-lead (Tape & Reel only)
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
2x3 DFN, 8-lead
Lead Finish:
Blank =
G
=
Note 1:
93AA86C-I/MS: 16K, 2048x8 or 1024x16
Serial EEPROM, MSOP package, 1.8V
93AA86AT-I/OT: 16K, 2048x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
b)
93C86C-I/MS: 16K, 2048x8 or 1024x16 Serial
EEPROM, MSOP package, 5.0V
93C86AT-I/OT: 16K, 2048x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
Pb-free - Matte Tin (see Note 1)
Pb-free - Matte Tin only
Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured
before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).
Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2005 Microchip Technology Inc.
DS21797G-page 25
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
NOTES:
DS21797G-page 26
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21797G-page 27
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10/31/05
DS21797G-page 28
© 2005 Microchip Technology Inc.