FREESCALE MC68EC030

Freescale Semiconductor, Inc.
Order this document
by MC68EC030/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68EC030
Freescale Semiconductor, Inc...
Technical Summary
Second-Generation 32-Bit Enhanced Embedded
Controller
The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:
•
•
•
•
•
•
Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors
Burst-Mode Bus Interface for Efficient DRAM Access
On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)
Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices
25- and 40-MHz Operating Frequency (up to 9.2 MIPS)
Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications
Additional features of the MC68EC030 include:
•
•
•
•
•
•
•
•
•
•
Complete 32-Bit Nonmultiplexed Address and Data Buses
Sixteen 32-Bit General-Purpose Data and Address Registers
Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers
Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection
Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution
Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)
Complete Support for Coprocessors with the M68000 Coprocessor Interface
Internal Status Indication for Hardware Emulation Support
4-Gbyte Direct Addressing Range
Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
©MOTOROLA INC., 1991
µ MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Rev. 1
Freescale Semiconductor, Inc.
INTRODUCTION
The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.
Freescale Semiconductor, Inc...
The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for offchip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.
The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure
1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.
CONTROLLER
CLOCK (40 MHz)
20 MHz
OSC.
3
MC88916
MC68EC030
(40 MHz)
BUS CLOCK
(20 MHz)
BUS CLOCK
(40 MHz)
BUS CLOCK
(80 MHz)
Figure 1.
MC68EC030 Clock Circuitry
The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing
2
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
information. The instruction pipe and other individual control sections provide the secondary decode of
instructions and generate the actual control signals that result in the decoding and interpretation of
nanoROM and microROM information.
Freescale Semiconductor, Inc...
The instruction and data cache blocks operate independently from the rest of the machine, storing
information read by the bus controller for future use with very fast access time. Each cache resides on its
own address bus and data bus, allowing simultaneous access to both. The data and instruction caches
are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache misses.
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
3
4
ADDRESS
BUS
ADDRESS
PADS
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
BUS CONTROL
SIGNALS
DATA
ADDRESS
BUS
PROGRAM
COUNTER
SECTION
EXECUTION UNIT
STAGE
C
ADDRESS
SECTION
STAGE
D
CACHE
HOLDING
REGISTER
(CAHR)
DATA
CACHE
MISALIGNMENT
MULTIPLEXER
DATA
SECTION
INSTRUCTION
CACHE
STAGE
B
INSTRUCTION PIPE
Figure 2. Block Diagram
ADDRESS
BUS
PREFETCH PENDING
BUFFER
MICROBUS
CONTROLLER
WRITE PENDING
BUFFER
BUS CONTROLLER
ACCESS
CONTROL
UNIT
ADDRESS
INSTRUCTION
ADDRESS
BUS
CONTROL
LOGIC
CONTROL
STORE
MICROSEQUENCER AND
CONTROL
Freescale Semiconductor, Inc...
SIZE
MULTIPLEXER
INTERNAL
DATA
BUS
DATA
PADS
DATA
BUS
Freescale Semiconductor, Inc.
MOTOROLA
Freescale Semiconductor, Inc.
The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.
Freescale Semiconductor, Inc...
PROGRAMMING MODEL
As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit generalpurpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, the
address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.
31
16 15
8
7
0
D0
D1
D2
D3
D4
DATA
REGISTERS
D5
D6
D7
31
16 15
0
A0
A1
A2
A3
ADDRESS
REGISTERS
A4
A5
A6
31
16 15
0
31
A7
(USP)
USER STACK
POINTER
PC
PROGRAM
COUNTER
CCR
CONDITION CODE
REGISTER
0
15
8 7
0
0
Figure 3. User Programming Model
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
5
Freescale Semiconductor, Inc.
31
16 15
31
0
16 15
A7'
(ISP)
INTERRUPT
STACK POINTER
A7"
(MSP)
MASTER
STACK POINTER
SR
STATUS
REGISTER
VBR
VECTOR
BASE REGISTER
SFC
ALTERNATE FUNCTION
CODE REGISTERS
0
15
8 7
0
(CCR)
31
0
31
2
0
DFC
Freescale Semiconductor, Inc...
31
0
31
CACR
CACHE CONTROL
REGISTER
CAAR
CACHE ADDRESS
REGISTER
AC0
ACCESS CONTROL
REGISTER 0
AC1
ACCESS CONTROL
REGISTER 1
ACUSR
ACU STATUS
REGISTER
0
31
0
31
0
0
15
Figure 4. Supervisor Programming Model Supplement
The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following
condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits
indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt
state (M).
SYSTEM BYTE
USER BYTE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T1
T0
S
M
0
I2
I1
I0
0
0
0
X
N
Z
V
C
INTERRUPT
PRIORITY MASK
TRACE ENABLE
SUPERVISOR/USER STATE
EXTEND
NEGATIVE
MASTER/INTERRUPT STATE
CONDITION
CODES
ZERO
OVERFLOW
CARRY
Figure 5. Status Register
6
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the
MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The
MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow
instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are
important for software program development and debug.
Freescale Semiconductor, Inc...
The vector base register (VBR) is used to determine the run-time location of the exception vector table in
memory; thus, each separate vector table for each process or task can properly manage exceptions
independent of each other.
The M68000 Family processors distinguish address spaces as supervisor/user, program/data, and CPU
space. These five combinations are specified by the function code pins (FC0/FC1/FC2) during bus
cycles, indicating the particular address space. Using the function codes, the memory subsystem
(hardware) can distinguish between supervisor accesses and user accesses as well as program accesses,
data accesses, and CPU space accesses. To support the full privileges of the supervisor, the alternate
function code registers allow the supervisor to specify the function code for an access by appropriately
preloading the SFC/DFC registers.
The cache registers allow supervisor software manipulation of the on-chip instruction and data caches.
Control and status accesses to the caches are provided by the cache control register (CACR); the cache
address register (CAAR) specifies the address for those cache control functions that require an address.
The access control registers are accessible by the supervisor only. The access control registers are used
to define two memory spaces with caching restrictions. The ACU status register (ACUSR) is used to show
the result of PTEST operations on the ACU.
DATA TYPES AND ADDRESSING MODES
Seven basic data types are supported by the MC68EC030:
• Bits
• Bit Fields (String of consecutive bits, 1–32 bits long)
• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
7
Freescale Semiconductor, Inc.
In addition, operations on other data types, such as memory addresses, status word data, etc., are
provided in the instruction set. The coprocessor mechanism allows direct support of floating-point data
types with the MC68881/MC68882 floating-point coprocessors as well as specialized user-defined data
types and functions. The 18 addressing modes, listed in Table 1, include nine basic types:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Memory Indirect
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Program Counter Memory Indirect
• Absolute
• Immediate
Freescale Semiconductor, Inc...
The register indirect addressing modes support postincrement, predecrement, offset, and indexing.
These capabilities are particularly useful for handling advanced data structures common to sophisticated
applications and high-level languages. The program counter relative mode also has index and offset
capabilities; this addressing mode is generally required to support position- independent software. In
addition to these addressing modes, the MC68EC030 provides data operand sizing and scaling; these
features provide performance enhancements to the programmer.
8
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Table 1. MC68EC030 Addressing Modes
Freescale Semiconductor, Inc...
Addressing Modes
Syntax
Register Direct Addressing
Data Register Direct
Address Register Direct
Dn
An
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
(An)
(An);pl
-(An)
(d16,An)
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
(d8,An,Xn)
(bd,An,Xn)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
([bd,An],Xn,od)
([bd,An,Xn],od)
Program Counter Indirect with Displacement
(d16,PC)
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
(d8,PC,Xn)
(bd,PC,Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
([bd,PC],Xn,od)
([bd,PC,Xn],od)
Absolute Data Addressing
Absolute Short
Absolute Long
xxx.W
xxx.L
Immediate
#<data>
NOTES:
Dn
=
An
=
d8, d16 =
Data Register, D0–D7
Address Register, A0–A7
A twos-complement or sign-extended displacement; added as part of
the effective address calculation; size is 8 (d8) or 16 (d16) bits;
when omitted, assemblers use a value of zero.
Xn
=
Address or data register used as an index register; form is
Xn.SIZE*SCALE, where SIZE is .W or .L (indicates index register
size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by
SCALE); use of SIZE and/or SCALE is optional.
bd
=
A twos-complement base displacement; when present, size can be
16 or 32 bits.
od
=
Outer displacement added as part of effective address calculation
after any memory indirection; use is optional with a size of 16 or 32
bits.
PC
=
Program Counter
<data> =
Immediate value of 8, 16, or 32 bits
()
=
Effective Address
[]
=
Used as indirect address to long-word address.
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
9
Freescale Semiconductor, Inc.
INSTRUCTION SET OVERVIEW
The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on
bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The
MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it
supports all instructions of previous family members.
Table 2. Instruction Set
Mnemonic
Freescale Semiconductor, Inc...
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL,ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BEFXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS,DIVSL
DIVU, DIVUL
EOR
EORI
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
10
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower
Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and
Lower Bounds
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Mnemonic
MOVE
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
PACK
PEA
PFLUSH
PLOAD
PMOVE
PTEST
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Description
Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive OR
Logical Inclusive OR Immediate
Pack BCD
Push Effective Address
No Effect
No Effect
Move to/from ACx Registers
Test Address in ACx Registers
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore Codes
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Coprocessor Instructions
cpBCC
cpDBcc
cpGEN
Branch Conditionally
Test Coprocessor Condition,
Decrement and Branch
Coprocessor General Instruction
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally
Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds
checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)
offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030
can be used on the MC68040 for even more performance. The memory management unit (MMU)
instructions of the MC68030, and MC68040 are not supported by the MC68EC030.
Freescale Semiconductor, Inc...
INSTRUCTION AND DATA CACHES
Studies have shown that typical programs spend most of their execution time in a few main routines or
tight loops. This phenomenon, known as locality of reference, has an impact on program performance.
The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can be
used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to
provide the system with two on-chip caches, one for instructions and one for data.
MC68EC030 CACHE GOALS
Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030
embedded controller caches. The first design goal was to reduce the external bus activity of the CPU
even more than was accomplished with the MC68020. The second design goal was to increase effective
CPU throughput as larger memory sizes or slower memories increased average access time. By placing a
high-speed cache between the controller and the rest of the memory system, the effective memory
access time becomes:
tacc =Rh*tcache + (1-Rh)*text
where tacc is the effective system access time, tcache is the cache access time, text is the access time of
the rest of the system, and Rh is the hit ratio or the percentage of time that the data is found in the cache.
Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial
CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower
and less expensive memories can be used for the same controller performance.
The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are
accessed in less time than is required for external accesses, providing improvement in the access time for
items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be
found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time
required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time
for items found in the caches even further. Third, the autonomous nature of the caches allows instruction
stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.
The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently
so that several internal instructions (those that do not require any external accesses) can execute while
the controller is performing an external access for a previous instruction.
INSTRUCTION CACHE
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
11
Freescale Semiconductor, Inc.
The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting
of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with
address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed of
the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry),
and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the
MC68EC030 whenever a cache miss occurs; using the burst transfer capability, up to four long words can
be filled in one burst operation. The caches cannot be manipulated directly by the programmer except by
the use of the CACR, which provides cache clearing and cache entry clearing facilities. The caches can
also be enabled/disabled by this register. Finally, the system hardware can disable the on-chip caches at
any time by asserting the CDIS signal.
Freescale Semiconductor, Inc...
LONG WORD
SELECT
TAG
F F F A
C C C 3
2 1 0 1
INDEX
A A A A A A A A A A A A A A A A A A A A A A A A
2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
TAG
V
V
V
ACCESS ADDRESS
V
1 OF 16
SELECT
DATA FROM INSTRUCTION
CACHE DATA BUS
TAG REPLACE
VALID
DATA TO INSTRUCTION
CACHE HOLDING REGISTER
ENTRY HIT
COMPARATOR
CACHE CONTROL LOGIC
LINE HIT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
Figure 6.
12
On-Chip Instruction Cache Organization
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
DATA CACHE
The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the
tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly
specifying the address space associated with each line. The data cache employs a write-through policy
with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data
cache and the external device are updated with the new data. If a write cycle generates a cache miss, the
external device is updated, and a new data cache entry can be replaced or allocated for that address,
depending on the state of the write-allocate (WA) bit in the CACR.
LONG-WORD
SELECT
Freescale Semiconductor, Inc...
TAG
F F F A
C C C 3
2 1 0 1
INDEX
A A A A A A A A A A A A A A A A A A A A A A A A
2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
TAG
V
V
V
ACCESS ADDRESS
V
1 OF 16
SELECT
DATA FROM DATA
CACHE DATA BUS
TAG REPLACE
VALID
DATA TO EXECUTION
UNIT
ENTRY HIT
COMPARATOR
CACHE CONTROL LOGIC
LINE HIT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
Figure 7. On-Chip Data Cache Organization
OPERAND TRANSFER MECHANISM
The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the
chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,
can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is
determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size
acknowledge (DSACKx) signals. Synchronous bus cycles, compatible with the synchronous bus on the
MC68030, are terminated with the synchronous termination (STERM) signal and always transfer 32-bits
of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
13
Freescale Semiconductor, Inc.
thereby increasing possible performance. Burst mode transfers can be used to fill lines of the instruction
and data caches when the MC68EC030 asserts cache burst request (CBREQ). After completing the first
cycle with STERM, subsequent cycles may accept data on every clock cycle where STERM is asserted
until the burst is completed. Use of this mode can further increase the available bus bandwidth in systems
that use DRAMs with page, nibble, or static-column mode operation.
ASYNCHRONOUS TRANSFERS
Freescale Semiconductor, Inc...
Though the MC68EC030 has a full 32-bit data bus, it offers the ability to automatically and dynamically
downsize its bus to 8 or 16 bits if peripheral devices are unable to accommodate the entire 32 bits. This
feature allows the programmer to write code that is not bus-width specific. For example, long-word (32 bit)
accesses to peripherals may be used in the code; yet, the MC68EC030 will transfer only the amount of
data that the peripheral can manage. This feature allows the peripheral to define its port size as 8, 16, or
32 bits wide, and the MC68EC030 will dynamically size the data transfer accordingly, using multiple bus
cycles when necessary. Hence, programmers are not required to program for each device port size or
know the specific port size before coding; hardware designers have the flexibility to choose hardware
implementations regardless of software implementations.
The dynamic bus sizing mechanism is invoked by DSACKx and occurs on a cycle-by-cycle basis. For
example, if the controller is executing an instruction that requires reading a long-word operand, it will
attempt to read 32 bits during the first bus cycle to a long-word address boundary. If the port responds
that it is 32 bits wide, the MC68EC030 latches all 32 bits of data and continues. If the port responds that it
is 16 bits wide, the MC68EC030 latches the 16 valid bits of data and continues. An 8-bit port is handled
similarly but has four bus read cycles. Each port is fixed in the assignment to particular sections of the data
bus. However, the MC68EC030 has no restrictions concerning the alignment of operands in memory;
long-word operands need not be aligned to long-word address boundaries. When misaligned data
requires multiple bus cycles, the MC68EC030 automatically runs the minimum number of bus cycles.
Instructions must still be aligned to word boundaries.
The timing of asynchronous bus cycles is also determined by the assertion of DSACKx on a cycle-bycycle basis. If the DSACKx signals are valid 1.5 clocks after the beginning of the bus cycle (with the
appropriate setup time), the cycle terminates in the minimum amount of time (corresponding to threeclock-cycle total). The cycle can be lengthened by delaying DSACKx (effectively inserting wait states in
one-clock increments) until the device being accessed is able to terminate the cycle. This flexibility gives
the controller the ability to communicate with devices of varying speeds while operating at the fastest rate
possible for each device.
The asynchronous transfer mechanism allows external errors to abort cycles upon the assertion of bus
error (BERR) or allows individual bus cycles to be retried with the simultaneous assertion of BERR and
HALT.
14
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
SYNCHRONOUS TRANSFERS
Synchronous bus cycles are terminated by asserting STERM, which automatically indicates that the bus
transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be
performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup
time. However, the bus cycle may be lengthened by delaying STERM (inserting wait states in one-clock
increments) until the device being accessed is able to terminate the cycle. After the assertion of STERM,
these cycles may be aborted upon the assertion of BERR, or they may be retried with the simultaneous
assertion of BERR and HALT.
Freescale Semiconductor, Inc...
BURST READ CYCLES
The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to
the overall system performance. The on-chip caches are organized with a line size of four long words;
there is only one tag for the four long words in a line. Since locality of reference is present to some
degree in most programs, filling of all four entries when a single entry misses can be advantageous,
especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data
can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be
performed only when the MC68EC030 requests them (with the assertion of CBREQ) and only when the
first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (CBACK) input
is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original AS, DS,
R/W, address, function code, and size outputs asserted and latches 32 bits from the data bus at the end
of each subsequent clock cycle that has STERM asserted. This procedure continues until the burst is
complete (the entire block has been transferred), BERR is asserted in lieu of or after STERM, the cache
inhibit in (CIIN) input is asserted, or the CBACK input is negated. The cache preloading allowed by the
bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal
performance impact.
EXCEPTIONS
The types of exceptions and the exception processing sequence are discussed in the following
paragraphs.
TYPES OF EXCEPTIONS
Exceptions can be generated by either internal or external causes. The externally generated exceptions
are interrupts, BERR, and RESET. Interrupts are requests from peripheral devices for controller action;
whereas, BERR and RESET are used for access control and controller restart. The internally generated
exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction
execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is
processed. The other internally generated exceptions are caused by illegal instructions, instruction
fetches from odd addresses, and privilege violations.
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
15
Freescale Semiconductor, Inc.
EXCEPTION PROCESSING SEQUENCE
Exception processing occurs in four steps. During the first step, an internal copy is made of the status
register. After the copy is made, the special controller state bits in the status register are changed. The Sbit is set, putting the controller into the supervisor state. Also, the T1 and T0 bits are negated, allowing
the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the
interrupt priority mask is also updated.
Freescale Semiconductor, Inc...
In the second step, the vector number of the exception is determined. For interrupts, the vector number
is obtained by a controller read that is classified as an interrupt acknowledge cycle. For coprocessordetected exceptions, the vector number is included in the coprocessor exception primitive response.
For all other exceptions, internal logic provides the vector number. This vector number is then used to
generate the address of the exception vector.
The third step is to save the current controller status. The exception stack frame is created and filled on
the current supervisor stack. To minimize the amount of machine state that is saved, various stack frame
sizes are used to contain the controller state, depending on the type of exception and where it occurred
during instruction execution. If the exception is an interrupt and the M-bit is set, the M-bit is then cleared,
and the short four-word exception stack frame that is saved on the master stack is also saved on the
interrupt stack. If the exception is a reset, the M-bit is simply cleared, and the reset vector is accessed.
The MC68EC030 provides the same extensions to the exception stacking process as the MC68020,
MC68030, and MC68040. If the M-bit is set, the master stack pointer (MSP) is used for all task-related
exceptions. When a nontask-related exception occurs (i.e., an interrupt), the M bit is cleared, and the
interrupt stack pointer (ISP) is used. This feature allows all the task's stack area to be carried within a single
controller control block, and new tasks can be initiated by simply reloading the MSP and setting the M-bit.
The fourth and last step of exception processing is the same for all exceptions. The exception vector
offset is determined by multiplying the vector number by four. This offset is then added to the contents of
the vector base register (VBR) to determine the memory address of the exception vector. The new
program counter is fetched from the exception vector. The instruction at the address given in the
exception vector is fetched, and normal instruction decoding and execution is started.
STATUS and REFILL
The MC68EC030 provides the STATUS and REFILL signals to identify internal microsequencer activity
associated with the processing of data pipelined in the pipeline. Since bus cycles are independently
controlled and scheduled by the bus controller, information concerning the processing state of the
microsequencer is not available by monitoring bus signals by themselves. The internal activity identified
by the STATUS and REFILL signals include instruction boundaries, some exception conditions, when
the microsequencer has halted, and instruction pipeline refills. STATUS and REFILL track only the
internal microsequencer activity and are not directly related to bus activity.
16
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
ACCESS CONTROL
Two access control registers are provided on the MC68EC030 to control cachability of accesses for two
independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is
specified in the corresponding ACx register with a base address, a base mask, function code, function
code mask, and read/write mask. A typical use for an access control register is to designate a block of
memory containing I/O devices as non-cachable.
Freescale Semiconductor, Inc...
COPROCESSOR INTERFACE
The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The
interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of
these extensions are the addition of specialized data operands for the existing data types or, for the case
of floating point, the inclusion of new data types and operations implemented by the
MC68881/MC68882 floating-point coprocessors.
SIGNAL DESCRIPTION
Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.
FUNCTION
CODES
ADDRESS
BUS
DATA
BUS
TRANSFER
SIZE
IPL0
IPL1
FC0–FC2
IPL2
IPEND
AVEC
A0–A31
D0–D31
BR
BG
SIZ0
SIZ1
BGACK
OCS
ECS
R/W
ASYNCHRONOUS
BUS CONTROL
RMC
AS
DS
DBEN
DSACK0
DSACK1
CACHE
CONTROL
CIIN
CIOUT
CBREQ
CBACK
MC68EC030
INTERRUPT
CONTROL
BUS ARBITRATION
CONTROL
RESET
HALT
BERR
BUS EXCEPTION
CONTROL
STERM
SYNCHRONOUS
BUS CONTROL
REFILL
STATUS
CDIS
EMULATOR
SUPPORT
CLK
VCC (10)
GND (14)
Figure 8. Functional Signal Groups
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
17
Freescale Semiconductor, Inc.
Table 3. Signal Index
Signal Name
Freescale Semiconductor, Inc...
Function
Function Codes
FC0–FC2
3-bit function code used to identify the address space of each bus
cycle.
Address Bus
A0–A31
32-bit address bus.
Data Bus
D0–D31
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus
cycle.
SIZ0–SIZ1
Indicates the number of bytes remaining to be transferred for this
cycle. These signals, together with A0 and A1, define the active
sections of the data bus.
Size
Operand Cycle Start
OCS
Identical operation to that of ECS except that OCS is asserted only
during the first bus cycle of an operand transfer
External Cycle Start
ECS
Provides an indication that a bus cycle is beginning.
Read/Write
R/W
Defines the bus transfer as a controller read or write.
Read-Modify-Write Cycle
RMC
Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.
Address Strobe
AS
Indicates that a valid address is on the bus.
Data Strobe
DS
Indicates that valid data is to be placed on the data bus by an external
device or has been replaced by the MC68EC030.
Data Buffer Enable
Data Transfer and Size
Acknowledge
Synchronous
Termination
Cache Inhibit In
DBEN
Provides an enable signal for external data buffers.
DSACK0,
DSACK1
Bus response signals that indicate the requested data transfer
operation has completed. In addition, these two lines indicate the size
of the external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.
STERM
Bus response signal that indicates a port size of 32 bits and that data
may be latched on the next falling clock edge.
CIIN
Prevents data from being loaded into the MC68EC030 instruction and
data caches.
Cache Inhibit Out
CIOUT
Reflects the CI bit in ACx registers; indicates that external caches
should ignore these accesses.
Cache Burst Request
CBREQ
Indicates a burst request for the instruction or data cache.
Cache Burst
Acknowledge
CBACK
Indicates that the accessed device can operate in burst mode.
Interrupt Priority Level
18
Mnemonic
IPL0 – IPL2
Provides an encoded interrupt level to the controller.
Interrupt Pending
IPEND
Indicates that an interrupt is pending.
Autovector
AVEC
Requests an autovector during an interrupt acknowledge cycle.
Bus Request
BR
Indicates that an external device requires bus mastership.
Bus Grant
BG
Indicates that an external device may assume bus mastership.
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership.
Reset
RESET
System reset.
Halt
HALT
Indicates that the controller should suspended bus activity.
Bus Error
BERR
Indicates that an erroneous bus operation is being attempted.
Cache Disable
CDIS
Dynamically disables the on-chip cache to assist emulator support.
Pipe Refill
REFILL
Indicates when the MC68EC030 is beginning to fill pipeline.
Microsequencer Status
STATUS
Indicates the state of the microsequencer.
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Clock
CLK
Clock input to the controller.
Table 3. Signal Index – Continued
Signal Name
Mnemonic
Function
Power Supply
VCC
Power supply.
Ground
GND
Ground connection.
NC
Do not connect.
Freescale Semiconductor, Inc...
No Connect
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
19
Freescale Semiconductor, Inc.
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Rating
Symbol
Unit
Supply Voltage
VCC
-0.3 to +7.0
V
Input Voltage
Vin
-0.5 to +7.0
V
Operating Temperature Range
Minimum Ambient Temperature
Maximum Ambient Temperature
TA
TA
0
70
Tstg
-55 to 150
Storage Temperature Range
Freescale Semiconductor, Inc...
Value
°C
°C
The device contains circuitry to
protect the inputs against damage
due to high static voltages or
electric fields; however, normal
precautions should be taken to
avoid application of voltages higher
than maximum-rated voltages to
these high-impedance circuits.
Tying unused inputs to the
appropriate logic voltage level (e.g.,
either GND or VCC) enhances
reliability of operation.
THERMAL CHARACTERISTICS-- PGA PACKAGE
Characteristic
Thermal Resistance - Plastic
Junction to Ambient
Junction to case
Symbol V a l u e Rating
o
C/W
θ JA
θJC
32
TBD
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in oC can be obtained from:
TJ=TA+(PD • θJA)
(1)
where:
TA
θJA
PD
PINT
PI/O
=
=
=
=
=
Ambient Temperature, oC
Package Thermal Resistance, Junction-to-Ambient, oC/W
PINT + PI/O
ICC X VCC, Watts — Chip Internal Power
Power Dissipation on Input and Output Pins — User Determined
For most applications, PI/O<PINT and can be neglected.
The following is an approximate relationship between PD and TJ (if PI/O is neglected):
PD=K ÷ (TJ+273oC)
(2)
K=PD • (TA + 273oC) + θJA•PD2
(3)
Solving Equations (1) and (2) for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring PD (at thermal equilibrium) for a known TA. Using this value of K, the values of PD and TJ can
be obtained by solving equations (1) and (2) iteratively for any value of TA.
20
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
The total thermal resistance of a package (θJA) can be separated into two components, θJC and θCA ,
representing the barrier to heat flow from the semiconductor junction to the package (case) surface (θJC)
and from the case to the outside ambient air (θCA). These terms are related by the equation:
θJA=θJC + θCA
(4)
θJC is device related and cannot be influenced by the user. However, θCA is user dependent and can
Freescale Semiconductor, Inc...
be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal
convection. Thus, good thermal management on the part of the user can significantly reduce θCA so that
θJA approximately equals; θJC. Substitution of θJC for θJA in equation (1) results in a lower
semiconductor junction temperature.
Values for thermal resistance presented in this document, unless estimated, were derived using the
procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for
MC68XX Microcomponent Devices,” and are provided for design purposes only. Thermal measurements
are complex and dependent on procedure and setup. User derived values for thermal resistance may
differ.
AC ELECTRICAL SPECIFICATION DEFINITIONS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew
times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more
other signals.
The measurement of the AC specifications is defined by the waveforms shown in Figure 9. To test the
parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in Figure 9.
Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in
Figure 9. Inputs are specified with minimum setup and hold times, and are measured as shown. Finally,
the measurement for signal-to-signal specifications is also shown.
Note that the testing levels used to verify conformance to the AC specifications does not affect the
guaranteed DC operation of the device as specified in the DC electrical specifications.
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
21
Freescale Semiconductor, Inc.
DRIVE
TO 2.4 V
2.0 V
CLK
2.0 V
0.8 V
A
DRIVE TO
0.5 V
OUTPUTS(1) CLK
0.8 V
B
VALID
OUTPUT n
2.0 V
2.0 V
0.8 V
0.8 V
VALID
OUTPUT
A
n+1
B
VALID
OUTPUT n
Freescale Semiconductor, Inc...
OUTPUTS(2) CLK
C
DRIVE TO
2.4 V
2.0 V
DRIVE TO
0.5 V
0.8 V
2.0 V
0.8 V
0.8 V
VALID
OUTPUT n+1
D
2.0 V
VALID
INPUT
INPUTS(3) CLK
2.0 V
0.8 V
D
C
2.0 V
INPUTS(4) CLK
0.8 V
VALID
INPUT
2.0 V
0.8 V
DRIVE
TO 2.4 V
DRIVE
TO 0.5 V
2.0 V
ALL SIGNALS(5)
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 9.
22
Drive Levels and Test Points for AC Specifications
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
DC ELECTRICAL SPECIFICATIONS
(VCC=5.0 Vdc ± 5%; GND=0Vdc; temperature in defined ranges)
Characteristics
Input High Voltage
Input Low Voltage
Freescale Semiconductor, Inc...
Input Leakage Current
GND≤Vin,≤VCC
Hi-Z (Off-State) Leakage
Current
@ 2.4 V/0.5 V
BERR,BR, BGACK, CLK,.IPL0–IPL2,
AVEC,
CDIS, DSACK0, DSACK1
HALT, RESET
Symbol
Min
Max
Unit
VIH
VIL
2.0
VCC
0.8
V
2.5
µA
GND
-0.5
-2.5
Iin
-20
20
V
A0-A31, AS, DBEN, DS, D0-D31, FC0-FC2,
R/W, RMC, SIZ0-SIZ1
ITSI
-20
20
µA
A0–A31, AS, BG, D0–D31, DBEN, DS,
ECS, R/W, IPEND
OCS, RMC, SIZ0–SIZ1, FC0–FC2
VOH
2.4
—
V
—
—
—
—
0.5
0.5
0.5
0.5
Output High Voltage
IOH = 400 µA
CBREQ, CIOUT, STATUS, REFILL
Output Low Voltage
IOL = 3.2 mA
IOL = 5.3 mA
IOL = 2.0 mA
IOL = 10.7 mA
V
VOL
A0–A31, FC0–FC2, SIZ0–SIZ1, BG, D0–D31
CBREQ, AS, DS, R/W, RMC, DBEN,
IPEND
STATUS, REFILL, CIOUT, ECS, OCS
HALT,RESET
Power Dissipation (TA=0C)
PD
—
2.6
W
Capacitance (see Note)
Vin = 0 V, TA=25C, f=1 MHz
Cin
—
20
pF
CL
—
50
70
130
pF
Load Capacitance
ECS, OCS
CIOUT, STATUS, REFILL
All Other
NOTE: Capacitance is periodically sampled rather than 100% tested.
AC ELECTRICAL SPECIFICATIONS — CLOCK INPUT
Num.
Characteristic
25MHz
(see Figure 10)
40 MHz
Unit
Min
Max
Min
Max
12.5
25
25
40
MHz
Cycle Time Clock
40
80
25
40
ns
2,3
Clock Pulse Width Measured from 1.5 V to 1.5 V
19
61
11.5
29
ns
4,5
Clock Rise and Fall Times
—
4
—
2
ns
Frequency of Operation
1
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
23
Freescale Semiconductor, Inc.
1
2
3
2.0 V
0.8 V
5
4
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.
Freescale Semiconductor, Inc...
Figure 10. Clock Input Timing Diagram
AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES
(VCC=5.0Vdc ± 5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)
Num.
25MHz
40 MHz
Unit
Min
Max
Min
Max
Clock High to Function Code, Size, RMC, IPEND,CIOUT,
Address Valid
0
20
0
14
ns
6A
Clock High to ECS, OCS Asserted
0
15
0
10
ns
6B
Function Code, Size, RMC, IPEND, CIOUT, Address Valid to
Negating Edge of ECS
3
—
3
—
ns
7
Clock High to Function Code Size, RMC, CIOUT, Address Data
High
Impedance
0
40
0
25
ns
8
Clock High to Function Code Size, RMC, IPEND, CIOUT, Address
Invalid
0
—
0
—
ns
9
Clock Low to AS, DS Asserted, CBREQ Valid
3
18
2
10
ns
6
9A1
AS to DS Assertion Skew (Read)
-10
10
-6
6
ns
9B14
AS Asserted to DS Asserted (Write)
27
—
16
—
ns
10
ECS Width Asserted
10
—
5
—
ns
10A
OCS Width Asserted
10
—
5
—
ns
10B7
ECS, OCS Width Negated
5
—
5
—
ns
11
Function Code, Size, RMC, CIOUT, Address Valid to AS Asserted
(and DS Asserted, Read)
7
—
5
—
ns
12
Clock Low to AS, DS, CBREQ Negated
0
18
0
10
ns
Clock Low to ECS/OCS Negated
0
18
0
12
ns
13
AS, DS Negated to Function Code, Size, RMC CIOUT, Address
Invalid
7
—
3
—
ns
14
AS (and DS Read) Width Asserted (Asynchronous Cycle)
70
—
30
—
ns
DS Width Asserted (Write)
30
—
18
—
ns
AS (and DS, Read) Width Asserted (Synchronous Cycle)
30
—
18
—
ns
AS, DS Width Negated
30
—
18
—
ns
12A
14A11
14B
15
24
Characterstics
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES
(Continued)
Num.
25MHz
40 MHz
Unit
Min
Max
Min
Max
DS Negated to AS Asserted
25
—
16
—
ns
16
Clock High to AS, DS, R/W, DBEN, CBREQ High Impedance
—
40
—
25
ns
17
AS, DS Negated to R/W Invalid
7
—
3
—
ns
18
Clock High to R/W High
0
20
0
14
ns
20
Clock High to R/W Low
0
20
0
14
ns
21
R/W High to AS Asserted
7
—
5
—
ns
22
R/W Low to DS Asserted (Write)
47
—
24
—
ns
23
Clock High to Data-Out Valid
—
20
—
14
ns
24
Data-Out Valid to Negating Edge of AS
5
—
3
—
ns
15A8
Freescale Semiconductor, Inc...
Characterstics
2511
AS, DS Negated to Data-Out Invalid
7
—
3
—
ns
25A9,11
DS Negated to DBEN Negated (Write)
7
—
3
—
ns
2611
Data-Out Valid to DS Asserted (Write)
7
—
3
—
ns
Data-In Valid to Clock Low (Setup)
2
—
1
—
ns
27A
Late BERR/HALT Asserted to Clock Low (Setup)
5
—
3
—
ns
2812
AS, DS Negated to DSACKx, BERR, HALT, AVEC Negated
(Asynchronous Hold)
0
40
0
20
ns
28A12
Clock Low to DSACKx, BERR, HALT, AVEC Negated
(Synchronous Hold)
8
70
6
40
ns
2912
AS, DS Negated to Data-In Invalid (Asynchronous Hold)
0
—
0
—
ns
AS, DS Negated to Data-In High Impedance
—
40
—
25
ns
Clock Low to Data-In Invalid (Synchronous Hold)
8
—
6
—
ns
Clock Low to Data-In High Impedance (Read followed by Write)
—
60
—
30
ns
DSACKx Asserted to Data-In Valid (Asynchronous Data Setup)
—
28
—
14
ns
DSACKx Asserted to DSACKx Valid (Skew)
—
7
—
3
ns
32
RESET Input Transition Time
—
1.5
—
1.5
Clks
33
Clock Low to BG Asserted
0
20
0
14
ns
34
Clock Low to BG Negated
0
20
0
14
Clks
35
BR Asserted to BG Asserted (RMC Not Asserted)
1.5
3.5
1.5
3.5
Clks
37
BGACK Asserted to BG Negated
1.5
3.5
1.5
3.5
Clks
37A6
BGACK Asserted to BR Negated
0
1.5
0
1.5
ns
27
29A12
3012
30A12
312
31A3
39
BG Width Negated
60
—
30
—
ns
39A
BG Width Asserted
60
—
30
—
ns
40
Clock High to DBEN Asserted (Read)
0
20
0
16
ns
41
Clock Low to DBEN Negated (Read)
0
20
0
16
ns
42
Clock Low to DBEN Asserted (Write)
0
20
0
16
ns
43
Clock High to DBEN Negated (Write)
0
20
0
16
ns
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
25
Freescale Semiconductor, Inc.
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES
(Concluded)
Freescale Semiconductor, Inc...
Num.
26
Characterstics
25 MHz
40 MHz
Unit
Min
Max
Min
Max
7
—
5
—
ns
44
R/W Low to DBEN Asserted (Write)
455
DBEN Width Asserted
Asynchronous Read
Asynchronous Write
40
80
—
—
22
45
—
—
ns
45A9
DBEN Width Asserted
Synchronous Read
Synchronous Write
5
40
—
—
5
22
—
—
ns
46
R/W Width Asserted (Asynchronous Write or Read)
100
—
50
—
ns
46A
R/W Width Asserted (Synchronous Write or Read)
60
—
30
—
ns
47A
Asynchronous Input Setup Time to Clock Low
2
—
2
—
ns
47B
Asynchronous Input Hold Time from Clock Low
8
—
6
—
ns
484
DSACKx Asserted to BERR, HALT Asserted
—
25
—
14
ns
53
Data-Out Hold from Clock High
3
—
2
—
ns
55
R/W Asserted to Data Bus Impedance Change
20
—
11
—
ns
56
RESET Pulse Width (Reset Instruction)
512
—
512
—
Clks
57
BERR Negated to HALT Negated (Rerun)
0
—
0
—
ns
5810
BGACK Negated to Bus Driven
1
—
1
—
Clks
5910
BG Negated to Bus Driven
1
—
1
—
Clks
6013
Synchronous Input Valid to Clock High (Setup Time)
2
—
2
—
ns
6113
Clock High to Synchronous Input Invalid (Hold Time)
8
—
6
—
ns
62
Clock Low to STATUS, REFILL Asserted
0
20
0
15
ns
63
Clock Low to STATUS, REFILL Negated
0
20
0
15
ns
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
NOTES:
1. This number can be reduced to 5 ns if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx low to data setup time
(#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the
data-in clock low setup time (#27) for the following clock cycle and BERR must only satisfy the late
BERR low to clock low setup time (#27A) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or
DSACK1 to DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1.
4. This specification applies to the first (DSACK0 or DSACK1) DSACKx signal asserted. In the absence of
DSACKx, BERR is an asynchronous input using the asynchronous input setup time (#47A).
5. DBEN may stay asserted on consecutive write cycles.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded,
BG may be reasserted.
7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit
followed immediately by another cache hit, a cache miss, or an operand cycle.
8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time
for DS negated to AS asserted (specification #13A in the MC68881/MC68882 User's Manual).
Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that
the MC68EC030 does not meet the MC68881/MC68882 requirements.
9. This specification allows a system designer to guarantee data hold times on the output side of data
buffers that have output enable signals generated with DBEN. The timing on DBEN precludes its use
for synchronous READ cycles with no wait states.
10. These specifications allow system designers to guarantee that an alternate bus master has stopped
driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence.
11. DS will not be asserted for synchronous write cycles with no wait states.
12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock
(synchronous). The designer is free to use either time.
13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of
the clock while AS is asserted. These values are specified relative to the high level of the rising clock
edge. The values originally published were specified relative to the low level of the rising clock edge.
14. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS
(allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (spec 8B of the
MC68881/MC68882 User's Manual).
MOTOROLA
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
27
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S4
S5
CLK
6
A31-A0
FC2-FC0
SIZ1-SIZ0
6A
RMC
12A
8
10A
Freescale Semiconductor, Inc...
ECS
10
6A
OCS
14
11
13
9A
AS
9
12
11
14
DS
18
20
9
R/W
46
21
41
DBEN
40
17
45
DSACK0
28
31A
DSACK1
31
29
D31-D0
27
29A
BERR
27A
HALT
47A
48
ALL
ASYNCHRONOUS
INPUTS
60
CIIN
61
CBREQ
Figure 11.
28
47B
12
Asynchronous Read Cycle Timing Diagram
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S4
S5
S0
CLK
6
8
A31-A0, FC2-FC0
SIZ1-SIZ0
12A
RMC
10
ECS
10B
10A
Freescale Semiconductor, Inc...
6A
OCS
13
11
15A
14
AS
9
15
14A
DS
22
20
12
9
17
R/W
42
25A
46
DBEN
44
43
45
DSACK0
31A
28
DSACK1
23
53
D31-D0
55
25
26
BERR
48
HALT
6
27A
8
CIOUT
Figure 12.
MOTOROLA
Asynchronous Write Cycle Timing Diagram
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
29
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S0
S1
S2
CLK
A31-A0, FC2-FC0
SIZ1-SIZ0
8
RMC
6
12A
ECS
6A
Freescale Semiconductor, Inc...
OCS
14B
AS
9
DS
18
46A
R/W
40
41
DBEN
45A
CIOUT
12
CBREQ
DSACK0/DSACK1
61
STERM
60
CIIN
30A
CBACK
30
D31-D0
27
Figure 13.
30
Synchronous Read Cycle Timing Diagram
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S0
S1
S2
CLK
A31-A0, FC2-FC0
SIZ1-SIZ0
8
6
RMC
12A
ECS
Freescale Semiconductor, Inc...
6A
OCS
12
9
AS
14B
DS
20
18
46A
R/W
43
42
45A
DBEN
53
23
D31-D0
24
DSACK0/DSACK1
60
STERM
61
28A
BERR
28A
HALT
27A
CBREQ
Figure 14.
MOTOROLA
Synchronous Write Cycle Timing Diagram
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
31
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S4
S5
CLK
A31-A0
D31-D0
FC2-FC0
Freescale Semiconductor, Inc...
SIZ1-SIZ0
ECS
7
OCS
AS
DS
R/W
DBEN
16
DSACK0
DSACK1
33
37A
35
BR
34
BG
39
37
BGACK
39A
NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.
Figure 15.
32
Bus Arbitration Timing Diagram
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
CLK
6
8
IPEND
47A
CDIS
STATUS
62
63
Freescale Semiconductor, Inc...
REFILL
Figure 16.
MOTOROLA
Other Signal Timings
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
33
Freescale Semiconductor, Inc.
MECHANICAL DATA
PIN ASSIGNMENTS — PIN GRID ARRAY (RC SUFFIX)
N
D31
D28
D26
D25
D23
D21
D19
D18
D16
D15
D13
D11
D8
DBEN ECS
D29
D27
D24
D22
D20
D17
D14
D12
D9
D6
D3
CIIN SIZ0
R/W
D30
GND
VCC
GND
GND
GND
D10
D7
D4
D2
V CC
V CC
D5
D1
D0
M
L
K
CBREQ
DS
SIZ1
CBACK
AS
GND
J
GND STATUS REFILL
MC68EC030
Freescale Semiconductor, Inc...
H
BERR HALT VCC
V CC
CDIS IPL0
GND
IPL2 IPL1
G
BOTTOM
VIEW
STERM DSACK1 GND
F
DSACK0 V CC GND
V CC
RESET NC
E
CLK
AVEC GND
FC2
FC0 OCS
GND
NC IPEND
D
V CC
V CC
A6
A3
A2
C
FC1 CIOUT BGACK A1
GND
V CC
GND
A18
GND
A11
A9
A5
A4
B
RMC
BG
A31
A29
A27
A25
A22
A20
A16
A14
A12
A8
A7
A
BR
A0
A30
A28
A26
A24
A23
A21
A19
A17
A15
A13
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTE
The MC68030 has four additional guide pins not present on the
MC68EC030. Therefore, an MC68EC030 fits in a socket designed
for the MC68030, but the MC68030 does not necessary fit in a
socket intended for the MC68EC030.
The Vcc and GND pins are separated into three groups to provide individual power
supply connections for the address bus buffers, data bus buffers, and all other output
buffers and internal logic
Pin Group
Address Bus
Data Bus
ECS, SIZx, DS, AS, DBEN, CBREQ, R/W
FC0–FC2, RMS, OCS, CIOUT, BG
Internal Logic, RESET, STATUS, REFILL,
Misc
34
VCC
C6, D10
L6, K10
K4
D4
H3, F2, F11, H11
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
GND
C5, C7, C9, E11
J11, L9, L7, L5
J3
E3
L8, G3, F3, G11
MOTOROLA
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
K
MC68EC030
RP SUFFIX PACKAGE
CASE 789F-01
X
T
V
G
M
N
M
L
K
J
H
G
F
E
D
C
B
A
Freescale Semiconductor, Inc...
A
1 2 3 4 5 6 7 8 9 10 11 12 13
L
B
C
G
D 124 PL
0.76 (0.030) M T A S
0.76 (0.030) M X
M T
0.17(0.007)
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
A
B
34.04
34.04
35.05
35.05
1.340
1.340
1.380
1.380
C
2.92
3.18
0.115
0.135
D
0.44
0.55
0.017
0.022
G
K
2.54 BSC
4.32
4.95
L
1.02
1.52
0.040
M
2.79
3.81
0.110
0.150
1.200 BSC
V
MOTOROLA
30.48 BSC
B S
0.100 BSC
0.195
0.170
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH
3. DIMENSION D INCLUDES LEAD FINISH.
0.060
MC68EC030 TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
35
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution: P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive Blakelands, Milton Keynes, MK14 5BP,
England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial
Estate, Tai Po, N.T., Hong Kong.
µ MOTOROLA
For More Information On This Product,
Go to: www.freescale.com