68HC08M6 HC08M68HC 8M68HC08M Freescale Semiconductor, Inc. MC68HC908AS60/D REV 1 MC68HC908AS60 Technical Data HCMOS Microcontroller Unit Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 33 Freescale Semiconductor, Inc... Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 61 Section 4. FLASH-1 Memory . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. FLASH-2 Memory . . . . . . . . . . . . . . . . . . . . . . 77 Section 6. EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Section 7. EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Section 8. Central Processor Unit (CPU) . . . . . . . . . . . 113 Section 9. System Integration Module (SIM) . . . . . . . . 133 Section 10. Clock Generator Module (CGM) . . . . . . . . . 155 Section 11. Configuration Register (CONFIG-1). . . . . . 181 Section 12. Break Module. . . . . . . . . . . . . . . . . . . . . . . . 185 Section 13. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 191 Section 14. Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . 203 Section 15. Low-Voltage Inhibit (LVI) Module . . . . . . . 209 Section 16. External Interrupt Module (IRQ) . . . . . . . . . 215 Section 17. Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . 223 MC68HC908AS60 — Rev. 1.0 Technical Data List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Sections Section 18. Serial Peripheral Interface (SPI). . . . . . . . . 259 Section 19. Modulo Timer (TIM) . . . . . . . . . . . . . . . . . . . 291 Section 20. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 301 Section 21. Byte Data Link Controller-Digital (BDLC-D) . . . . . . . . . . . 327 Freescale Semiconductor, Inc... Section 22. Timer Interface Module A (TIMA-6) . . . . . . 375 Section 23. Analog-to-Digital Converter (ADC-15) . . . . 407 Section 24. Electrical Specifications. . . . . . . . . . . . . . . 419 Section 25. Mechanical Specifications . . . . . . . . . . . . . 433 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 437 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Technical Data MC68HC908AS60 — Rev. 1.0 List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Table of Contents Freescale Semiconductor, Inc... Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . .39 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40 1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 40 1.5.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 41 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . . 41 1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . 41 1.5.10 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.11 Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . . . 41 1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . 41 1.5.13 Port F I/O Pins (PTF7–PTF0/TACH2) . . . . . . . . . . . . . . . . . 42 1.5.14 Port G I/O Pins (PTG2–PTG0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.15 Port H I/O Pins (PTH1–PTH0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.16 BDLC Transmit Pin (BDTxD) . . . . . . . . . . . . . . . . . . . . . . . .42 1.5.17 BDLC Receive Pin (BDRxD) . . . . . . . . . . . . . . . . . . . . . . . .42 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Section 2. Memory Map 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Freescale Semiconductor, Inc... Section 3. Random-Access Memory (RAM) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 4. FLASH-1 Memory 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 67 4.6 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 68 4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8.1 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 72 4.8.2 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 73 4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Section 5. FLASH-2 Memory 5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents 5.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.5 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 81 5.6 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 82 5.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 5.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Section 6. EEPROM-1 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.1 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.3 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.4 EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.5 MCU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.4.6 EEPROM Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.4.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4.8 EEPROM Non-Volatile Register and EEPROM Array Configuration Register . . . . . . . . . 98 6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Section 7. EEPROM-2 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Freescale Semiconductor, Inc... 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.1 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.4.3 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . 106 7.4.4 EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . . 106 7.4.5 MCU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.4.6 MC68HC908AS60 EEPROM Protect. . . . . . . . . . . . . . . . . 107 7.4.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4.8 EEPROM Non-Volatile Register and EEPROM Array Control Register . . . . . . . . . . . . . 110 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Section 8. Central Processor Unit (CPU) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.2 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.3 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.4.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . 119 8.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 8.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Freescale Semiconductor, Inc... Section 9. System Integration Module (SIM) 9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 137 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 137 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 138 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 139 9.4.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 141 9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .142 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 142 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 143 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 143 9.6 Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 147 9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 9.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 154 Freescale Semiconductor, Inc... Section 10. Clock Generator Module (CGM) 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . 159 10.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .161 10.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . 161 10.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . 165 10.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 165 10.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .167 10.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 167 10.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 167 10.5.4 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 168 10.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .168 10.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 168 10.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 168 10.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 171 10.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 10.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 175 Freescale Semiconductor, Inc... 10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 176 10.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . 176 10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .177 10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 178 Section 11. Configuration Register (CONFIG-1) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Section 12. Break Module 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 187 12.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .187 12.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .188 12.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 12.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.6.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . .189 12.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 190 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Section 13. Monitor ROM (MON) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Freescale Semiconductor, Inc... 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 13.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 13.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 13.4.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Section 14. Computer Operating Properly (COP) Module 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 14.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 14.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 14.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.7 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.8 COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 14.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 14.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .208 Freescale Semiconductor, Inc... Section 15. Low-Voltage Inhibit (LVI) Module 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 15.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 15.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 15.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 15.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 15.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Section 16. External Interrupt Module (IRQ) 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 16.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 220 16.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 220 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Section 17. Serial Communications Interface (SCI) 17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Freescale Semiconductor, Inc... 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 17.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 17.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .231 17.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 231 17.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 17.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 241 17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.8.1 PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . 241 17.8.2 PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . 242 17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 17.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 17.9.5 17.9.6 17.9.7 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Freescale Semiconductor, Inc... Section 18. Serial Peripheral Interface (SPI) 18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.4 Pin Name and Register Name Conventions . . . . . . . . . . . . . .261 18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 18.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 18.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .266 18.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 267 18.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 268 18.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 269 18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 18.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 276 18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 280 18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 280 18.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 18.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18.13.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 285 18.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Freescale Semiconductor, Inc... Section 19. Modulo Timer (TIM) 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.5 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 19.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 295 19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 19.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 296 19.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 19.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 299 Section 20. Input/Output (I/O) Ports 20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 20.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 20.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 307 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 20.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 20.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 20.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 309 Freescale Semiconductor, Inc... 20.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 312 20.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.8.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 20.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 20.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . 321 20.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 20.10.1 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 20.10.2 Data Direction Register H. . . . . . . . . . . . . . . . . . . . . . . . . . 324 Section 21. Byte Data Link Controller-Digital (BDLC-D) 21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 21.4.1 BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 21.4.1.1 Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 21.4.1.2 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 21.4.1.3 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.6 Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 334 21.4.1.7 Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 334 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... 21.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 21.5.1 Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 21.5.1.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 21.5.1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 21.5.2 J1850 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 21.5.2.1 Start-of-Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . . 337 21.5.2.2 In-Message Data Bytes (Data). . . . . . . . . . . . . . . . . . . . 338 21.5.2.3 Cyclical Redundancy Check Byte (CRC) . . . . . . . . . . . . 338 21.5.2.4 End-of-Data Symbol (EOD) . . . . . . . . . . . . . . . . . . . . . . 339 21.5.2.5 In-Frame Response Bytes (IFR) . . . . . . . . . . . . . . . . . .339 21.5.2.6 End-of-Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . . 340 21.5.2.7 Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . . 340 21.5.2.8 Break (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.2.9 Idle Bus (IDLE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.3 J1850 VPW Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.3.1 Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 21.5.3.2 Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 21.5.3.3 Normalization Bit (NB) . . . . . . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.4 Break Signal (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.5 Start-of-Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . . 344 21.5.3.6 End-of-Data Symbol (EOD) . . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.7 End-of-Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.8 Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . . 344 21.5.3.9 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 21.5.4 J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . . . 345 21.5.4.1 Invalid Passive Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.5.4.2 Valid Passive Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.5.4.3 Valid Passive Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.4 Valid EOD Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.5 Valid EOF and IFS Symbols . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.6 Idle Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 21.5.4.7 Invalid Active Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.8 Valid Active Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.9 Valid Active Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.10 Valid SOF Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.5.4.11 Valid BREAK Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.5.5 Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.6.1 Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 21.6.2 Rx and Tx Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 352 21.6.3 Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . . .353 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... 21.6.4 Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .353 21.6.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.6.5.1 4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 21.6.5.2 Receiving a Message in Block Mode . . . . . . . . . . . . . . . 354 21.6.5.3 Transmitting a Message in Block Mode . . . . . . . . . . . . . 354 21.6.5.4 J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.6.5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 21.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 21.7.1 BDLC Analog and Roundtrip Delay . . . . . . . . . . . . . . . . . .358 21.7.2 BDLC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.7.3 BDLC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.7.4 BDLC State Vector Register. . . . . . . . . . . . . . . . . . . . . . . . 370 21.7.5 BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 Section 22. Timer Interface Module A (TIMA-6) 22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 22.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 380 22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 22.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 22.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 382 22.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .383 22.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 385 22.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 386 22.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 387 22.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 22.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 22.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 391 22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 22.8.1 TIMA Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . 392 22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0). . . . . . . . . . . . . . . . . 392 Freescale Semiconductor, Inc... 22.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 22.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . 393 22.9.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 395 22.9.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 396 22.9.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 397 22.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Section 23. Analog-to-Digital Converter (ADC-15) 23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 23.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 23.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 23.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 23.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412 23.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 23.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH). . . . . . . . . . . . . . . . . . .412 23.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . 412 23.7.3 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 412 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents 23.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 23.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 413 23.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 23.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 416 Freescale Semiconductor, Inc... Section 24. Electrical Specifications 24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 24.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 24.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 421 24.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 24.5 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .422 24.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 24.7 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 24.8 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . 425 24.9 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 428 24.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . 428 24.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 429 24.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 429 24.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 24.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 431 24.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . 431 Section 25. Mechanical Specifications 25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 25.3 52-Pin Plastic Leaded Chip Carrier Package . . . . . . . . . . . . . 434 25.4 64-Pin Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 MC68HC908AS60 — Rev. 1.0 Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Section 26. Ordering Information 26.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 26.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 26.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 Index Freescale Semiconductor, Inc... Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Technical Data MC68HC908AS60 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 List of Figures Freescale Semiconductor, Inc... Figure Title Page 1-1 1-2 1-3 1-4 MCU Block Diagram for the MC68HC08ASxx Emulator . . . . .36 MC68HC908AS60 (52-Pin PLCC) . . . . . . . . . . . . . . . . . . . . . . 37 MC68HC908AS60 (64-Pin QFP) . . . . . . . . . . . . . . . . . . . . . . . 38 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 51 4-1 4-2 4-3 4-4 FLASH-1 Control Register (FLCR1) . . . . . . . . . . . . . . . . . . . . . 65 Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH-1 Block Protect Register (FLBPR1) . . . . . . . . . . . . . . .72 FLASH-2 Block Protect Register (FLBPR2) . . . . . . . . . . . . . . .73 5-1 5-2 FLASH-2 Control Register (FLCR2) . . . . . . . . . . . . . . . . . . . . . 79 Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 85 6-1 6-2 6-3 EEPROM-1 Control Register (EECR1). . . . . . . . . . . . . . . . . . . 96 EEPROM-1 Non-Volatile Register (EENVR1) . . . . . . . . . . . . . 98 EEPROM-1 Array Control Register (EEACR1). . . . . . . . . . . . . 98 7-1 7-2 7-3 EEPROM-2 Control Register (EECR2). . . . . . . . . . . . . . . . . . 108 EEPROM-2 Non-Volatile Register (EENVR2) . . . . . . . . . . . . 110 EEPROM-2 Array Control Register (EEACR2). . . . . . . . . . . . 110 8-1 8-2 8-3 8-4 8-5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 MC68HC908AS60 — Rev. 1.0 Technical Data List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... Figure Title Page 8-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . .119 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 147 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 149 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 149 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 150 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 151 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 153 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 154 10-1 10-2 10-3 10-4 10-5 10-6 CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 167 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 169 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 171 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . 173 11-1 Configuration Write-Once Register (CONFIG-1) . . . . . . . . . . 182 12-1 12-2 12-3 12-4 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 186 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Break Status and Control Register (BSCR) . . . . . . . . . . . . . . 189 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . . 190 Technical Data MC68HC908AS60 — Rev. 1.0 List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... Figure Title Page 13-1 13-2 13-3 13-4 13-5 13-6 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14-1 14-2 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 207 15-1 15-2 15-3 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16-1 16-2 16-3 16-4 IRQ Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 217 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 220 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 232 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 243 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 246 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 248 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 250 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 253 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 255 MC68HC908AS60 — Rev. 1.0 Technical Data List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... Figure Title Page 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 264 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 267 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 268 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 270 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 271 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 272 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 275 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 276 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 283 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . 286 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19-1 19-2 19-3 19-4 19-5 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 296 TIM Counter Registers (TCNTH–TCNTL) . . . . . . . . . . . . . . . 298 TIM Counter Modulo Registers (TMODH–TMODL) . . . . . . . . 299 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 304 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 307 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 309 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 312 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 316 Technical Data MC68HC908AS60 — Rev. 1.0 List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... Figure Title Page 20-16 20-17 20-18 20-19 20-20 20-21 20-22 20-23 20-24 20-25 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 319 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . . 321 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . . 324 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 21-17 21-18 21-19 21-20 21-21 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 BDLC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 331 BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . . 332 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . .335 J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . . . 338 J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . .343 J1850 VPW Received Passive Symbol Times . . . . . . . . . . . . 346 J1850 VPW Received Passive EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . . .347 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . . 348 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . . 349 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . .350 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . . .352 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 BDLC Analog and Roundtrip Delay Register (BARD) . . . . . . 358 BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . . . . 359 BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . . . . 362 Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . 366 BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . . . 370 BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 372 22-1 22-2 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 378 MC68HC908AS60 — Rev. 1.0 Technical Data List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Figures Figure Title Page Freescale Semiconductor, Inc... 22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 385 22-4 Timer A Status and Control Register (TASC) . . . . . . . . . . . . . 393 22-5 TIMA Counter Registers (TCNTH and TCNTL) . . . . . . . . . . . 395 22-6 TIMA Counter Modulo Registers (TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . . . . 396 22-7 TIMA Channel Status and Control Registers (TACC0–TASC5) . . . . . . . . . . . . . .397 22-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 22-9 TIMA Channel Registers (TACH0H/L–TACH3H/L) . . . . . . . . 403 23-1 23-2 23-3 23-4 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . .413 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . . 416 24-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 426 24-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 24-3 BDLC Variable Pulse-Width Modulation (VPW) Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Technical Data MC68HC908AS60 — Rev. 1.0 List of Figures For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 List of Tables Freescale Semiconductor, Inc... Table Title Page 1-1 1-2 External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4-1 4-2 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . .67 Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5-1 5-2 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . .81 Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6-1 6-2 6-3 EEPROM Program/Erase Cycling Reduction . . . . . . . . . . . . . . 93 EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . .94 EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . . 97 7-1 7-2 7-3 EEPROM Program/Erase Cycling Reduction . . . . . . . . . . . . . 105 EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . .106 EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . 109 8-1 8-2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9-1 9-2 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10-1 10-2 Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . . 173 11-1 COP Time Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 MC68HC908AS60 — Rev. 1.0 Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... Table Title Page 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 197 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 197 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 198 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 198 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 198 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .199 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 199 15-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 257 18-1 18-2 18-3 18-4 18-5 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 288 19-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 20-1 20-2 20-3 20-4 20-5 20-6 20-7 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Technical Data MC68HC908AS60 — Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Tables Table Freescale Semiconductor, Inc... 20-8 21-1 21-2 21-3 21-4 Title Page 21-5 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . . . 356 BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 BDLC Transmit In-Frame Response Control Bit Priority Encoding . . . . . . . . . . . . . . . . . . . . . . .365 BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22-1 22-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 401 23-1 23-2 26-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 MC68HC908AS60 — Rev. 1.0 Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... List of Tables Technical Data MC68HC908AS60 — Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 1. General Description Freescale Semiconductor, Inc... 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . .39 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40 1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 40 1.5.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 41 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . . 41 1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . 41 1.5.10 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.11 Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . . . 41 1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . 41 1.5.13 Port F I/O Pins (PTF7–PTF0/TACH2) . . . . . . . . . . . . . . . . . 42 1.5.14 Port G I/O Pins (PTG2–PTG0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.15 Port H I/O Pins (PTH1–PTH0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.16 BDLC Transmit Pin (BDTxD) . . . . . . . . . . . . . . . . . . . . . . . .42 1.5.17 BDLC Receive Pin (BDRxD) . . . . . . . . . . . . . . . . . . . . . . . .42 MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description 1.2 Introduction The MC68HC908AS60 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Freescale Semiconductor, Inc... This part is designed to emulate the M68HC08ASxx automotive family. NOTE: The MC68HC908AS60 offers extra features which are not available on the MC68HC08AS20 and MC68HC908AS32 devices. It is the user’s responsibility to ensure compatibility between the features used on the MC68HC908AS60 and those which are available on the device which will ultimately be used in the application. 1.3 Features Features of the MC68HC908AS60 include: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • 8.4-MHz internal bus frequency • 60 Kbytes of FLASH electrically erasable read-only memory (FLASH) • FLASH data security(1) • 1 Kbyte of on-chip electrically erasable programmable read-only memory (EEPROM) with security option • 2 Kbytes of on-chip random-access memory (RAM) • Clock generator module (CGM) • Serial peripheral interface module (SPI) 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH/EEPROM difficult for unauthorized users. Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description MCU Block Diagram • Serial communications interface module (SCI) • 8-bit, 15-channel analog-to-digital converter (ADC-15) • 16-bit, 6-channel timer interface module (TIMA-6) • Modulo timer (TIM) • SAE J1850 byte data link controller digital module (BDLC-D) • System protection features: Freescale Semiconductor, Inc... – Computer operating properly (COP) with optional reset – Low-voltage detection with optional reset – Illegal opcode detection with optional reset – Illegal address detection with optional reset • Low-power design with stop and wait modes • Master reset pin and power-on reset Features of the CPU08 include: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the M68HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • C language support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AS60. MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com ARITHMETIC/LOGIC UNIT (ALU) Technical Data General Description For More Information On This Product, Go to: www.freescale.com POWER BYTE DATA LINK CONTROLLER PTF5 PTF4 PTF3/TACH5 PTF2 /TACH4 PTF1/TACH3 PTF0/TACH2 PTH1* PTH0* PTG2* PTG1* PTG0* PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12 PTD3/ATD11 PTD2/ATD10 PTD1/ATD9–PTD0/ATD8 PTC5–PTC3 PTC2/MCLK PTC1–PTC0 PTA7–PTA0 PTB7/ATD7–PTB0/ATD0 Figure 1-1. MCU Block Diagram for the MC68HC08ASxx Emulator * PTG and PTH pins are available only in 64-pin quad flat packs (QFP). VSS VDD VDDAREF/ VDDA VSSA/VREFL POWER-ON RESET MODULE IRQ MODULE SERIAL PERIPHERAL INTERFACE MODULE SYSTEM INTEGRATION MODULE RST IRQ SERIAL COMMUNICATIONS INTERFACE MODULE CLOCK GENERATOR MODULE OSC1 OSC2 CGMXFC MODULO TIMER USER FLASH VECTOR SPACE — 38 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE BREAK MODULE ANALOG-TO-DIGITAL MODULE TIMER A 6 CHANNEL INTERFACE MODULE VREFH MONITOR ROM — 224 BYTES USER EEPROM — 1 KBYTE USER RAM — 2 KBYTES USER FLASH — 60 KBYTES CONTROL AND STATUS REGISTERS — 62 BYTES CPU REGISTERS BDRxD DDRD DDRE DDRF DDRG M68HC08 CPU BDTxD PTA DDRB DDRA PTB PTC DDRC PTD PTE PTF PTG PTH DDRH Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description MC68HC908AS60 — Rev. 1.0 Freescale Semiconductor, Inc. General Description Pin Assignments 1.5 Pin Assignments VDDA/VDDAREF VREFH PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12 50 49 48 47 OSC2 2 51 OSC1 3 VSSA/VREFL PTC0 4 52 PTC1 5 CGMXFC PTC2/MCLK 6 1 PTC3 7 14 40 PTB5/ATD5 BDRxD 15 39 PTB4/ATD4 BDTxD 16 38 PTB3/ATD3 PTE0/TxD 17 37 PTB2/ATD2 PTE1/RxD 18 36 PTB1/ATD1 PTE2/TACH0 19 35 PTB0/ATD0 PTE3/TACH1 20 34 PTA7 33 PTF3/TACH5 PTA6 PTB6/ATD6 32 41 PTA5 13 31 PTF2/TACH4 PTA4 PTB7/ATD7 30 42 PTA3 12 29 PTF1/TACH3 PTA2 PTD0/ATD8 28 43 PTA1 11 27 PTF0/TACH2 PTA0 PTD1/ATD9 26 44 VDD 10 25 RST VSS PTD2/ATD10 24 45 PTE7/SPSCK 9 23 IRQ PTE6/MOSI PTD3/ATD11 22 46 PTE5/MISO 8 21 PTC4 PTE4/SS Freescale Semiconductor, Inc... Figure 1-2 shows the MC68HC908AS60 pin assignments for the 52-pin plastic leaded chip carrier (PLCC) package. Figure 1-2. MC68HC908AS60 (52-Pin PLCC) MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description PTC2/MCLK PTC1 PTC0 OSC1 OSC2 CGMXFC VSSA VDDA VREFH PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12 62 61 60 59 58 57 56 55 54 53 52 51 50 1 49 PTH1 PTC3 63 PTC4 48 PTH0 BDRxD 9 40 PTB6/ATD6 BDTxD 10 39 PTB5/ATD5 PTF5 11 38 PTB4/ATD4 PTF6 12 37 PTB3/ATD3 PTE0/TxD 13 36 PTB2/ATD2 PTE1/RxD 14 35 PTB1/ATD1 PTE2/TACH0 15 34 PTB0/ATD0 16 33 PTA7 PTA6 32 PTE3/TACH1 31 PTB7/ATD7 PTA5 41 30 8 PTA4 PTF4 29 PTD0/ATD8 PTA3 42 28 7 PTA2 PTF3/TACH5 27 PTD1/ATD9 PTA1 43 26 6 PTA0 PTF2/TACH4 25 VDDAREF PTG2 44 24 5 PTG1 PTF1/TACH3 23 AVSS /V REFL PTG0 45 22 4 VDD PTF0/TACH2 21 PTD2/ATD10 V SS 46 20 3 PTE7/SPSCK RST 19 PTD3/ATD11 PTE6/MOSI 47 18 2 PTE5/MISO IRQ PTE4/SS 17 Freescale Semiconductor, Inc... 64 PTC5 Figure 1-3 shows the pin assignments for the MC68HC908AS60 64-pin quad flat pack (QFP) package. Figure 1-3. MC68HC908AS60 (64-Pin QFP) NOTE: The following pin descriptions are for quick reference only. For a more detailed representation, see Section 20. Input/Output (I/O) Ports. Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Pin Assignments 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Freescale Semiconductor, Inc... Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure 1-4. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MCU VDD VSS C1 0.1 µF + C2 VDD Note: Component values shown represent typical applications. Figure 1-4. Power Supply Bypassing VSS is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (SPI). See Section 18. Serial Peripheral Interface (SPI). NOTE: VSS must be grounded for proper MCU operation. MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description 1.5.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Section 10. Clock Generator Module (CGM). Freescale Semiconductor, Inc... 1.5.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See Section 9. System Integration Module (SIM) for more information. 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. See Section 16. External Interrupt Module (IRQ). 1.5.5 Analog Power Supply Pin (VDDA) VDDA is the power supply pin for the analog portion of the chip. This pin will supply both the clock generator module (CGM) and the analog-to-digital converter (ADC). See Section 10. Clock Generator Module (CGM), and Section 23. Analog-to-Digital Converter (ADC-15). 1.5.6 Analog Ground Pin (VSSA) The VSSA analog ground pin is used only for the ground connections for the analog sections of the circuit and should be decoupled as per the VSS digital ground pin. The analog sections consist of a clock generator module (CGM) and an analog-to-digital converter (ADC). See Section 10. Clock Generator Module (CGM) and Section 23. Analog-to-Digital Converter (ADC-15). Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Pin Assignments 1.5.7 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Section 23. Analog-to-Digital Converter (ADC-15). 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) Freescale Semiconductor, Inc... PTA7–PTA0 are general-purpose bidirectional input/output (I/O) port pins. See Section 20. Input/Output (I/O) Ports. 1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) Port B is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (ADC). See Section 23. Analog-to-Digital Converter (ADC-15), and Section 20. Input/Output (I/O) Ports. 1.5.10 Port C I/O Pins (PTC5–PTC0) PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special function port that shares its pin with the system clock which has a frequency equivalent to the system clock. See Section 20. Input/Output (I/O) Ports. 1.5.11 Port D I/O Pins (PTD7–PTD0/ATD8) Port D is an 8-bit special-function port that shares seven of its pins with the analog-to-digital converter module (ADC-15) and one of its pins with the timer interface module (TIMA). See Section 22. Timer Interface Module A (TIMA-6), Section 23. Analog-to-Digital Converter (ADC-15), and Section 20. Input/Output (I/O) Ports. 1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), four of its pins with the serial peripheral interface module (SPI), and two of its pins with the serial communication interface module (SCI). See Section 17. Serial Communications MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Interface (SCI), Section 18. Serial Peripheral Interface (SPI), Section 22. Timer Interface Module A (TIMA-6), and Section 20. Input/Output (I/O) Ports. 1.5.13 Port F I/O Pins (PTF7–PTF0/TACH2) Freescale Semiconductor, Inc... Port F is a 7-bit special function port that shares six of its pins with the timer interface module (TIMA-6). See Section 22. Timer Interface Module A (TIMA-6) and Section 20. Input/Output (I/O) Ports. 1.5.14 Port G I/O Pins (PTG2–PTG0) Port G is a 3-bit, general-purpose, bidirectional I/O port. 1.5.15 Port H I/O Pins (PTH1–PTH0) Port H is a 2-bit, general-purpose, bidirectional I/O port. NOTE: Port G and Port H I/O pins are available only in the 64-pin QFP. 1.5.16 BDLC Transmit Pin (BDTxD) This pin is the serial digital output from the BDLC module (BDTxD). See Section 21. Byte Data Link Controller-Digital (BDLC-D). 1.5.17 BDLC Receive Pin (BDRxD) This pin is the serial digital input to the BDLC module (BDRxD). See Section 21. Byte Data Link Controller-Digital (BDLC-D). Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Pin Assignments Table 1-1. External Pins Summary Freescale Semiconductor, Inc... Pin Name Function Driver Type Hysteresis Reset State PTA7–PTA0 General-purpose I/O Dual state No Input Hi-Z PTB7/ATD7–PTB0/ATD0 General-purpose I/O ADC channel Dual state No Input Hi-Z PTC5–PTC0 PTC5 available in 64-pin package only General-purpose I/O Dual state No Input Hi-Z PTD7 Available in 64-pin package only General-purpose I/O Dual state No Input Hi-Z PTD6/ATD14/TACLK ADC channel General-purpose I/O ADC channel/timer external input clock Dual state No Input Hi-Z PTD5/ATD13 ADC channel General-purpose I/O ADC channel Dual state No Input Hi-Z PTD4/ATD12/TBCLK ADC channel TBCLK for 64-pin package only General-purpose I/O ADC channel/timer external input clock Dual state No Input Hi-Z PTD3/ATD11–PTD0/ATD8 ADC channel General-purpose I/O ADC channel Dual state No Input Hi-Z PTE7/SPSCK General-purpose I/O SPI clock Dual state open drain Yes Input Hi-Z PTE6/MOSI General-purpose I/O SPI data path Dual state open drain Yes Input Hi-Z PTE5/MISO General-purpose I/O SPI data path Dual state open drain Yes Input Hi-Z PTE4/SS General-purpose I/O SPI slave select Dual state Yes Input Hi-Z PTE3/TACH1 General-purpose I/O timer channel 1 Dual state Yes Input Hi-Z PTE2/TACH0 General-purpose I/O timer channel 0 Dual state Yes Input Hi-Z PTE1/RxD General-purpose I/O SCI receive data Dual state Yes Input Hi-Z PTE0/TxD General-purpose I/O SCI transmit data Dual state No Input Hi-Z PTF6 Available in 64-pin package only General-purpose I/O Dual state No Input Hi-Z PTF5/TBCH1–PTF4/TBCH0 Available in 64-pin package only General-purpose I/O timer B channel Dual state Yes Input Hi-Z MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Table 1-1. External Pins Summary (Continued) Freescale Semiconductor, Inc... Pin Name Function Driver Type Hysteresis Reset State PTF3/TACH5 General-purpose I/O timer A channel 5 Dual state Yes Input Hi-Z PTF2/TACH4 General-purpose I/O timer A channel 4 Dual state Yes Input Hi-Z PTF1/TACH3 General-purpose I/O timer A channel 3 Dual state Yes Input Hi-Z PTF0/TACH2 General-purpose I/O timer A channel 2 Dual state Yes Input Hi-Z PTG2–PTG0 Available in 64-pin package only General-purpose I/O Dual state Yes Input Hi-Z PTH1–PTH0 Available in 64-pin package only General-purpose I/O Dual state Yes Input Hi-Z VDD Chip power supply N/A N/A N/A VSS Chip ground N/A N/A N/A VDDA/VDDAREF ADC reference voltage for 52-pin package only Analog power supply N/A N/A N/A VSSA/VREFL VREFL Available in 52-pin package only Analog ground/ADC reference voltage N/A N/A N/A AVDD/VDDAREF Available in 64-pin package only ADC power supply/ ADC reference voltage N/A N/A N/A AVSS/VREFL Available in 64-pin package only ADC ground/ADC reference voltage N/A N/A N/A VREFH A/D reference voltage N/A N/A N/A OSC1 External clock in N/A N/A Input Hi-Z OSC2 External clock out N/A N/A Output PLL filter cap N/A N/A N/A IRQ External interrupt request N/A N/A Input Hi-Z RST Reset N/A N/A Output low BDRxD BDLC-D serial input N/A No Input Hi-Z BDTxD BDLC-D serial output Output No Output low CGMXFC Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Pin Assignments Freescale Semiconductor, Inc... Table 1-2. Clock Source Summary Module Clock Source ADC CGMXCLK or bus clock BDLC CGMXCLK COP CGMXCLK CPU Bus clock EEPROM RC OSC or bus clock SPI Bus clock/SPSCK SCI CGMXCLK TIMA-6 Bus clock or PTD6/ATD14/TACLK TIM Bus clock SIM CGMOUT and CGMXCLK IRQ Bus clock BRK Bus clock LVI Bus clock CGM OSC1 and OSC2 MC68HC908AS60 — Rev. 1.0 Technical Data General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... General Description Technical Data MC68HC908AS60 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 2. Memory Map Freescale Semiconductor, Inc... 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 60 Kbytes of FLASH EEPROM • 2048 bytes of RAM • 1024 bytes of EEPROM with protect option • 38 bytes of user-defined vectors • 224 bytes of monitor ROM These definitions apply to the memory map representation of reserved and unimplemented locations. • Reserved — Accessing a reserved location can have unpredictable effects on MCU operation. • Unimplemented — Accessing an unimplemented location causes an illegal address reset. MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Freescale Semiconductor, Inc... $0000 ↓ $003F $0040 ↓ $004A $004B $004F $0050 ↓ $044F $0450 ↓ $05FF $0600 ↓ $07FF $0800 ↓ $09FF $0A00 ↓ $0DFF $0E00 ↓ $7FFF $8000 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A I/O REGISTERS 64 BYTES UNIMPLEMENTED 11 BYTES I/O REGISTERS 5 BYTES RAM-1 1024 BYTES FLASH-2 432 BYTES EEPROM-2 512 BYTES EEPROM-1 512 BYTES RAM-2 1024 BYTES FLASH-2 29,184 BYTES FLASH-1 32,256 BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR) RESERVED RESERVED UNIMPLEMENTED RESERVED RESERVED RESERVED RESERVED $0000 ↓ $003F $0040 ↓ $004A $004B $004F $0050 ↓ $044F $0450 ↓ $05FF $0600 ↓ $07FF $0800 ↓ $09FF $0A00 ↓ $0DFF $0E00 ↓ $7FFF $8000 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A Figure 2-1. Memory Map Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Introduction Freescale Semiconductor, Inc... $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 ↓ $FE17 $FE18 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 ↓ $FEFF $FF00 ↓ $FF7F $FF80 $FF81 $FF82 ↓ $FFCB $FFCC ↓ $FFD9 $FFDA ↓ $FFFF FLASH CONTROL REGISTER (FLCR1) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BSCR) LVI STATUS REGISTER (LVISR) RESERVED FLASH CONTROL REGISTER (FLCR2) UNIMPLEMENTED 6 BYTES EEPROM NON-VOLATILE REGISTER (EENVR2) EEPROM CONTROL REGISTER (EECR2) RESERVED EEPROM ARRAY CONFIGURATION (EEACR2) EEPROM NON-VOLATILE REGISTER (EENVR1) EEPROM CONTROL REGISTER (EECR1) RESERVED EEPROM ARRAY CONFIGURATION (EEACR1) MONITOR ROM 224 BYTES UNIMPLEMENTED 128 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR1) FLASH BLOCK PROTECT REGISTER (FLBPR2) RESERVED 74 BYTES RESERVED 14 BYTES VECTORS 38 BYTES $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 ↓ $FE17 $FE18 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 ↓ $FEFF $FF00 ↓ $FF7F $FF80 $FF81 $FF82 ↓ $FFCB $FFCC ↓ $FFD9 $FFDA ↓ $FFFF Figure 2-1. Memory Map (Continued) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map 2.3 Input/Output Section Freescale Semiconductor, Inc... Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional input/output (I/O) registers have these addresses: • $FE00 — SIM break status register, SBSR • $FE01 — SIM reset status register, SRSR • $FE03 — SIM break flag control register, SBFCR • $FE0B — FLASH control register, FLCR1 • $FE0C — Break address register high, BRKH • $FE0D — Break address register low, BRKL • $FE0E — Break status and control register, BRKSCR • $FE0F — LVI status register, LVISR • $FE11 — FLASH control register, FLCR2 • $FE18 — EEPROM non-volatile register, EENVR2 • $FE19 — EEPROM control register, EECR2 • $FE1B — EEPROM array configuration register, EEACR2 • $FE1C — EEPROM non-volatile register, EENVR1 • $FE1D — EEPROM control register, EECR1 • $FE1F — EEPROM array configuration register, EEACR1 • $FF80 — FLASH block protect register, FLBPR1 • $FF81 — FLASH block protect register, FLBPR2 • $FFFF — COP control register, COPCTL Table 2-1 is a list of vector locations. Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Input/Output Section Addr. $0000 $0001 Freescale Semiconductor, Inc... $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 Register Name Read: Port A Data Register (PTA) Write: See page 304. Reset: Read: Port B Data Register (PTB) Write: See page 306. Reset: Read: Port C Data Register (PTC) Write: See page 308. Reset: Read: Port D Data Register (PTD) Write: See page 311. Reset: Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTC2 PTC1 PTC0 PTD2 PTD1 PTD0 DDRA2 DDRA1 DDRA0 Unaffected by reset PTB7 0 0 R R PTB4 PTB3 PTC5 PTC4 PTC3 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset Read: Data Direction Register B DDRB7 (DDRB) Write: See page 307. Reset: 0 Read: Data Direction Register C MCLKEN (DDRC) Write: See page 309. Reset: 0 Read: Data Direction Register D DDRD7 (DDRD) Write: See page 312. Reset: 0 Port F Data Register Read: (PTF) Write: See page 318. Reset: PTB5 Unaffected by reset Read: Data Direction Register A DDRA7 (DDRA) Write: See page 304. Reset: Read: Port E Data Register (PTE) Write: See page 314. Reset: PTB6 PTE7 DDRA6 DDRA5 DDRA4 DDRA3 Unaffected by reset DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 0 0 0 0 0 0 0 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 PTF2 PTF1 PTF0 0 R Unaffected by reset 0 R PTF6 PTF5 PTF4 PTF3 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Addr. Register Name $000A Read: Port G Data Register (PTG) Write: See page 320. Reset: $000B Freescale Semiconductor, Inc... $000C $000D $000E $000F Read: Port H Data Register (PTH) Write: See page 323. Reset: Bit 7 6 5 4 3 0 0 0 0 0 R R R R R Read: Data Direction Register G (DDRG) Write: See page 321. Reset: Read: Data Direction Register H (DDRH) Write: See page 324. Reset: $0010 $0011 $0012 $0013 Read: SPI Data Register (SPDR) Write: See page 289. Reset: Bit 0 PTG2 PTG1 PTG0 PTH1 PTH0 0 0 0 0 0 0 R R R R R R Unaffected by reset DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R DDRG2 DDRG1 DDRG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R DDRH1 DDRH0 0 0 0 0 0 0 0 0 R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 1 0 1 0 0 0 OVRF MODF SPTE R R R MODFEN SPR1 SPR0 0 R Read: SPI Control Register SPRIE (SPCR) Write: See page 283. Reset: 0 Read: SPI Status and Control Register (SPSCR) Write: See page 286. Reset: 1 Unaffected by reset Read: Data Direction Register E DDRE7 (DDRE) Write: See page 316. Reset: 0 Read: Data Direction Register F (DDRF) Write: See page 319. Reset: 2 SPRF R ERRIE 0 0 0 0 1 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 Read: SCI Control Register 1 LOOPS (SCC1) Write: See page 243. Reset: 0 Indeterminate after reset ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9) Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Input/Output Section Addr. $0014 $0015 Freescale Semiconductor, Inc... $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E Register Name Read: SCI Control Register 2 (SCC2) Write: See page 246. Reset: Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 T8 R R ORIE NEIE FEIE PEIE Read: SCI Control Register 3 (SCC3) Write: See page 248. Reset: R8 U U 0 0 0 0 0 0 Read: SCI Status Register 1 (SCS1) Write: See page 250. Reset: SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 BKF RPF Read: SCI Status Register 2 (SCS2) Write: See page 253. Reset: Read: SCI Data Register (SCDR) Write: See page 254. Reset: Read: SCI Baud Rate Register (SCBR) Write: See page 255. Reset: Read: IRQ Status and Control Register (ISCR) Write: See page 220. Reset: 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 Unaffected by reset SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 IMASK1 MODE1 0 0 0 0 0 0 0 0 0 0 IRQF1 0 R R R R R ACK1 0 0 0 0 0 0 0 0 PLLON BCS 1 1 1 1 1 0 1 1 1 1 ACQ XLD 0 0 0 0 Unimplemented PLL Control Register Read: (PCTL) Write: See page 169. Reset: Read: PLL Bandwidth Control Register (PBWC) Write: See page 171. Reset: PLL Programming Register Read: (PPG) Write: See page 173. Reset: PLLIE 0 AUTO PLLF 0 LOCK 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Addr. $001F $0020 Register Name 6 5 4 3 2 1 Bit 0 R LVIRST LVIPWR SSREC COPL STOP COPD 1 1 1 0 0 0 0 TOIE TSTOP 0 0 TRST R PS2 PS1 PS0 0 0 1 0 0 0 0 0 Read: Timer A Counter Register High (TACNTH) Write: See page 395. Reset: Bit 15 14 13 12 11 10 9 Bit 8 R R R R R R R R 0 0 0 0 0 0 0 0 Timer A Counter Register Read: Low (TACNTL) Write: See page 395. Reset: Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Read: Configuration Write-Once LVISTOP Register (CONFIG-1) Write: See page 182. Reset: 0 Read: Timer A Status and Control Register (TASC) Write: See page 393. Reset: Freescale Semiconductor, Inc... $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 Bit 7 TOF 0 Unimplemented Read: Timer A Modulo Register High (TAMODH) Write: See page 396. Reset: Timer A Modulo Register Read: Low (TAMODL) Write: See page 396. Reset: Read: Timer A Channel 0 Status and Control Register (TASC0) Write: See page 397. Reset: Timer A Channel 0 Register Read: High (TACH0H) Write: See page 403. Reset: Read: Timer A Channel 0 Register Low (TACH0L) Write: See page 403. Reset: Timer A Channel 1 Status and Read: Control Register (TASC1) Write: See page 397. Reset: CH0F 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH1F 0 0 CH1IE 0 0 R 0 = Unimplemented MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9) Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Input/Output Section Addr. $002A $002B Freescale Semiconductor, Inc... $002C $002D $002E $002F $0030 $0031 $0032 $0033 Register Name Read: Timer A Channel 1 Register High (TACH1H) Write: See page 403. Reset: Read: Timer A Channel 1 Register Low (TACH1L) Write: See page 403. Reset: Read: Timer A Channel 2 Status and Control Register (TASC2) Write: See page 397. Reset: Read: Timer A Channel 2 Register High (TACH2H) Write: See page 403. Reset: Read: Timer A Channel 2 Register Low (TACH2L) Write: See page 403. Reset: Read: Timer A Channel 3 Status and Control Register (TASC3) Write: See page 397. Reset: Read: Timer A Channel 3 Register High (TACH3H) Write: See page 403. Reset: Read: Timer A Channel 3 Register Low (TACH3L) Write: See page 403. Reset: Read: Timer A Channel 4 Status and Control Register (TASC4) Write: See page 397. Reset: Read: Timer A Channel 4 Register High (TACH4H) Write: See page 403. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH3F 0 CH3IE 0 R MS3A ELS3B ELS3A TOV3 CH3MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH4F CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 0 Indeterminate after reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Addr. $0034 $0035 Freescale Semiconductor, Inc... $0036 $0037 $0038 $0039 $003A $003B $003C $003D Register Name Read: Timer A Channel 4 Register Low (TACH4L) Write: See page 403. Reset: Read: Timer A Channel 5 Status and Control Register (TASC5) Write: See page 397. Reset: Read: Timer A Channel 5 Register High (TACH5H) Write: See page 403. Reset: Read: Timer A Channel 5 Register Low (TACH5L) Write: See page 403. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Indeterminate after reset CH5F 0 Read: Analog-to-Digital Input Clock Register (ADICLK) Write: See page 416. Reset: Read: BDLC Analog and Roundtrip Delay Register (BARD) Write: See page 358. Reset: Read: BDLC Control Register 1 (BCR1) Write: See page 359. Reset: 0 R MS5A ELS5B ELS5A TOV5 CH5MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset Read: COCO Analog-to-Digital Status and Control Register (ADSCR) Write: R See page 413. Reset: 0 Read: Analog-to-Digital Data Register (ADR) Write: See page 416. Reset: CH5IE AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R 0 0 0 0 R R R R 0 0 0 0 BO3 BO2 BO1 BO0 0 1 1 1 0 0 R R IE WCM Indeterminate after reset ADIV2 ADIV1 ADIV0 ADICLK 0 0 0 0 ATE RXPOL 0 0 1 1 0 0 IMSG CLKS R1 R0 1 1 1 0 0 0 0 0 DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 1 0 0 0 0 0 0 Read: BDLC Control Register 2 ALOOP (BCR2) Write: See page 362. Reset: 1 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9) Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Input/Output Section Addr. $003E Freescale Semiconductor, Inc... $003F $0040 ↓ $004A $004B $004C $004D $004E $004F $FE00 Register Name Read: BDLC State Vector Register (BSVR) Write: See page 370. Reset: Read: BDLC Data Register (BDR) Write: See page 372. Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 PS2 PS1 PS0 Indeterminate after reset Unimplemented Read: TIM Status and Control Register (TSC) Write: See page 296. Reset: TOF 0 0 TOIE TSTOP 0 0 1 0 0 0 0 0 Read: TIM Counter Register High (TCNTH) Write: See page 298. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Read: TIM Counter Register Low (TCNTL) Write: See page 298. Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R R R R R R Read: TIM Modulo Register High (TMODH) Write: See page 299. Reset: Read: TIM Modulo Register Low (TMODL) Write: See page 299. Reset: Read: SIM Break Status Register (SBSR) Write: See page 151. Reset: 0 TRST SBSW See Note R 0 Note: Writing a logic 0 clears SBSW. $FE01 Read: SIM Reset Status Register (SRSR) Write: See page 153. Reset: POR PIN COP ILOP ILAD 0 LVI 0 1 0 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Addr. $FE03 Register Name Read: SIM Break Flag Control Register (SBFCR) Write: See page 154. Reset: $FE09 Freescale Semiconductor, Inc... $FE0B $FE0C $FE0D $FE0E Reserved Read: FLASH-1 Control Register (FLCR1) Write: See page 65. Reset: Read: Break Address Register High (BRKH) Write: See page 190. Reset: Break Address Register Low Read: (BRKL) Write: See page 190. Reset: Read: Break Status and Control Register (BSCR) Write: See page 189. Reset: $FE0F $FE11 $FE18 $FE19 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R R R R R FDIV1 FDIV0 BLK1 BLK0 HVEN 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDIV1 FDIV0 BLK1 BLK0 HVEN 0 0 0 0 0 EERA CON2 CON1 LVI Status Register Read: LVIOUT (LVISR) Write: See page 212. Reset: 0 Read: FLASH-2 Control Register (FLCR2) Write: See page 79. Reset: EEPROM-2 Non-volatile Read: Register (EENVR2) Write: See page 110. Reset: 0 R R MARGIN ERASE MARGIN ERASE EEPRTCT EEBP3 R PGM PGM 0 0 0 EEBP2 EEBP1 EEBP0 Programmed value or 1 in the erased state. Read: EEPROM-2 Control Register EEBCLK (EECR2) Write: See page 108. Reset: 0 0 0 0 0 0 0 0 0 Reserved R R R R R R R $FE1A R EEOFF = Unimplemented EERAS1 EERAS0 R EELAT = Reserved 0 EEPGM U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9) Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Input/Output Section Addr. $FE1B $FE1C Freescale Semiconductor, Inc... $FE1D $FE1E $FE1F $FF80 $FF81 $FFFF Register Name Read: EEPROM-2 Array Control Register (EEACR2) Write: See page 110. Reset: Read: EEPROM-1 Non-volatile Register (EENVR1) Write: See page 98. Reset: Bit 7 6 5 EERA CON2 CON1 4 3 EEPRTCT EEBP3 2 1 Bit 0 EEBP2 EEBP1 EEBP0 EEBP2 EEBP1 EEBP0 EENVR2 EERA CON2 CON1 EEPRTCT EEBP3 Programmed value or 1 in the erased state Read: EEPROM-1 Control Register EEBCLK (EECR1) Write: See page 96. Reset: 0 0 0 0 0 0 0 0 0 Reserved R R R R R R R R EERA CON2 CON1 EEBP2 EEBP1 EEBP0 BPR3 BPR2 BPR1 BPR0 0 0 0 0 BPR3 BPR2 BPR1 BPR0 0 0 0 0 EEPROM-1 Array Control Read: Register (EEACR1) Write: See page 98. Reset: EEOFF EERAS1 EERAS0 EEPRTCT EEBP3 EELAT 0 EEPGM EENVR Read: FLASH-1 Block Protect Register (FLBPR1) Write: See page 72. Reset: 0 0 0 0 0 0 0 0 FLASH-2 Block Protect Read: Register (FLBPR2) Write: See page 73. Reset: 0 0 0 0 0 0 0 0 Read: COP Control Register (COPCTL) Write: See page 207. Reset: Low byte of reset vector Clear COP counter Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9) MC68HC908AS60 — Rev. 1.0 Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Memory Map Table 2-1. Vector Addresses High Priority Freescale Semiconductor, Inc... Low Address Vector $FFDA TIM vector (high) $FFDB TIM vector (low) $FFDC BDLC vector (high) $FFDD BDLC vector (low) $FFDE ADC vector (high) $FFDF ADC vector (low) $FFE0 SCI transmit vector (high) $FFE1 SCI transmit vector (low) $FFE2 SCI receive vector (high) $FFE3 SCI receive vector (low) $FFE4 SCI error vector (high) $FFE5 SCI error vector (low) $FFE6 SPI transmit vector (high) $FFE7 SPI transmit vector (low) $FFE8 SPI receive vector (high) $FFE9 SPI receive vector (low) $FFEA TIM A overflow vector (high) $FFEB TIM A overflow vector (low) $FFEC TIM A channel 5 vector (high) $FFED TIM A channel 5 vector (low) $FFEE TIM A channel 4 vector (high) $FFEF TIM A channel 4 vector (low) $FFF0 TIM A channel 3 vector (high) $FFF1 TIM A channel 3 vector (low) $FFF2 TIM A channel 2 vector (high) $FFF3 TIM A channel 2 vector (low) $FFF4 TIM A channel 1 vector (high) $FFF5 TIM A channel 1vector (low) $FFF6 TIM A channel 0 vector (high) $FFF7 TIM A channel 0 vector (low) $FFF8 PLL vector (high) $FFF9 PLL vector (low) $FFFA IRQ1 vector (high) $FFFB IRQ1 vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) $FFFF Reset vector (low) Technical Data MC68HC908AS60 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 3. Random-Access Memory (RAM) Freescale Semiconductor, Inc... 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2 Introduction This section describes the 2048 bytes of random-access memory (RAM). 3.3 Functional Description Addresses $0050–$044F and $0A00–$0DFF are the RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64-Kbyte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. MC68HC908AS60 — Rev. 1.0 Technical Data Random-Access Memory (RAM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Random-Access Memory (RAM) Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Freescale Semiconductor, Inc... NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data MC68HC908AS60 — Rev. 1.0 Random-Access Memory (RAM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 4. FLASH-1 Memory Freescale Semiconductor, Inc... 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 67 4.6 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 68 4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8.1 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 72 4.8.2 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 73 4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.2 Introduction This section describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory 4.3 Functional Description Freescale Semiconductor, Inc... The FLASH memory physically consists of two independent arrays of 32 Kbytes with an additional 38 bytes of user vectors and two bytes of block protection. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages within rows. There are eight pages of memory per row with eight bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per-page basis, eight bytes at a time. The FLASH-1 address ranges for the user memory, control register, and vectors are: • $8000–$FDFF • $FF80–$FF81, block protect registers • $FE0B, FLASH control register • $FFDA–$FFFF, reserved for user-defined interrupt and reset vectors When programming the FLASH, just enough program time must be used to program a page. Too much program time can result in a program disturb condition, in which case an erased bit on the row being programmed becomes unintentionally programmed. Program disturb is avoided by using an iterative program and margin read technique known as the smart programming algorithm. The smart programming algorithm is required whenever programming the FLASH (see 4.7 FLASH Program/Margin Read Operation). To avoid the program disturb issue, each page on the row should be programmed only once before it is erased. The eight program cycle maximum per row aligns with the architecture’s eight pages of storage per row. The margin read step of the smart programming algorithm is used to ensure programmed bits are programmed to sufficient margin for data retention over the device lifetime. Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory FLASH-1 Control Register Freescale Semiconductor, Inc... The row architecture for this array is: • $8000–$803F (Row 0) • $8040–$807F (Row 1) • $8080–$80BF (Row 2) • -------------------------------------- • $FFC0–$FFFF (Row 511) Programming tools are available from Motorola. Contact a local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.(1) 4.4 FLASH-1 Control Register The FLASH-1 control register (FLCR1) controls FLASH-1 program, erase, and margin read operations. Address: $FE0B Bit 7 6 5 4 3 2 1 Bit 0 FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 4-1. FLASH-1 Control Register (FLCR1) FDIV1 — Frequency Divide Control Bit This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided from the system clock. See 4.5 FLASH Charge Pump Frequency Control. FDIV0 — Frequency Divide Control Bit This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided from the system clock. See 4.5 FLASH Charge Pump Frequency Control. 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory BLK1— Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See 4.6 FLASH Erase Operation for a description of available block sizes. BLK0 — Block Erase Control Bit Freescale Semiconductor, Inc... This read/write bit together with BLK1 allows erasing of blocks of varying size. See 4.6 FLASH Erase Operation for a description of available block sizes. HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can be set only if either PGM = 1 or ERASE = 1 and the proper sequence for program/margin read or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARGIN — Margin Read Control Bit This read/write bit configures the memory for margin read operation. MARGIN cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if asserted when HVEN = 1. 1 = Margin read operation selected 0 = Margin read operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be set at the same time. 1 = Program operation selected 0 = Program operation unselected Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory FLASH Charge Pump Frequency Control 4.5 FLASH Charge Pump Frequency Control Freescale Semiconductor, Inc... The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2-MHz clock. The charge pump clock is derived from the bus clock. Table 4-1 shows how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency. Program, margin read, and erase operations cannot be performed if the bus clock frequency is below 2 MHz. Table 4-1. Charge Pump Clock Frequency FDIV1 FDIV0 Pump Clock Frequency Bus Clock Frequency 0 0 Bus frequency ÷ 1 1.8–2.5 MHz 0 1 Bus frequency ÷ 2 3.6–5.0 MHz 1 0 Bus frequency ÷ 2 3.6–5.0 MHz 1 1 Bus frequency ÷ 4 7.2–8.4 MHz 4.6 FLASH Erase Operation See 24.13 Memory Characteristics for a detailed description of the times used in this algorithm. Use this step-by-step procedure to erase a block of FLASH memory: 1. Set the ERASE, BLK0, BLK1, FDIV0, and FDIV1 bits in the FLASH-1 control register. See Table 4-2 for block sizes and Table 4-1 for FDIV settings. 2. Ensure target portion of array is unprotected by reading the block protect register, FLBPR1: address $FF80. See 4.8 FLASH Block Protection and 4.8.1 FLASH-1 Block Protect Register for more information. 3. Write to any FLASH address with any data within the block address range desired. 4. Set the HVEN bit. 5. Wait for a time, tErase. 6. Clear the HVEN bit. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory 7. Wait for a time, tKill, for the high voltages to dissipate. 8. Clear the ERASE bit. 9. After time tHVD, the memory can be accessed in read mode again. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Freescale Semiconductor, Inc... Table 4-2 shows the various block sizes which can be erased in one erase operation. Table 4-2. Erase Block Sizes BLK1 BLK0 Block Size, Addresses Cared 0 0 Full array: 30 Kbytes 0 1 One-half array: 16 Kbytes (A14) 1 0 Eight rows: 512 bytes (A14–A9) 1 1 Single row: 64 bytes (A14–A6) In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any FLASH address in the range $8000–$FFFF will enable the full-array erase. NOTE: To ensure the timing requirements of the high-voltage erase and program mode of the FLASH memory, interrupts must be masked (interrupt mask bit of CCR = 1) when the HVEN bit is set. 4.7 FLASH Program/Margin Read Operation NOTE: After a total of eight program operations have been applied to a row, the row must be erased before further programming to avoid program disturb. An erased byte will read $00. Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes starting from address $XXX0 or $XXX8. The purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for long-term data retention. While performing a margin read, the operation is the same as for Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory FLASH Program/Margin Read Operation ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to ensure the bitcell is programmed with enough margin for long-term data retention. During these eight cycles, the COP counter continues to run. The user must account for these extra cycles within COP feed loops. A margin read cycle can only follow a page programming operation. Freescale Semiconductor, Inc... To program and margin read the FLASH memory, use this step-by-step algorithm. See 24.13 Memory Characteristics for a detailed description of the times used in this algorithm. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the block protect register (FLBPR1). 3. Write data to the eight bytes of the page being programmed. This requires eight separate write operations. 4. Set the HVEN bit. 5. Wait for a time, tPROG. 6. Clear the HVEN bit. 7. Wait for a time, tHVTV. 8. Set the MARGIN bit. 9. Wait for a time, tVTP. 10. Clear the PGM bit. 11. Wait for a time, tHVD. 12. Read back data in margin read mode. This is done in eight separate read operations which are each stretched by eight cycles. 13. Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory This program/margin read sequence is repeated throughout the memory until all data is programmed. The smart programming algorithm shown in Figure 4-2 is always required when programming any part of the array. This algorithm ensures the minimum possible program time and avoids the deleterious program disturb effect. (See 4.6 FLASH Erase Operation.) Freescale Semiconductor, Inc... NOTE: In order to ensure the timing requirements of the high-voltage erase and program mode of the FLASH memory, interrupts must be masked (interrupt mask bit of CCR = 1) when the HVEN bit is set. 4.8 FLASH Block Protection NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by reserving a location in the memory for block protect information and requiring that this location be read from to enable setting of the HVEN bit. When the block protect register is read, its contents are latched by the FLASH control logic. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is erased (all 0s), the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in 4.8.1 FLASH-1 Block Protect Register. The block protect register itself can be erased or programmed only with an external voltage VHI present on the IRQ pin. The presence of VHI on the IRQ pin also allows entry into monitor mode out of reset. Therefore, the ability to change the block protect register is voltage dependent and can occur in either user or monitor modes. Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory FLASH Block Protection PROGRAM FLASH 2TS Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. SET INTERRUPT MASK: SEI INSTRUCTION Note: This page program algorithm assumes the page/s to be programmed are initially erased. INITIALIZE ATTEMPT COUNTER TO 0 SET PGM BIT AND FDIV BITS Freescale Semiconductor, Inc... READ FLASH BLOCK PROTECT REG. WRITE DATA TO SELECTED PAGE SET HVEN BIT WAIT tSTEP CLEAR HVEN BIT WAIT tHVTV SET MARGIN BIT WAIT tVTP CLEAR PGM BIT WAIT tHVD MARGIN READ PAGE OF DATA CLEAR MARGIN BIT NO INCREMENT ATTEMPT COUNTER MARGIN READ DATA EQUAL TO WRITE DATA? YES NO CLEAR MARGIN BIT ATTEMPT COUNT EQUAL TO flsPulses? CLEAR INTERRUPT MASK: CLI INSTRUCTION YES PROGRAMMING OPERATION FAILED PROGRAMMING OPERATION COMPLETE Figure 4-2. Smart Programming Algorithm MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory 4.8.1 FLASH-1 Block Protect Register The block protect register (FLBPR1) is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-1 array. Address: Read: $FF80 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 BPR3 BPR2 BPR1 BPR0 0 0 0 0 Freescale Semiconductor, Inc... Write: Reset: 0 0 0 0 = Unimplemented Figure 4-3. FLASH-1 Block Protect Register (FLBPR1) BPR3 — Block Protect Register Bit 3 This bit protects the FLASH memory contents in the address range $C000–$FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR2 — Block Protect Register Bit 2 This bit protects the FLASH memory contents in the address range $A000–$FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR1 — Block Protect Register Bit 1 This bit protects the FLASH memory contents in the address range $9000–$FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR0 — Block Protect Register Bit 0 This bit protects the FLASH memory contents in the address range $8000–$FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory FLASH Block Protection Freescale Semiconductor, Inc... By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both bit 1 and bit 2 are set, for instance, the address range $9000–$FFFF is locked. If all bits are erased, then all of the memory is available for erase and program. The presence of a voltage VHI on the IRQ pin will bypass the block protection so that all of the memory, including the block protect register, is open for program and erase operations. 4.8.2 FLASH-2 Block Protect Register NOTE: This block protect register controls the FLASH-2 array block protection. However, since it is physically located in the FLASH-1 array, the FLASH-1 control register must be used to program/erase this register. The block protect register (FLBPR2) is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. Address: Read: $FF81 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 BPR3 BPR2 BPR1 BPR0 0 0 0 0 Write: Reset: 0 0 0 0 = Unimplemented Figure 4-4. FLASH-2 Block Protect Register (FLBPR2) BPR3 — Block Protect Register Bit 3 This bit protects the FLASH memory contents in the address range $4000–$7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory BPR2 — Block Protect Register Bit 2 This bit protects the FLASH memory contents in the address range $2000–$7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR1 — Block Protect Register Bit 1 Freescale Semiconductor, Inc... This bit protects the FLASH memory contents in the address range $1000–$7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR0 — Block Protect Register Bit 0 This bit protects the FLASH memory contents in the address range $0450–$7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both bit 1 and bit 2 are set, for instance, the address range $1000–$FFFF is locked. If all bits are erased, then all of the memory is available for erase and program. The presence of a voltage VHI on the IRQ pin will bypass the block protection so that all of the memory, including the block protect register, is open for program and erase operations. Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-1 Memory Low-Power Modes 4.9 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. Freescale Semiconductor, Inc... 4.9.1 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will be no memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into wait mode, the charge pump for the FLASH is disabled so that neither a program nor erase operation will continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN = 1), then it will remain in that mode during wait. Exit from wait must now be done with a reset rather than an interrupt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. 4.9.2 Stop Mode When the MCU is put into stop mode, if the FLASH is in read mode, it will be put into low-power standby. The STOP instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into stop mode, the charge pump for the FLASH is disabled so that neither a program nor erase operation will continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN = 1), then it will remain in that mode during stop. Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... FLASH-1 Memory Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 5. FLASH-2 Memory Freescale Semiconductor, Inc... 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.5 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 81 5.6 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 82 5.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 5.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 5.2 Introduction This section describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory 5.3 Functional Description Freescale Semiconductor, Inc... The FLASH-2 memory is an array of up to 29,616 bytes. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages within rows. There are eight pages of memory per row with eight bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per-page basis, eight bytes at a time. The address ranges for the user memory and the control register are: • $0450–$05FF • $0E00–$7FFF • $FE11, FLASH-2 control register When programming the FLASH, just enough program time must be used to program a page. Too much program time can result in a program disturb condition, in which case an erased bit on the row being programmed becomes unintentionally programmed. Program disturb is avoided by using an iterative program and margin read technique known as the smart programming algorithm. The smart programming algorithm is required whenever programming the FLASH. See 5.7 FLASH Program/Margin Read Operation. To avoid the program disturb issue, each storage page of the row should not be programmed more than once before it is erased. The eight program cycle maximum per row aligns with the architecture’s eight pages of storage per row. The margin read step of the smart programming algorithm is used to ensure programmed bits are programmed to sufficient margin for data retention over the device lifetime. The row architecture for this array is: • $7F40–$7F7F (Row 509) • $7F80–$7FBF (Row 510) • $7FC0–$7FFF (Row 511) Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory FLASH Control Register Programming tools are available from Motorola. Contact a local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.(1) 5.4 FLASH Control Register Freescale Semiconductor, Inc... The FLASH-2 control register (FLCR2) controls FLASH-2 program, erase, and margin read operations. Address: $FE11 Bit 7 6 5 4 3 2 1 Bit 0 FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 5-1. FLASH-2 Control Register (FLCR2) FDIV1 — Frequency Divide Control Bit This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided from the system clock. See 5.5 FLASH Charge Pump Frequency Control. FDIV0 — Frequency Divide Control Bit This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided from the system clock. See 5.5 FLASH Charge Pump Frequency Control. BLK1 — Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See 5.6 FLASH Erase Operation for a description of available block sizes. 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory BLK0 — Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size. See 5.6 FLASH Erase Operation for a description of available block sizes. HVEN — High-Voltage Enable Bit Freescale Semiconductor, Inc... This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can be set only if either PGM = 1 or ERASE = 1 and the proper sequence for program/margin read or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARGIN — Margin Read Control Bit This read/write bit configures the memory for margin read operation. MARGIN cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if asserted when HVEN = 1. 1 = Margin read operation selected 0 = Margin read operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be set at the same time. 1 = Program operation selected 0 = Program operation unselected Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory FLASH Charge Pump Frequency Control 5.5 FLASH Charge Pump Frequency Control The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2-MHz clock. The charge pump clock is derived from the bus clock. Table 5-1 shows how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency. Program, margin read, and erase operations cannot be performed if the bus clock frequency is below 2 MHz. Freescale Semiconductor, Inc... Table 5-1. Charge Pump Clock Frequency FDIV1 FDIV0 Pump Clock Frequency Bus Clock Frequency 0 0 Bus frequency ÷ 1 1.8–2.5 MHz 0 1 Bus frequency ÷ 2 3.6–5.0 MHz 1 0 Bus frequency ÷ 2 3.6–5.0 MHz 1 1 Bus frequency ÷ 4 7.2–8.4 MHz 5.6 FLASH Erase Operation See 24.13 Memory Characteristics for a detailed description of the times used in this algorithm. Use this step-by-step procedure to erase a block of FLASH-2 memory: 1. Set the ERASE, BLK0, BLK1, FDIV0, and FDIV1 bits in the FLASH control register. See Table 5-2 for block sizes and Table 5-1 for FDIV settings. 2. Ensure target portion of array is unprotected by reading the block protect register: address $FF81. See 5.8 FLASH Block Protection and 5.9 FLASH Block Protect Register for more information. 3. Write to any FLASH address with any data within the block address range desired. 4. Set the HVEN bit. 5. Wait for a time, tErase. 6. Clear the HVEN bit. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory 7. Wait for a time, tKill, for the high voltages to dissipate. 8. Clear the ERASE bit. 9. After a time, tHVD, the memory can be accessed in read mode again. Freescale Semiconductor, Inc... NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Table 5-2 shows the various block sizes which can be erased in one erase operation. Table 5-2. Erase Block Sizes BLK1 BLK0 Block Size, Addresses Cared 0 0 Full array: 24 Kbytes 0 1 One-half array: 16 Kbytes (A14) 1 0 Eight rows: 512 bytes (A14–A9) 1 1 Single row: 64 bytes (A14–A6) In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any FLASH address in the range $0450–$05FF or $0E00–$7FFF will enable the full-array erase. NOTE: To ensure the timing requirements of the high-voltage erase and program mode of the FLASH memory, interrupts must be masked (interrupt mask bit of CCR = 1) when the HVEN bit is set. 5.7 FLASH Program/Margin Read Operation NOTE: After a total of eight program operations have been applied to a row, the row must be erased before further programming to avoid program disturb. An erased byte will read $00. Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes starting from address $XXX0 or $XXX8. The purpose of the margin read, mode is to ensure that data has been programmed with sufficient margin for long-term data retention. Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory FLASH Program/Margin Read Operation Freescale Semiconductor, Inc... While performing a margin read, the operation is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to ensure the bitcell is programmed with enough margin for long-term data retention. During these eight cycles, the computer operating properly (COP) counter continues to run. The user must account for these extra cycles within COP feed loops. A margin read cycle can only follow a page programming operation. To program and margin read the FLASH memory, use this step-by-step algorithm. See 24.13 Memory Characteristics for a detailed description of the times used in this algorithm. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the block protect register (FLBPR2). 3. Write data to the eight bytes of the page being programmed. This requires eight separate write operations. 4. Set the HVEN bit. 5. Wait for a time, tPROG. 6. Clear the HVEN bit. 7. Wait for a time, tHVTV. 8. Set the MARGIN bit. 9. Wait for a time, tVTP. 10. Clear the PGM bit. 11. Wait for a time, tHVD. 12. Read back data in margin read mode. This is done in eight separate read operations which are each stretched by eight cycles. 13. Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory This program/margin read sequence is repeated throughout the memory until all data is programmed. The smart programming algorithm shown in Figure 5-2 is always required when programming any part of the array. This algorithm ensures the minimum possible program time and avoids the deleterious program disturb effect. See 5.6 FLASH Erase Operation. Freescale Semiconductor, Inc... NOTE: To ensure the timing requirements of the high-voltage erase and program mode of the FLASH memory, interrupts must be masked (interrupt mask bit of CCR = 1) when the HVEN bit is set. 5.8 FLASH Block Protection NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by reserving a location in the memory for block protect information and requiring that this location be read before setting the HVEN bit. When the block protect register is read, its contents are latched by the FLASH control logic. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is erased (all 0s), the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in 5.9 FLASH Block Protect Register. The block protect register itself can be erased or programmed only with an external voltage VHI present on the IRQ pin. The presence of VHI on the IRQ pin also allows entry into monitor mode out of reset. Therefore, the ability to change the block protect register is voltage dependent and can occur in either user or monitor modes. Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory FLASH Block Protection PROGRAM FLASH 2TS Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. SET INTERRUPT MASK: SEI INSTRUCTION Note: This page program algorithm assumes the page/s to be programmed are initially erased. INITIALIZE ATTEMPT COUNTER TO 0 SET PGM BIT AND FDIV BITS Freescale Semiconductor, Inc... READ FLASH BLOCK PROTECT REG. WRITE DATA TO SELECTED PAGE SET HVEN BIT WAIT tSTEP CLEAR HVEN BIT WAIT tHVTV SET MARGIN BIT WAIT tVTP CLEAR PGM BIT WAIT tHVD MARGIN READ PAGE OF DATA CLEAR MARGIN BIT NO INCREMENT ATTEMPT COUNTER MARGIN READ DATA EQUAL TO WRITE DATA? YES NO CLEAR MARGIN BIT ATTEMPT COUNT EQUAL TO flsPulses? CLEAR INTERRUPT MASK: CLI INSTRUCTION YES PROGRAMMING OPERATION FAILED PROGRAMMING OPERATION COMPLETE Figure 5-2. Smart Programming Algorithm MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory 5.9 FLASH Block Protect Register The block protect register for FLASH-2 is physically implemented as a byte within the FLASH-1 memory. Refer to Figure 4-4. FLASH-2 Block Protect Register (FLBPR2) for definition of this register. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. Freescale Semiconductor, Inc... 5.10 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 5.10.1 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into wait mode, the charge pump for the FLASH is disabled so that either a program or erase operation will not continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN = 1), then it will remain in that mode during wait. Exit from wait must now be done with a reset rather than an interrupt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. 5.10.2 Stop Mode When the MCU is put into stop mode, if the FLASH is in read mode, it will be put into low-power standby. The STOP instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into stop mode, the charge pump for the FLASH is disabled so that either a program or erase operation will not continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FLASH-2 Memory Low-Power Modes Freescale Semiconductor, Inc... HVEN = 1), then it will remain in that mode during wait. Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. MC68HC908AS60 — Rev. 1.0 Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... FLASH-2 Memory Technical Data MC68HC908AS60 — Rev. 1.0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 6. EEPROM-1 Freescale Semiconductor, Inc... 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.1 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.3 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.4 EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.5 MCU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.4.6 EEPROM Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.4.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4.8 EEPROM Non-Volatile Register and EEPROM Array Configuration Register . . . . . . . . . . . . . . . . . . . . . 98 6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 6.2 Introduction This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC908AS60 are physically located in two 512-byte arrays. This section details the array covering the address range $0800–$09FF. For information relating to the array covering address range $0600–$07FF, see Section 7. EEPROM-2. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 6.3 Features Freescale Semiconductor, Inc... EEPROM features include: • Byte, block, or bulk erasable • Non-volatile redundant array option • Non-volatile block protection option • Non-volatile MCU configuration bits • On-chip charge pump for programming/erasing • Security option 6.4 Functional Description The 512 bytes of EEPROM-1 can be programmed or erased without an external voltage supply. EEPROM cells are protected with a non-volatile block protection option. These options are stored in the EEPROM non-volatile register (EENVR1) and are loaded into the EEPROM array configuration register after reset (EEACR1) or a read of EENVR1. Hardware interlocks are provided to protect stored data corruption from accidental programming/erasing. 6.4.1 EEPROM Programming The unprogrammed state is a logic 1. Programming changes the state to a logic 0. Only valid EEPROM bytes in the non-protected blocks and EENVR1 can be programmed. When the array is configured in the redundant mode, programming the first 256 bytes also will program the last 256 bytes with the same data. Programming the EEPROM in the non-redundant mode is recommended. Program the data to both locations before entering redundant mode. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Functional Description Follow this step-by-step procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECR1. (See notes a and b.) 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note c.) 4. Wait for a time, tEEPGM, to program the byte. Freescale Semiconductor, Inc... 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the programming voltage to fall. 7. Clear EELAT bits. (See note d.) 8. Repeat steps 1 to 7 for more EEPROM programming. Notes: a. EERAS1 and EERAS0 must be cleared for programming. Otherwise, the part will be in erase mode. b. Setting EELAT bit configures the address and data buses to latch data for programming the array. Only data with valid EEPROM address will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR1 will be allowed only after a valid EEPROM write. c. To ensure proper programming sequence, the EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. When EEPGM is set, the on-board charge pump generates the program voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off. d. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 6.4.2 EEPROM Erasing The unprogrammed state is a logic 1. Only the valid EEPROM bytes in the non-protected blocks and EENVR1 can be erased. When the array is configured in the redundant mode, erasing the first 256 bytes also will erase the last 256 bytes. Using this step-by-step procedure erases EEPROM: Freescale Semiconductor, Inc... 1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase, and set EELAT in EECR1. (See note a.) 2. Write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. Set the EEPGM bit. (See note b.) 4. Wait for a time, tEEPGM/tEEBLOCK/tEEBULK.. 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the erasing voltage to fall. 7. Clear EELAT bits. (See note c.) 8. Repeat steps 1 to 7 for more EEPROM byte/block erasing. EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the corresponding block cannot be erased and bulk erase mode does not apply. Notes: a. Setting EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses with their data will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. In block erase mode, any EEPROM address in the block may be used in step 2. All locations within this block will be erased. In bulk erase mode, any EEPROM address may be used to erase the whole EEPROM. EENVR1 is not affected with block or bulk erase. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR1 will be allowed only after a valid EEPROM write. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Functional Description Freescale Semiconductor, Inc... b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified. If EEPGM is set, the on-board charge pump generates the erase voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. In general, all bits should be erased before being programmed. However, if program/erase cycling is of concern, minimize bit cycling in each EEPROM byte. If any bit in a byte requires change from a 0 to a 1, the byte needs to be erased before programming. Table 6-1 summarizes the conditions for erasing before programming Table 6-1. EEPROM Program/Erase Cycling Reduction EEPROM Data To Be Programmed EEPROM Data Before Programming Erase Before Programming? 0 0 No 0 1 No 1 0 Yes 1 1 No MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 6.4.3 EEPROM Block Protection The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be separately protected by EEBPx bit. Any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. Table 6-2 shows the address ranges within the blocks. Freescale Semiconductor, Inc... Table 6-2. EEPROM Array Address Blocks Block Number (EEBPx) Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900–$097F EEBP3 $0980–$09FF If EEBPx bit is set, that corresponding address block is protected. These bits are effective after a reset or a read to EENVR1 register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR1 register and then reading the EENVR1 register. In redundant mode, EEBP3 and EEBP2 will have no meaning. 6.4.4 EEPROM Redundant Mode To extend the EEPROM data retention, the array can be placed in redundant mode. In this mode, the first 256 bytes of user EEPROM array are mapped to the last 256 bytes. Reading, programming, and erasing of the first 256 EEPROM bytes will physically affect two bytes of EEPROM. Addressing the last 256 bytes will not be recognized. Block protection still applies but EEBP3 and EEBP2 are meaningless. NOTE: Programming the EEPROM in non-redundant mode and programming the data to its corresponding location before entering redundant mode is recommended. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Functional Description Freescale Semiconductor, Inc... The EEPROM non-volatile register (EENVR1) contains configurations concerning block protection and redundancy. EENVR1 is physically located on the bottom of the EEPROM array. The contents are non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration into a corresponding volatile EEPROM array configuration register (EEACR1). Thereafter, all reads to the EENVR1 will reload EEACR1. The EEPROM configuration can be changed by programming/erasing the EENVR1 like a normal EEPROM byte. The new array configuration will take affect with a system reset or a read of the EENVR1. 6.4.5 MCU Configuration The EEPROM non-volatile register (EENVR1) also contains general-purpose bits which can be used to enable/disable functions within the MCU which, for safety reasons, need to be controlled from non-volatile memory. On reset, this special register loads the MCU configuration into the volatile EEPROM array configuration register (EEACR1). Thereafter, all reads to the EENVR1 will reload EEACR1. The MCU configuration can be changed by programming/erasing the EENVR1 like a normal EEPROM byte. Note that it is the user’s responsibility to program the EENVR1 register to the correct system requirements and verify it prior to use. The new array configuration will take effect after a system reset or a read of the EENVR1. 6.4.6 EEPROM Protection The MC68HC908AS60 has a special protection option which prevents program/erase access to memory locations $08F0–$08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Freescale Semiconductor, Inc... In addition to the disabling of the program and erase operations on memory locations $08F0–$08FF, the enabling of the protect option has the following effects: NOTE: • Bulk and block erase modes are disabled. • Programming and erasing of the EENVR are disabled. • Unsecure locations ($0800–$08EF) can be erased using the single byte erase function as normal. • Secured locations can be read as normal. • Writing to a secure location no longer qualifies as a valid EEPROM write as detailed in 6.4.1 EEPROM Programming note b and 6.4.2 EEPROM Erasing note a. Once armed, the protect option is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled. 6.4.7 EEPROM Control Register This read/write register controls programming/erasing of the array. Address: $FE1D Bit 7 Read: 6 5 4 3 2 EEOFF EERAS1 EERAS0 EELAT 0 0 0 0 0 EEBCLK 1 Bit 0 0 EEPGM Write: Reset: 0 0 0 0 = Unimplemented Figure 6-1. EEPROM-1 Control Register (EECR1) EEBCLK — EEPROM Bus Clock Enable Bit This read/write bit determines which clock will be used to drive the internal charge pump for programming/erasing. Reset clears this bit. 1 = Bus clock drives charge pump. 0 = Internal RC oscillator drives charge pump. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Functional Description NOTE: It is recommended that the internal RC oscillator be used to drive the internal charge pump for applications that have a bus frequency of less than 8 MHz. Freescale Semiconductor, Inc... EEOFF — EEPROM Power Down Bit This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM array 0 = Enable EEPROM array NOTE: The EEPROM requires a recovery time, t EEOFF, to stabilize after clearing the EEOFF bit. EERAS1 and EERAS0 — Erase Bits These read/write bits set the erase modes (see Table 6-3). Reset clears these bits. Table 6-3. EEPROM Program/Erase Mode Select EEBPx EERAS1 EERAS0 MODE 0 0 0 Byte program 0 0 1 Byte erase 0 1 0 Block erase 0 1 1 Bulk erase 1 X X No erase/program X = Don’t care EELAT — EEPROM Latch Control Bit This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 EEPGM — EEPROM Program/Erase Enable Bit This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off Freescale Semiconductor, Inc... NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage. 6.4.8 EEPROM Non-Volatile Register and EEPROM Array Configuration Register The EEPROM non-volatile register (EENVR1) and array configuration register (EEACR1) are shown in Figure 6-2 and Figure 6-3. Address: $FE1C Bit 7 6 5 4 3 2 1 Bit 0 EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Read: Write: Reset: Programmed value or 1 in the erased state = Unimplemented Figure 6-2. EEPROM-1 Non-Volatile Register (EENVR1) Address: Read: $FE1F Bit 7 6 5 4 3 2 1 Bit 0 EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write: Reset: EENVR = Unimplemented Figure 6-3. EEPROM-1 Array Control Register (EEACR1) Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 Functional Description EERA — EEPROM Redundant Array Bit This programmable/erasable/read bit in EENVR1 and read-only bit in EEACR1 configures the array in redundant mode. Reset loads EERA from EENVR1 to EEACR1. 1 = EEPROM array is in redundant mode configuration. 0 = EEPROM array is in normal mode configuration. Freescale Semiconductor, Inc... CON2 and CON1 — MCU Configuration Bits These read/write bits can be used to enable/disable functions within the MCU. Reset loads CONx from EENVR1 to EEACR1. NOTE: The EEPROM protection feature is a write-once feature. Once the protection is enabled, it may not be disabled. EEPRTCT — EEPROM Protection Bit This one-time programmable bit can be used to protect 16 bytes ($8F0–$8FF) from being erased or programmed. 1 = EEPROM protection disabled 0 = EEPROM protection enabled EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP3–EEBP0 from EENVR1 to EEACR1. 1 = EEPROM array block is protected. 0 = EEPROM array block is unprotected. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-1 6.5 Low-Power Modes The WAIT and STOP instructions can put the MCU in low powerconsumption standby modes. Freescale Semiconductor, Inc... 6.5.1 Wait Mode The WAIT instruction does not affect the EEPROM. It is possible to program the EEPROM and put the MCU in wait mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit before executing the WAIT instruction. 6.5.2 Stop Mode The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction should not be executed while the high voltage is turned on (EEPGM = 1). If stop mode is entered while program/erase is in progress, high voltage will be automatically turned off. However, the EEPGM bit will remain set. When stop mode is terminated, and if EEPGM is still set, the high voltage will be automatically turned back on. Program/erase time will need to be extended if program/erase is interrupted by entering stop mode. The module requires a recovery time, tEESTOP, to stabilize after leaving stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 7. EEPROM-2 Freescale Semiconductor, Inc... 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.1 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.4.3 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . 106 7.4.4 EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . . 106 7.4.5 MCU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.4.6 MC68HC908AS60 EEPROM Protect. . . . . . . . . . . . . . . . . 107 7.4.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4.8 EEPROM Non-Volatile Register and EEPROM Array Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.2 Introduction This section describes the electrically erasable programmable read-only memory (EEPROM-2) covering the address range $0600–$07FF. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 7.3 Features Freescale Semiconductor, Inc... EEPROM-2 features include: • Byte, block, or bulk erasable • Non-volatile redundant array option • Non-volatile block protection option • Non-volatile MCU configuration bits • On-chip charge pump for programming/erasing • Security option 7.4 Functional Description The 512 bytes of EEPROM-2 can be programmed or erased without an external voltage supply. EEPROM cells are protected with a non-volatile block protection option. These options are stored in the EEPROM non-volatile register (EENVR2) and are loaded into the EEPROM array configuration register after reset (EEACR2) or a read of EENVR2. Hardware interlocks are provided to protect stored data corruption from accidental programming/erasing. 7.4.1 EEPROM Programming The unprogrammed state is a logic 1. Programming changes the state to a logic 0. Only valid EEPROM bytes in the non-protected blocks and EENVR2 can be programmed. When the array is configured in the redundant mode, programming the first 256 bytes also will program the last 256 bytes with the same data. Programming the EEPROM in the non-redundant mode is recommended. Program the data to both locations before entering redundant mode. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Functional Description Follow this step-by-step procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECTL. Set value of tEEPGM. (See notes a and b.) 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note c.) 4. Wait for a time, tEEPGM, to program the byte. Freescale Semiconductor, Inc... 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the programming voltage to fall. 7. Clear EELAT bits. (See note d.) 8. Repeat steps 1 to 7 for more EEPROM programming. Notes: a. EERAS1 and EERAS0 must be cleared for programming. Otherwise, the part will be in erase mode. b. Setting EELAT bit configures the address and data buses to latch data for programming the array. Only data with valid EEPROM address will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR2 will be allowed only after a valid EEPROM write. c. To ensure proper programming sequence, the EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. When EEPGM is set, the on-board charge pump generates the program voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off. d. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 7.4.2 EEPROM Erasing The unprogrammed state is a logic 1. Only the valid EEPROM bytes in the non-protected blocks and EENVR2 can be erased. When the array is configured in the redundant mode, erasing the first 256 bytes also will erase the last 256 bytes. Using this step-by-step procedure erases EEPROM: Freescale Semiconductor, Inc... 1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase, and set EELAT in EECR2. (See note a.) 2. Write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. Set the EEPGM bit. (See note b.) 4. Wait for a time, tEEPGM/tEEBLOCK/tEEBULK. 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the erasing voltage to fall. 7. Clear EELAT bits. (See note c.) 8. Repeat steps 1 to 7 for more EEPROM byte/block erasing. EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the corresponding block cannot be erased and bulk erase mode does not apply. Notes: a. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses with their data will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. In block erase mode, any EEPROM address in the block may be used in step 2. All locations within this block will be erased. In bulk erase mode, any EEPROM address may be used to erase the whole EEPROM. EENVR2 is not affected with block or bulk erase. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR2 will be allowed after a valid EEPROM write. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Functional Description Freescale Semiconductor, Inc... b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. In general, all bits should be erased before being programmed. However, if program/erase cycling is of concern, minimize bit cycling in each EEPROM byte. If any bit in a byte requires change from a 0 to a 1, the byte needs be erased before programming. Table 7-1 summarizes the conditions for erasing before programming Table 7-1. EEPROM Program/Erase Cycling Reduction EEPROM Data To Be Programmed EEPROM Data Before Programming Erase Before Programming? 0 0 No 0 1 No 1 0 Yes 1 1 No MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 7.4.3 EEPROM Block Protection The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be separately protected by EEBPx bit. Any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. Table 7-2 shows the address ranges within the blocks. Freescale Semiconductor, Inc... Table 7-2. EEPROM Array Address Blocks Block Number (EEBPx) Address Range EEBP0 $0600–$067F EEBP1 $0680–$06FF EEBP2 $0700–$077F EEBP3 $0780–$07FF If the EEBPx bit is set, that corresponding address block is protected. These bits are effective after a reset or a read to the EENVR2 register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR2 register and then reading the EENVR2 register. In redundant mode, EEBP3 and EEBP2 will have no meaning. 7.4.4 EEPROM Redundant Mode To extend the EEPROM data retention, the array can be placed in redundant mode. In this mode, the first 256 bytes of user EEPROM array are mapped to the last 256 bytes. Reading, programming, and erasing of the first 256 EEPROM bytes will physically affect two bytes of EEPROM. Addressing the last 256 bytes will not be recognized. Block protection still applies but EEBP3 and EEBP2 are meaningless. NOTE: Programming the EEPROM in non-redundant mode and programming the data to its corresponding location before entering redundant mode is recommended. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Functional Description Freescale Semiconductor, Inc... The EEPROM non-volatile register (EENVR2) contains configurations concerning block protection and redundancy. EENVR2 is physically located on the bottom of the EEPROM array. The contents are non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration into a corresponding volatile EEPROM array configuration register (EEACR2). Thereafter, all reads to the EENVR2 will reload EEACR2. The EEPROM configuration can be changed by programming/erasing the EENVR2 like a normal EEPROM byte. The new array configuration will take effect with a system reset or a read of the EENVR2. 7.4.5 MCU Configuration The EEPROM non-volatile register (EENVR2) also contains general-purpose bits which can be used to enable/disable functions within the MCU which, for safety reasons, need to be controlled from non-volatile memory. On reset, this special register loads the MCU configuration into the volatile EEPROM array configuration register (EEACR2). Thereafter, all reads to the EENVR2 will reload EEACR2. The MCU configuration can be changed by programming/erasing the EENVR2 like a normal EEPROM byte. Note that it is the users responsibility to program the EENVR2 register to the correct system requirements and verify it prior to use. The new array configuration will only take effect after a system reset or a read of the EENVR2. 7.4.6 MC68HC908AS60 EEPROM Protect The MC68HC908AS60 has a special protect option which prevents program/erase access to memory locations $06F0–$06FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR2 to 0. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Freescale Semiconductor, Inc... In addition to the disabling of the program and erase operations on memory locations $06F0–$06FF, the enabling of the protect option has the following effects: NOTE: • Bulk and block erase modes are disabled. • Programming and erasing of the EENVR are disabled. • Unsecure locations ($0600–$06EF) can be erased using the single byte erase function as normal. • Secured locations can be read as normal. • Writing to a secured location no longer qualifies as a valid EEPROM write as detailed in 7.4.1 EEPROM Programming note b and 7.4.2 EEPROM Erasing note a. Once armed, the security option is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled. 7.4.7 EEPROM Control Register This read/write register controls programming/erasing of the array. Address: $FE19 Bit 7 Read: 6 5 4 3 2 EEOFF EERAS1 EERAS0 EELAT 0 0 0 0 0 EEBCLK 1 Bit 0 0 EEPGM Write: Reset: 0 0 0 0 = Unimplemented Figure 7-1. EEPROM-2 Control Register (EECR2) EEBCLK — EEPROM Bus Clock Enable Bit This read/write bit determines which clock will be used to drive the internal charge pump for programming/erasing. Reset clears this bit. 1 = Bus clock drives charge pump. 0 = Internal RC oscillator drives charge pump. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Functional Description NOTE: It is recommended that the internal RC oscillator be used to drive the internal charge pump for applications that have a bus frequency of less than 8 MHz. Freescale Semiconductor, Inc... EEOFF — EEPROM Power Down Bit This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM array 0 = Enable EEPROM array NOTE: The EEPROM requires a recovery time, t EEOFF, to stabilize after clearing the EEOFF bit. EERAS1 and EERAS0 — Erase Bits These read/write bits set the erase modes. Reset clears these bits. Table 7-3. EEPROM Program/Erase Mode Select EEBPx EERAS1 EERAS0 MODE 0 0 0 Byte program 0 0 1 Byte erase 0 1 0 Block erase 0 1 1 Bulk erase 1 X X No erase/program X = Don’t care EELAT — EEPROM Latch Control Bit This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 EEPGM — EEPROM Program/Erase Enable Bit This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off Freescale Semiconductor, Inc... NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage. 7.4.8 EEPROM Non-Volatile Register and EEPROM Array Control Register The EEPROM non-volatile register (EENVR2) and array control register (EEACR2) are shown in Figure 7-2 and Figure 7-3. Address: $FE18 Bit 7 6 5 4 3 2 1 Bit 0 EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Read: Write: Reset: Programmed value or 1 in the erased state Figure 7-2. EEPROM-2 Non-Volatile Register (EENVR2) Address: Read: $FE1B Bit 7 6 5 4 3 2 1 Bit 0 EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write: Reset: EENVR2 = Unimplemented Figure 7-3. EEPROM-2 Array Control Register (EEACR2) Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 Functional Description EERA — EEPROM Redundant Array Bit This programmable/erasable/read bit in EENVR2 and read-only bit in EEACR2 configures the array in redundant mode. Reset loads EERA from EENVR2 to EEACR2. 1 = EEPROM array is in redundant mode configuration. 0 = EEPROM array is in normal mode configuration. Freescale Semiconductor, Inc... CON2 and CON1 — MCU Configuration Bits These read/write bits can be used to enable/disable functions within the MCU. Reset loads CONx from EENVR2 to EEACR2. NOTE: The EEPROM protect feature is a write-once feature. Once the protection is enabled, it may not be disabled. EEPRTCT — EEPROM Protect Bit This one-time programmable bit can be used to protect 16 bytes ($6F0–$6FF) from being erased or programmed. 1 = EEPROM protect disabled 0 = EEPROM protect enabled EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP3–EEBP0 from EENVR2 to EEACR2. 1 = EEPROM array block is protected. 0 = EEPROM array block is unprotected. MC68HC908AS60 — Rev. 1.0 Technical Data EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. EEPROM-2 7.5 Low-Power Modes The WAIT and STOP instructions can put the MCU in low power-consumption standby modes. Freescale Semiconductor, Inc... 7.5.1 Wait Mode The WAIT instruction does not affect the EEPROM. It is possible to program the EEPROM and put the MCU in wait mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit before executing the WAIT instruction. 7.5.2 Stop Mode The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction should not be executed while the high voltage is turned on (EEPGM = 1). If stop mode is entered while program/erase is in progress, high voltage will be automatically turned off. However, the EEPGM bit will remain set. When stop mode is terminated, and if EEPGM is still set, the high voltage will be automatically turned back on. Program/erase time will need to be extended if program/erase is interrupted by entering stop mode. The module requires a recovery time, tEESTOP, to stabilize after leaving stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. Technical Data MC68HC908AS60 — Rev. 1.0 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 8. Central Processor Unit (CPU) Freescale Semiconductor, Inc... 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.2 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.3 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.4.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . 119 8.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 8.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.2 Introduction This section describes the central processor unit (CPU08). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual, Motorola document order number CPU08RM/AD, contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.3 Features Freescale Semiconductor, Inc... Features of the CPU08 include: • Full upward, object-code compatibility with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-bit index register with X-register manipulation instructions • 8.4-MHz CPU internal bus frequency • 64-Kbyte program/data memory space • 16 addressing modes • Memory-to-memory data moves without using accumulator • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) CPU Registers 8.4 CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR (A) 15 0 Freescale Semiconductor, Inc... H 15 X INDEX REGISTER (H:X) 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 8-1. CPU Registers MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Freescale Semiconductor, Inc... Write: Reset: Unaffected by reset Figure 8-2. Accumulator (A) 8.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 8-3. Index Register (H:X) The index register can also be used as a temporary data storage location. Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) CPU Registers 8.4.3 Stack Pointer (SP) Freescale Semiconductor, Inc... The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least-significant byte to $FF and does not affect the most-significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 8-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000–$00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations. MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. Freescale Semiconductor, Inc... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 8-5. Program Counter (PC) Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) CPU Registers 8.4.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X Read: Freescale Semiconductor, Inc... Write: Reset: X = Indeterminate Figure 8-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) NOTE: To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. Freescale Semiconductor, Inc... A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions, such as bit test and branch, shift, and rotate, also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Arithmetic/Logic Unit (ALU) 8.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Freescale Semiconductor, Inc... Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. 8.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 8.6.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 8.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.7 CPU During Break Interrupts If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See Section 12. Break Module. The program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode). Freescale Semiconductor, Inc... A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 8.8 Instruction Set Summary Table 8-1 provides a summary of the M68HC08 instruction set. Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Operand Cycles IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff Effect on CCR Freescale Semiconductor, Inc... Source Form ADC ADC ADC ADC ADC ADC ADC ADC #opr opr opr opr,X opr,X ,X opr,SP opr,SP ADD ADD ADD ADD ADD ADD ADD ADD #opr opr opr opr,X opr,X ,X opr,SP opr,SP Operation Description V H I N Z C A ← (A) + (M) + (C) Add with Carry ↕ A ← (A) + (M) Add without Carry ↕ ↕ – ↕ – ↕ ↕ ↕ ↕ Address Mode Opcode Table 8-1. Instruction Set Summary (Sheet 1 of 8) ff ee ff ff ee ff 2 3 4 4 3 2 4 5 AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM A7 ii 2 AIX #opr Add Immediate Value (Signed to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2 ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 ↕ DIR INH INH ↕ IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 37 dd 47 57 67 ff 77 9E67 ff 4 1 1 4 3 5 AND AND AND AND AND AND AND AND #opr opr opr opr,X opr,X ,X opr,SP opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP A ← (A) & (M) Logical AND Arithmetic Shift Left (Same as LSL) C Arithmetic Shift Right BCC rel Branch if Carry Bit Clear BCLR n, opr 0 b7 ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP ↕ – – – – ↕ ↕ b0 C b7 Clear Bit n in M 0 ↕ – – ↕ ↕ DIR INH INH ↕ IX1 IX SP1 – – – – – – REL 24 rr 3 – DIR (b0) DIR (b1) DIR (b2) DIR (b3) – DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 b0 PC ← (PC) + 2 + rel ? (C) = 0 Mn ← 0 ff ee ff – – – – MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Freescale Semiconductor, Inc... V H I N Z C Cycles Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-1. Instruction Set Summary (Sheet 2 of 8) BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3 BGT opr Branch if Greater Than (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V ) = 0 – – – – – – REL 92 rr 3 BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr 3 BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3 BHS rel Branch if Higher or Same (Same as BCC) PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3 BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3 ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 A5 B5 C5 D5 E5 F5 9EE5 9ED5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 93 rr 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) BLO rel Branch if Lower (Same as BCS) BLS rel (A) & (M) PC ← (PC) + 2 + rel ? (Z) | (N 0 – – ↕ ⊕ V) = 1 – – – – – – REL PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL 91 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel – – – – – – REL 20 rr 3 – DIR (b0) DIR (b1) DIR (b2) DIR (b3) ↕ DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary BRN rel Freescale Semiconductor, Inc... BRSET n,opr,rel BSET n,opr BSR rel PC ← (PC) + 2 Branch Never PC ← (PC) + 3 + rel ? (Mn) = 1 Branch if Bit n in M Set Set Bit n in M Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M V H I N Z C – – – – – – – – Cycles Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-1. Instruction Set Summary (Sheet 3 of 8) – – REL 21 rr 3 – DIR (b0) DIR (b1) DIR (b2) DIR (b3) ↕ DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 rr 4 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 Mn ← 1 – – – – – DIR (b0) DIR (b1) DIR (b2) DIR (b3) – DIR (b4) DIR (b5) DIR (b6) DIR (b7) PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel – – – – – – REL AD 31 41 51 61 71 9E61 98 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00 – – – – – DIR IMM IMM – IX1+ IX+ SP1 C←0 – – – – – 0 INH I←0 – – 0 – – – INH 1 DIR INH INH – INH IX1 IX SP1 3F dd 4F 5F 8C 6F ff 7F 9E6F ff 3 1 1 1 3 2 4 ↕ IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 A1 B1 C1 D1 E1 F1 9EE1 9ED1 2 3 4 4 3 2 4 5 M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 (A) – (M) 0 ↕ – – 0 – – MC68HC908AS60 — Rev. 1.0 ↕ 1 9A 2 ii dd hh ll ee ff ff ff ee ff Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) COM opr COMA COMX COM opr,X COM ,X COM opr,SP M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) Complement (One’s Complement) V H I N Z C 0 – – ↕ Cycles Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-1. Instruction Set Summary (Sheet 4 of 8) ↕ DIR INH INH 1 IX1 IX SP1 ↕ IMM ↕ DIR 65 75 ii+ 1 dd 3 4 ↕ IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 A3 B3 C3 D3 E3 F3 9EE3 9ED3 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 ↕ INH 72 DIR INH – INH IX1 IX SP1 3B 4B 5B 6B 7B 9E6B 3A dd 4A 5A 6A ff 7A 9E6A ff 33 dd 43 53 63 ff 73 9E63 ff 4 1 1 4 3 5 Freescale Semiconductor, Inc... ii CPHX #opr CPHX opr CPX CPX CPX CPX CPX CPX CPX CPX #opr opr opr ,X opr,X opr,X opr,SP opr,SP DAA Compare H:X with M (H:X) – (M:M + 1) Compare X with M (X) – (M) (A)10 Decimal Adjust A DBNZ opr,rel DBNZA rel Decrement and Branch if Not DBNZX rel Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment ↕ ↕ U A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 – PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0 – – – – – – ↕ ↕ ↕ – – – ↕ – ff ee ff 2 dd rr rr rr ff rr rr ff rr M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1 ↕ – – ↕ ↕ DIR INH INH – IX1 IX SP1 A ← (H:A)/(X) H ← Remainder – – – – ↕ ↕ INH 52 ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 A8 B8 C8 D8 E8 F8 9EE8 9ED8 DIR INH INH – IX1 IX SP1 3C dd 4C 5C 6C ff 7C 9E6C ff A ← (A ⊕ M) M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 0 ↕ – – – – Technical Data ↕ ↕ ↕ 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc... JMP JMP JMP JMP JMP opr opr opr,X opr,X ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Operation BC CC DC EC FC dd hh ll ee ff ff 2 3 4 3 2 – DIR EXT – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 Jump to Subroutine ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Load A from M LDHX #opr LDHX opr Load H:X from M ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right A ← (M) Move MUL Unsigned multiply 0 X ← (M) 0 C 0 b7 – 0 H:X ← ( M:M + 1) ↕ – – – – – – – – – – – – – – ↕ ↕ ↕ ↕ C ↕ – – 0 ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE ↕ DIR INH INH ↕ IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 ↕ DIR INH INH ↕ IX1 IX SP1 34 dd 44 54 64 ff 74 9E64 ff 4 1 1 4 3 5 4E 5E 6E 7E 42 0 – – ↕ ↕ DD DIX+ – IMD IX+D – 0 – – – 0 INH (M)Destination ← (M)Source H:X ← (H:X) + 1 (IX+D, DIX+) MC68HC908AS60 — Rev. 1.0 45 55 – b0 X:A ← (X) × (A) IMM DIR ↕ b0 0 b7 MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr – PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address Load X from M Logical Shift Left (Same as ASL) V H I N Z C PC ← Jump Address Jump LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP Description Cycles Operand – DIR EXT – IX2 IX1 IX Effect on CCR Source Form Address Mode Opcode Table 8-1. Instruction Set Summary (Sheet 5 of 8) ff ee ff dd dd dd ii dd dd 5 4 4 4 5 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Freescale Semiconductor, Inc... V H I N Z C Cycles Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-1. Instruction Set Summary (Sheet 6 of 8) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) ↕ – – ↕ ↕ DIR INH INH ↕ IX1 IX SP1 No Operation None – – – – – – INH 9D 1 Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3 ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 AA BA CA DA EA FA 9EEA 9EDA NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP Negate (Two’s Complement) NOP NSA 30 dd 40 50 60 ff 70 9E60 ff 4 1 1 4 3 5 ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP Inclusive OR A and M PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2 A ← (A) | (M) 0 – – ↕ ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2 PULA Pull A from Stack SP ← (SP + 1); Pull (A ) – – – – – – INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X ) – – – – – – INH 88 2 ↕ DIR INH INH ↕ IX1 IX SP1 39 dd 49 59 69 ff 79 9E69 ff 4 1 1 4 3 5 36 dd 46 56 66 ff 76 9E66 ff 4 1 1 4 3 5 ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Rotate Left through Carry C ↕ b7 ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine – – ↕ b0 ↕ – – ↕ ↕ DIR INH INH ↕ IX1 IX SP1 SP ← $FF – – – – – – INH 9C 1 SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) ↕ ↕ ↕ ↕ ↕ INH 80 7 SP ← SP + 1; Pull ( PCH) SP ← SP + 1; Pull (PCL) – – – – – – INH 81 4 C b7 b0 ↕ Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc... SBC SBC SBC SBC SBC SBC SBC SBC #opr opr opr opr,X opr,X ,X opr,SP opr,SP Operation Description A2 B2 C2 D2 E2 F2 9EE2 9ED2 ii dd hh ll ee ff ff A ← (A) – (M) – (C) Subtract with Carry V H I N Z C ↕ – – ↕ ↕ ff ee ff Cycles Operand IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 Effect on CCR Source Form Address Mode Opcode Table 8-1. Instruction Set Summary (Sheet 7 of 8) 2 3 4 4 3 2 4 5 SEC Set Carry Bit C←1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask I←1 – – 1 – – – INH 9B 2 ↕ DIR EXT IX2 – IX1 IX SP1 SP2 B7 C7 D7 E7 F7 9EE7 9ED7 STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP M ← (A) Store A in M STHX opr Store H:X in M STOP Enable IRQ Pin; Stop Oscillator STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Store X in M Subtract 0 – – ↕ dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 dd 4 (M:M + 1) ← (H:X) 0 – – ↕ ↕ – DIR 35 I ← 0; Stop Oscillator – – 0 – – – INH 8E ↕ DIR EXT IX2 – IX1 IX SP1 SP2 BF CF DF EF FF 9EEF 9EDF dd hh ll ee ff ff IMM DIR EXT IX2 ↕ IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff M ← (X) A ← (A) – (M) 0 ↕ – – – – ↕ ↕ ↕ 1 ff ee ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte TAP Transfer A to CCR CCR ← (A) ↕ ↕ ↕ ↕ ↕ INH 84 2 TAX Transfer A to X X ← (A) – – – – – – INH 97 1 TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1 – – 1 – – – INH 83 9 ↕ MC68HC908AS60 — Rev. 1.0 Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processor Unit (CPU) Freescale Semiconductor, Inc... TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Test for Negative or Zero TSX Transfer SP to H:X TXA Transfer X to A TXS Transfer H:X to SP A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N V H I N Z C Cycles Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-1. Instruction Set Summary (Sheet 8 of 8) (A) – $00 or (X) – $00 or (M) – $00 0 – – ↕ ↕ DIR INH INH – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH 9F 1 (SP) ← (H:X) – 1 – – – – – – INH 94 2 Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & | ⊕ () –( ) # « ← ? : ↕ — 3D dd 4D 5D 6D ff 7D 9E6D ff 3 1 1 3 2 4 Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected 8.9 Opcode Map The opcode map is provided in Table 8-2. Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 2 2 2 2 2 2 2 2 2 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 7 8 9 A B C D E F MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 2 2 2 2 2 2 4 BCLR4 DIR 4 BSET5 DIR 4 BCLR5 DIR 4 BSET6 DIR 4 BCLR6 DIR 4 BSET7 DIR 2 3 BMS REL 3 BIH REL 2 2 3 BMC REL 3 BIL REL 3 2 3 BPL REL 3 BMI REL 2 3 BHCS REL 2 3 BHCC REL 2 3 BNE REL 2 2 3 BCS REL 3 BEQ REL 2 3 BCC REL 2 1 1 5 DBNZ DIR 4 INC DIR 3 TST DIR 3 CLR DIR 1 4 DEC DIR 1 3 1 4 ROL DIR 1 4 LSL DIR 1 4 ROR DIR 1 3 4 STHX DIR 4 ASR DIR 1 4 LSR DIR INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD Direct-Direct IMD Immediate-Direct IX+D Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions 2 2 4 BSET4 DIR 4 BCLR7 DIR 2 4 BCLR3 DIR 2 4 BSET3 DIR 2 5 BRSET3 3 DIR 6 2 4 BCLR2 DIR 2 5 BRCLR2 3 DIR 5 2 4 BSET2 DIR 2 1 1 3 DBNZA INH 1 INCA INH 1 TSTA INH 1 1 CLRX INH 2 3 2 1 TSTX INH 4 2 1 INCX INH 4 IX1 4 IX1 4 IX1 4 IX1 4 IX1 4 IX1 4 IX1 3 IX1 CLR IX1 3 4 MOV IMD TST INC 5 DBNZ IX1 DEC ROL LSL ASR ROR 3 CPHX IMM LSR 4 COM IX1 3 NSA INH 5 3 3 3 4 3 3 3 3 3 3 3 4 3 1 1 2 1 1 5 ROL SP1 5 DEC SP1 6 DBNZ SP1 5 INC SP1 4 TST SP1 4 CLR SP1 1 5 LSL SP1 1 3 IX 3 IX TST INC DBNZ DEC ROL LSL ASR ROR CLR IX 2 4 IX 2 IX 3 IX 4 IX 3 IX 3 IX 3 IX 3 IX 3 4 CPHX DIR LSR COM 2 DAA INH MOV 2 IX+D 1 1 2 1 1 5 ASR SP1 5 ROR SP1 5 LSR SP1 5 COM SP1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 CBEQ IX+ 2 6 CBEQ SP1 3 1 NEG 1 5 NEG SP1 IX 7 IX 9E6 SP1 Stack Pointer, 8-Bit Offset Stack Pointer, 16-Bit Offset Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment SP1 SP2 IX+ 1 CLRA INH DD 3 2 1 DECX INH 3 DBNZX INH 2 1 ROLX INH 2 1 LSLX INH 2 1 RORX INH 2 3 4 LDHX DIR 1 ASRX INH 2 2 1 LSRX INH 1 COMX INH MOV 2 DIX+ 1 1 DECA INH 5 1 1 ROLA INH MOV 1 1 LSLA INH 1 1 RORA INH 1 2 3 LDHX IMM 1 ASRA INH 1 1 LSRA INH 1 2 1 1 COMA INH 5 BRSET2 3 DIR 4 COM DIR 4 3 BLS REL 2 2 1 4 BCLR1 DIR INH 7 2 DIV 5 BRCLR1 3 DIR 1 5 MUL INH 3 1 2 4 BSET1 DIR 2 5 BRSET1 3 DIR 2 3 BHI REL CBEQ 3 IX1+ 4 CBEQX IMM 3 4 CBEQA IMM 3 5 CBEQ DIR 3 3 BRN REL 2 4 BCLR0 DIR 2 5 BRCLR0 3 DIR 1 4 IX1 NEG 2 1 NEGX INH 1 1 NEGA INH 1 4 NEG DIR 2 3 BRA REL 2 4 BSET0 DIR 2 5 BRSET0 3 DIR 0 LSB 6 IX1 5 INH Read-Modify-Write 4 INH 3 DIR 2 REL Branch 1 DIR 0 MSB DIR Bit Manipulation 1 1 2 PSHH INH 1 CLRH INH 1 2 INH 1 TXA INH * 1 NOP INH 1 RSP INH SEI INH 2 2 2 2 2 2 1 SEC INH 2 2 1 CLC INH CLI 2 2 2 2 1 TAX INH 2 TSX INH 2 TXS INH 2 AIX IMM 2 LDX IMM 4 BSR REL 3 DIR 3 3 ADD DIR 0 MSB 3 STX DIR 3 LDX DIR 4 JSR DIR 3 3 3 4 ADC EXT 4 ORA EXT 4 ADD EXT 0 4 STX EXT 4 LDX EXT 5 JSR EXT STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC 4 IX2 4 IX2 4 IX2 6 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 IX2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 5 ADD SP2 5 STX SP2 5 LDX SP2 2 5 ORA SP2 2 2 2 2 2 2 5 EOR SP2 5 ADC SP2 2 5 STA SP2 2 2 5 BIT SP2 5 LDA SP2 2 2 5 CPX SP2 5 AND SP2 2 5 SBC SP2 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC Cycles Opcode Mnemonic Number of Bytes / Addressing Mode IX1 3 IX1 3 IX1 5 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 IX1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CMP IX1 2 5 CMP SP2 3 3 SUB 2 5 SUB SP2 IX1 E IX1 9ED SP2 High Byte of Opcode in Hexadecimal 3 3 3 3 3 4 EOR EXT 3 JMP EXT 3 3 3 3 4 STA EXT 4 LDA EXT 4 BIT EXT 4 AND EXT 5 BRSET0 3 DIR 3 3 3 3 3 3 ORA DIR 2 JMP DIR 3 3 3 EOR DIR 3 ADC DIR 3 3 3 3 3 STA DIR 3 LDA DIR BIT 3 AND DIR 3 LSB 2 2 2 2 2 2 2 ORA IMM 2 ADD IMM 2 2 2 EOR IMM 2 ADC IMM 2 2 2 2 2 AIS IMM 2 LDA IMM 2 BIT IMM 2 AND IMM 2 3 CPX DIR 3 2 CPX IMM 3 3 SBC DIR 4 CPX EXT 2 3 BLE REL 2 3 2 SBC IMM 4 SBC EXT 2 3 4 CMP EXT 3 3 CMP DIR 2 2 CMP IMM 2 3 BLT REL 3 BGT REL SUB 3 4 SUB EXT 3 3 SUB DIR 2 2 SUB IMM 2 3 BGE REL CMP D IX2 Register/Memory C EXT B DIR A IMM 9 INH Low Byte of Opcode in Hexadecimal 1 WAIT INH 1 STOP INH 1 2 PULH INH 1 1 1 2 PULX INH 2 PSHX INH 1 1 1 2 2 PSHA INH 2 PULA INH 1 TPA INH 2 TAP INH 9 SWI INH 2 4 RTS INH 2 2 7 INH RTI 8 INH Control Table 8-2. Opcode Map Freescale Semiconductor, Inc... 1 4 SBC SP1 4 STX SP1 4 LDX SP1 1 1 1 1 1 1 4 ORA SP1 4 ADD SP1 1 1 4 EOR SP1 4 ADC SP1 1 4 STA SP1 1 1 4 BIT SP1 4 LDA SP1 1 4 AND SP1 1 1 4 CMP SP1 4 CPX SP1 SUB 1 4 SUB SP1 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP F IX 9EE SP1 2 IX 2 IX 2 IX 4 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX 2 IX Freescale Semiconductor, Inc. Central Processor Unit (CPU) Opcode Map Technical Data Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Central Processor Unit (CPU) Technical Data MC68HC908AS60 — Rev. 1.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 9. System Integration Module (SIM) 9.1 Contents Freescale Semiconductor, Inc... 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 137 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 137 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 138 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 139 9.4.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 141 9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .142 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 142 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 143 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 143 9.6 Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 147 9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 9.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 154 9.2 Introduction Freescale Semiconductor, Inc... This section describes the system integration module (SIM), which supports up to 32 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. A block diagram of the SIM is shown in Figure 9-1. Figure 9-2 is a summary of the SIM input/output (I/O) registers. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) Freescale Semiconductor, Inc... CGMOUT (FROM CGM) ÷2 CLOCK CONTROL RESET PIN LOGIC CLOCK GENERATORS INTERNAL CLOCKS LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU INTERFACE Figure 9-1. SIM Block Diagram MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Addr. $FE00 Freescale Semiconductor, Inc... $FE01 $FE03 Register Name Bit 7 6 5 4 3 2 R R R R R R Read: SIM Break Status Register (SBSR) Write: See page 151. Reset: Read: SIM Reset Status Register (SRSR) Write: See page 153. Reset: Read: SIM Break Flag Control Register (SBFCR) Write: See page 154. Reset: 1 Bit 0 SBSW R See Note 0 POR PIN COP ILOP ILAD 0 LVI 0 1 0 0 0 0 0 0 0 BCFE R R R R R R R 0 = Unimplemented Note: Writing a logic 0 clears SBSW. R = Reserved Figure 9-2. SIM I/O Register Summary Table 9-1 shows the internal signal names used in this section. Table 9-1. Signal Name Conventions Signal Name Description CGMXCLK Buffered version of OSC1 from clock generator module (CGM) CGMVCLK PLL output CGMOUT PLL-based or OSC1-based clock output from clock generator module (CGM) Bus clock = CGMOUT divided by two IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset (POR) module to the SIM IRST Internal reset signal R/W Read/write signal Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Bus Clock Control and Generation 9.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come from either an external oscillator or from the on-chip phase-locked loop (PLL). See Section 10. Clock Generator Module (CGM). Freescale Semiconductor, Inc... 9.3.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. See Section 10. Clock Generator Module (CGM). 9.3.2 Clock Startup from POR or LVI Reset When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the timeout. CGMXCLK OSC1 CLOCK SELECT CIRCUIT CGMVCLK ÷2 A CGMOUT B S* *When S = 1, CGMOUT = B ÷2 BUS CLOCK GENERATORS SIM BCS PLL SIM COUNTER PTC3 MONITOR MODE USER MODE CGM Figure 9-3. CGM Clock Signals MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) 9.3.3 Clocks in Stop Mode and Wait Mode Freescale Semiconductor, Inc... Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See 9.7.2 Stop Mode. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 9.4 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 9.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 9.8 SIM Registers. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization 9.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 9-2 for details. Figure 9-4 shows the relative timing. Freescale Semiconductor, Inc... Table 9-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) CGMOUT RST IAB VECT H PC VECT L Figure 9-4. External Reset Timing 9.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 9-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 9-6 . Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 9-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Freescale Semiconductor, Inc... Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 9-6. Sources of Internal Reset 9.4.2.1 Power-On Reset (POR) When power is first applied to the MCU, the POR generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT. • Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. • The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK Freescale Semiconductor, Inc... CGMOUT RST $FFFE IAB $FFFF Figure 9-7. POR Recovery 9.4.2.2 Computer Operating Properly (COP) Reset The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG-1 register is at logic 0. See Section 14. Computer Operating Properly (COP) Module. 9.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the CONFIG-1 register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. 9.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address using MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) indexed addressing and PUL/PSH instructions will also generate an illegal address reset. Freescale Semiconductor, Inc... WARNING: Extra care should be exercised when using this emulator part for development of code to be run in ROM-based M68HC08AS Family parts with a smaller memory size since some legal addresses will become illegal addresses on the smaller ROM memory map device and may, as a result, generate unwanted resets. 9.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit (LVI) module asserts its output to the SIM when the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic 0. The RST pin will be held low until the SIM counts 4096 CGMXCLK cycles after VDD rises above VLVIR. Another 64 CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. See Section 15. Low-Voltage Inhibit (LVI) Module. 9.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of CGMXCLK. 9.5.1 SIM Counter During Power-On Reset The POR detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control Freescale Semiconductor, Inc... 9.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG-1 register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. 9.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter (see 9.7.2 Stop Mode for details). The SIM counter is free-running after all reset states. See 9.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences. 9.6 Program Exception Control Normal, sequential program execution can be changed in three different ways: 1. Interrupts: a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 9.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 9-8 shows interrupt entry timing. Figure 9-9 shows interrupt recovery timing. MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See Figure 9-10. Freescale Semiconductor, Inc... MODULE INTERRUPT I BIT IAB IDB DUMMY SP DUMMY SP – 1 PC – 1[7:0] SP – 2 PC–1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 9-8. Interrupt Entry MODULE INTERRUPT I BIT IAB IDB SP – 4 SP – 3 CCR SP – 2 A SP – 1 X PC – 1 [7:0] SP PC PC–1[15:8] PC + 1 OPCODE OPERAND R/W Figure 9-9. Interrupt Recovery Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control FROM RESET YES BREAK INTERRUPT? I BIT SET? Freescale Semiconductor, Inc... NO YES I BIT SET? NO IRQ1 INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 9-10. Interrupt Processing MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) 9.6.1.1 Hardware Interrupts Freescale Semiconductor, Inc... A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 9-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805, M146805, and M68HC05 Families, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 9.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE Freescale Semiconductor, Inc... PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 9-11. Interrupt Recognition Example 9.6.2 Reset All reset sources always have higher priority than interrupts and cannot be arbitrated. 9.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. See Section 12. Break Module. The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Freescale Semiconductor, Inc... Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 9.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in this section. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 9.7.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 9-12 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) Low-Power Modes IAB WAIT ADDR IDB WAIT ADDR + 1 PREVIOUS DATA SAME SAME NEXT OPCODE SAME SAME R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 9-12. Wait Mode Entry Timing Freescale Semiconductor, Inc... IAB $6E0B IDB $A6 $A6 $6E0C $A6 $01 $00FF $00FE $0B $00FD $00FC $6E EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin or CPU interrupt OR break interrupt Figure 9-13. Wait Recovery from Interrupt or Break 32 CYCLES IAB IDB 32 CYCLES $6E0B $A6 $A6 RSTVCT H RSTVCTL $A6 RST CGMXCLK Figure 9-14. Wait Recovery from Internal Reset 9.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG-1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. Freescale Semiconductor, Inc... NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 9-15 shows stop mode entry timing. CPUSTOP IAB IDB STOP ADDR STOP ADDR + 1 PREVIOUS DATA SAME NEXT OPCODE SAME SAME SAME R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 9-15. Stop Mode Entry Timing STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 9-16. Stop Mode Recovery from Interrupt or Break Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Registers 9.8 SIM Registers The SIM has three memory mapped registers: • Break status register, SBSR • Reset status register, SRSR • Break flag control register, SBFCR Freescale Semiconductor, Inc... 9.8.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW See Note Bit 0 R 0 R = Reserved Note: Writing a logic 0 clears SBSW. Figure 9-17. SIM Break Status Register (SBSR) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The code given here is an example of this. Writing 0 to the SBSW bit clears it. MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 Freescale Semiconductor, Inc... ; If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited ; by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too. DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH RTI ; Restore H register. Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Registers 9.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset. The status register will automatically clear after reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: Freescale Semiconductor, Inc... Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD 0 LVI 0 1 0 0 0 0 0 0 0 Write: POR: = Unimplemented Figure 9-18. SIM Reset Status Register (SRSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR MC68HC908AS60 — Rev. 1.0 Technical Data System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Integration Module (SIM) 9.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Freescale Semiconductor, Inc... Write: Reset: 0 R = Reserved Figure 9-19. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Technical Data MC68HC908AS60 — Rev. 1.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 10. Clock Generator Module (CGM) Freescale Semiconductor, Inc... 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . 159 10.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .161 10.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . 161 10.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . 165 10.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 165 10.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .167 10.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 167 10.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 167 10.5.4 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 168 10.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .168 10.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 168 10.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 168 10.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 171 10.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 10.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 175 Freescale Semiconductor, Inc... 10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 176 10.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . 176 10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .177 10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 178 10.2 Introduction The clock generator module (CGM) generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1-MHz to 8-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency without using a 32-MHz crystal. 10.3 Features Features of the CGM include: • Phase-locked loop with output frequency in integer multiples of the crystal reference • Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation • Automatic bandwidth control mode for low-jitter operation • Automatic frequency lock detector • CPU interrupt on entry or exit from locked condition Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 10.4 Functional Description The CGM consists of three major submodules: 1. Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. Freescale Semiconductor, Inc... 2. Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock CGMVCLK. 3. Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT. Figure 10-1 shows the structure of the CGM. 10.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50 percent and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGMXCLK OSC1 CLOCK SELECT CIRCUIT CGMRDV ÷2 CGMRCLK A CGMOUT B S* *When S = 1, CGMOUT = B BCS PTC3 VDDA CGMXFC VSS MONITOR MODE VRS7–VRS4 Freescale Semiconductor, Inc... USER MODE PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PLL ANALOG LOCK DETECTOR LOCK BANDWIDTH CONTROL AUTO ACQ INTERRUPT CONTROL PLLIE CGMINT PLLF MUL7–MUL4 CGMVDV FREQUENCY DIVIDER CGMVCLK Figure 10-1. CGM Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description Addr. $001C Freescale Semiconductor, Inc... $001D $001E Register Name Bit 7 Read: PLL Control Register (PCTL) Write: See page 169. Reset: Read: PLL Bandwidth Control Register (PBWC) Write: See page 171. Reset: Read: PLL Programming Register (PPG) Write: See page 173. Reset: 6 5 4 PLLON BCS 1 0 ACQ XLD PLLF PLLIE 0 0 LOCK AUTO 3 2 1 Bit 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 = Unimplemented Figure 10-2. I/O Register Summary 10.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 10.4.2.1 Circuits The PLL consists of these circuits: • Voltage-controlled oscillator (VCO) • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM. Freescale Semiconductor, Inc... CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV, running at a frequency fRDV = fRCLK. The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed back through a programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s output is the VCO feedback clock, CGMVDV, running at a frequency fVDV = fVCLK/N. See 10.4.2.4 Programming the PLL for more information. The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in 10.4.2.2 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 10.4.2.2 Acquisition and Tracking Modes Freescale Semiconductor, Inc... The PLL filter is manually or automatically configurable into one of two operating modes: 1. Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. See 10.6.2 PLL Bandwidth Control Register. 2. Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See 10.4.3 Base Clock Selector Circuit. The PLL is automatically in tracking mode when it’s not in acquisition mode or when the ACQ bit is set. 10.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 10.6.2 PLL Bandwidth Control Register. If PLL CPU interrupt requests are enabled, the software can wait for a PLL CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See 10.4.3 Base Clock Selector Circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. See 10.7 Interrupts. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Freescale Semiconductor, Inc... These conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (see 10.6.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the filter. See 10.4.2.2 Acquisition and Tracking Modes. • The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆TRK, and is cleared when the VCO frequency is out of a certain tolerance, ∆UNT. See 24.2 Maximum Ratings. • The LOCK bit is a read-only indicator of the locked state of the PLL. • The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared when the VCO frequency is out of a certain tolerance, ∆unl. See 24.2 Maximum Ratings. • CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. See 10.6.1 PLL Control Register. The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX and require fast startup. These conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tacq (see 24.2 Maximum Ratings), after turning on the PLL by setting PLLON in the PLL control register (PCTL). • Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). • The LOCK bit is disabled. • CPU interrupts from the CGM are disabled. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 10.4.2.4 Programming the PLL Use this 9-step procedure to program the PLL. Table 10-1 lists the variables used and their meaning. Table 10-1. Variable Definitions Freescale Semiconductor, Inc... Variable Definition fBUSDES Desired bus clock frequency fVCLKDES Desired VCO clock frequency fRCLK Chosen reference crystal frequency fVCLK Calculated VCO clock frequency fBUS Calculated bus clock frequency fNOM Nominal VCO center frequency fVRS Shifted VCO center frequency 1. Choose the desired bus frequency, fBUSDES. Example: fBUSDES = 8 MHz 2. Calculate the desired VCO frequency, fVCLKDES. fVCLKDES = 4 × fBUSDES Example: fVCLKDES = 4 × 8 MHz = 32 MHz 3. Using a reference frequency, fRCLK, equal to the crystal frequency, calculate the VCO frequency multiplier, N. Round the result to the nearest integer. fVCLKDES N = ---------------------fRCLK 32 MHz Example: N = -------------------- = 8 4 MHz 4. Calculate the VCO frequency, fVCLK. f VCLK = N × f RCLK Example: fVCLK = 8 × 4 MHz = 32 MHz MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) 5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES. f VCLK f BUS = ------------4 32 MHz Example: f BUS = -------------------- = 8 MHz 4 Freescale Semiconductor, Inc... 6. If the calculated fBUS is not within the tolerance limits of the application, select another fBUSDES or another fRCLK. 7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL. f VCLK L = round ------------- f NOM Example: L = 32 MHz -------------------------------- = 7 4.9152 MHz 8. Calculate the VCO center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. fVRS = L × fNOM Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz NOTE: f NOM For proper operation, f VRS – f VCLK ≤ ---------------- . 2 Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent of N. b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 10.4.2.5 Special Programming Exceptions Freescale Semiconductor, Inc... The programming method, described in 10.4.2.4 Programming the PLL, does not account for two possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for N is interpreted the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See 10.4.3 Base Clock Selector Circuit. 10.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.4.4 CGM External Connections In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. Freescale Semiconductor, Inc... The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 10-3. Figure 10-3 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: 1. Crystal, X1 2. Fixed capacitor, C1 3. Tuning capacitor, C2 (can also be a fixed capacitor) 4. Feedback resistor, RB 5. Series resistor, RS (optional) The series resistor (RS) may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information. Figure 10-3 also shows the external components for the PLL: 1. Bypass capacitor, CBYP 2. Filter capacitor, CF Routing should be done with great care to minimize signal cross talk and noise. See 10.10 Acquisition/Lock Time Specifications for routing information and more information on the filter capacitor’s value and its effects on PLL performance. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) I/O Signals SIMOSCEN RS* VDDA CGMXFC VSS OSC2 OSC1 CGMXCLK VDD CF CBYP RB Freescale Semiconductor, Inc... X1 C1 C2 *RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. Figure 10-3. CGM External Connections 10.5 I/O Signals The following paragraphs describe the CGM input/output (I/O) signals. 10.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 10.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 10.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the CF connection. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.5.4 Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. Freescale Semiconductor, Inc... 10.5.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal enables the oscillator and PLL. 10.5.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 10-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup. 10.5.7 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 10.5.8 CGM CPU Interrupt (CGMINT) CGMINT is the CPU interrupt signal generated by the PLL lock detector. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers 10.6 CGM Registers Three registers control and monitor operation of the CGM: 1. PLL control register (PCTL) 2. PLL bandwidth control register (PBWC) 3. PLL programming register (PPG) Freescale Semiconductor, Inc... 10.6.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. Address: $001C Bit 7 Read: Write: Reset: 6 5 4 PLLON BCS 1 0 PLLF PLLIE 0 0 3 2 1 Bit 0 1 1 1 1 1 1 1 1 = Unimplemented Figure 10-4. PLL Control Register (PCTL) PLLIE — PLL Interrupt Enable Bit This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL CPU interrupt requests enabled 0 = PLL CPU interrupt requests disabled PLLF — PLL Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON — PLL On Bit Freescale Semiconductor, Inc... This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See 10.4.3 Base Clock Selector Circuit. Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS — Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See 10.4.3 Base Clock Selector Circuit. Reset and the STOP instruction clear the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT. 0 = CGMXCLK divided by two drives CGMOUT. NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See 10.4.3 Base Clock Selector Circuit. PCTL3–PCTL0 — Unimplemented These bits provide no function and always read as logic 1s. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers 10.6.2 PLL Bandwidth Control Register Freescale Semiconductor, Inc... The PLL bandwidth control register (PBWC): • Selects automatic or manual (software-controlled) bandwidth control mode • Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode Address: $001D Bit 7 Read: 6 5 4 ACQ XLD 0 0 LOCK AUTO 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: 0 0 = Unimplemented Figure 10-5. PLL Bandwidth Control Register (PBWC) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. Freescale Semiconductor, Inc... In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. 1 = Crystal reference not active 0 = Crystal reference active To check the status of the crystal reference: 1. Write a logic 1 to XLD. 2. Wait N × 4 cycles. N is the VCO frequency multiplier. 3. Read XLD. The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as logic 0. Bits 3–0 — Reserved for Test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write 0s to bits 3–0 when writing to PBWC. Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers 10.6.3 PLL Programming Register The PLL programming register (PPG) contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO. Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 Read: Freescale Semiconductor, Inc... Write: Reset: Figure 10-6. PLL Programming Register (PPG) MUL7–MUL4 — Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. (See 10.4.2.1 Circuits and 10.4.2.4 Programming the PLL.) A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6. Table 10-2. VCO Frequency Multiplier (N) Selection NOTE: MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) VRS7–VRS4 — VCO Range Select Bits Freescale Semiconductor, Inc... These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, fVRS. (See 10.4.2.1 Circuits, 10.4.2.4 Programming the PLL, and 10.6.1 PLL Control Register.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control register (PCTL) is set. See 10.4.2.5 Special Programming Exceptions. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. (See 10.4.3 Base Clock Selector Circuit and 10.4.2.5 Special Programming Exceptions for more information.) Reset initializes the bits to $6 to give a default range multiply value of 6. NOTE: The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. 10.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Low-Power Modes service routines from impeding software performance or from exceeding stack limitations. NOTE: Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. Freescale Semiconductor, Inc... 10.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 10.8.1 Wait Mode The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 10.8.2 Stop Mode The STOP instruction disables the CGM and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If CGMOUT is being driven by CGMVCLK and a STOP instruction is executed, the PLL will clear the BCS bit in the PLL control register, causing CGMOUT to be driven by CGMXCLK. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. 10.9 CGM During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Section 12. Break Module. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. Freescale Semiconductor, Inc... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. 10.10 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 10.10.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5 percent of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5 percent of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Acquisition/Lock Time Specifications a certain tolerance of the desired frequency regardless of the size of the initial error. Freescale Semiconductor, Inc... The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are: • Acquisition time, tACQ, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆trk. Acquisition time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic bandwidth control mode (see 10.4.2.3 Manual and Automatic PLL Bandwidth Modes), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). • Lock time, tLock, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ∆Lock. Lock time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). See 10.4.2.3 Manual and Automatic PLL Bandwidth Modes. Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 10.10.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Freescale Semiconductor, Inc... Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See 10.10.3 Choosing a Filter Capacitor. Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 10.10.3 Choosing a Filter Capacitor As described in 10.10.2 Parametric Influences on Reaction Time, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to this equation: V DDA C F = C Fact -----------f RDV Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clock Generator Module (CGM) Acquisition/Lock Time Specifications Freescale Semiconductor, Inc... For acceptable values of CFact, see 24.2 Maximum Ratings. For the value of VDDA, choose the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the middle of the range of possible supply values. This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance (±20 percent or better) and low dissipation. MC68HC908AS60 — Rev. 1.0 Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Clock Generator Module (CGM) Technical Data MC68HC908AS60 — Rev. 1.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 11. Configuration Register (CONFIG-1) Freescale Semiconductor, Inc... 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.2 Introduction This section describes the configuration register (CONFIG-1), which contains bits that configure these options: • Resets caused by the low-voltage inhibit (LVI) module • Power to the LVI module • LVI enabled during stop mode • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • Computer operating properly (COP) module • STOP instruction enable/disable 11.3 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read the default value. Once the register is written, further writes will have no effect until a reset occurs. NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs when VDD falls to a voltage, LVITRIPF, and remains at or below that level for at least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU remains in reset until VDD rises to a voltage, LVITRIPR. MC68HC908AS60 — Rev. 1.0 Technical Data Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 LVISTOP R LVIRST LVIPWR SSREC COPL STOP COPD 0 1 1 1 0 0 0 0 Read: Write: Reset: R = Reserved Freescale Semiconductor, Inc... Figure 11-1. Configuration Write-Once Register (CONFIG-1) LVISTOP — LVI Stop Mode Enable Bit LVISTOP enables the LVI module in stop mode. See Section 15. Low-Voltage Inhibit (LVI) Module. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode NOTE: To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1 and the LVISTOP bit must be at a logic 1. Take note that by enabling the LVI in stop mode, the stop IDD current will be higher and for compatibility when using a MC68HC08AS20 a register bit will have to be written. See the LVI section of the MC68HC08AS20 Advance Information (Motorola document order number MC68HC08AS20/D.) LVIRST — LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. See Section 15. Low-Voltage Inhibit (LVI) Module. 1 = LVI module resets enabled 0 = LVI module resets disabled LVIPWR — LVI Power Enable Bit LVIPWR enables the LVI module. See Section 15. Low-Voltage Inhibit (LVI) Module. 1 = LVI module power enabled 0 = LVI module power disabled Technical Data MC68HC908AS60 — Rev. 1.0 Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) Functional Description SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. See 9.7.2 Stop Mode. 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles NOTE: If using an external crystal oscillator, do not set the SSREC bit. Freescale Semiconductor, Inc... COPL — COP Long Timeout Bit COPL enables the shorter COP timeout period. See Section 14. Computer Operating Properly (COP) Module. 1 = COP timeout period is 8,176 CGMXCLK cycles. 0 = COP timeout period is 262,128 CGMXCLK cycles. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See Section 14. Computer Operating Properly (COP) Module. 1 = COP module disabled 0 = COP module enabled WARNING: Extra care should be exercised when using this emulation part for development of code to be run in ROM-based M68HC08AS Family parts that the options selected by setting the CONFIG-1 register match exactly the options selected on any ROM code request submitted. The enable/disable logic is not necessarily identical in all parts of the AS Family. If there is any doubt, check with a local field applications representative. MC68HC908AS60 — Rev. 1.0 Technical Data Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) The bit in the CONFIG register or MOR (mask option register) used to control the short and long COP timeout has some variation within the A-Family of devices. Table 11-1 is intended to clarify bit 2 within the CONFIG or MOR of a FLASH or ROM device, respectively. Table 11-1. COP Time Clarification Device Freescale Semiconductor, Inc... MC68HC908AS60 MC68HC908AZ60 MC68HC08AS32 MC68HC08AS20 Register/Bit Location Bit Name CONFIG-1/bit 2 COPL CONFIG-1/bit 2 MOR/bit 2 MOR/bit 2 Value Definition 1 Short COP timeout 0 Long COP timeout 1 Short COP timeout 0 Long COP timeout 1 Short COP timeout 0 Long COP timeout 1 Short COP timeout 0 Long COP timeout COPL COPRS COPL Definition: Short COP timeout: 8,176 CGMXCLK cycles Long COP timeout: 262,128 CGMXCLK cycles CGMXCLK is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. Technical Data MC68HC908AS60 — Rev. 1.0 Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 12. Break Module Freescale Semiconductor, Inc... 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 187 12.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .187 12.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .188 12.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 12.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.6.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . .189 12.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.2 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 12.3 Features Features of the break module include: • Accessible input/output (I/O) registers during break interrupts • CPU-generated break interrupts • Software-generated break interrupts • Computer operating properly (COP) disabling during break interrupts MC68HC908AS60 — Rev. 1.0 Technical Data Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Break Module 12.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). Freescale Semiconductor, Inc... These two events can cause a break interrupt to occur: • A CPU-generated address (the address in the program counter) matches the contents of the break address registers. • Software writes a logic 1 to the BRKA bit in the break status and control register. When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 12-1 shows the structure of the break module. IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 12-1. Break Module Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Break Module Functional Description Addr. $FE0C Freescale Semiconductor, Inc... $FE0D $FE0E Register Name Read: Break Address Register High (BRKH) Write: See page 190. Reset: Read: Break Address Register Low (BRKL) Write: See page 190. Reset: Read: Break Status and Control Register (BSCR) Write: See page 189. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 = Unimplemented Figure 12-2. I/O Register Summary 12.4.1 Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. 12.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 12.4.3 TIM During Break Interrupts A break interrupt stops the timer counter. MC68HC908AS60 — Rev. 1.0 Technical Data Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Break Module 12.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VHI is present on the RST pin. 12.5 Low-Power Modes Freescale Semiconductor, Inc... The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 12.5.1 Wait Mode If enabled, the break module is active in wait mode. The SIM break stop/wait bit (SBSW) in the SIM break status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return address on the stack by subtracting one from it. (See 9.8.1 SIM Break Status Register.) 12.5.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. A break interrupt will cause an exit from stop mode and sets the SBSW bit in the SIM break status register. 12.6 Break Module Registers These registers control and monitor operation of the break module: • Break address register high, BRKH • Break address register low, BRKL • Break status and control register, BSCR Technical Data MC68HC908AS60 — Rev. 1.0 Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Break Module Break Module Registers 12.6.1 Break Status and Control Register The break status and control register (BSCR) contains break module enable and status bits. Address: $FE0E Bit 7 6 BRKE BRKA 0 0 Read: 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Write: Reset: = Unimplemented Figure 12-3. Break Status and Control Register (BSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = When read, break address match 0 = When read, no break address match MC68HC908AS60 — Rev. 1.0 Technical Data Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Break Module 12.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register Name and Address: BRKH — $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read: Write: Reset: Register Name and Address: BRKL — $FE0D Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: Figure 12-4. Break Address Registers (BRKH and BRKL) Technical Data MC68HC908AS60 — Rev. 1.0 Break Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 13. Monitor ROM (MON) Freescale Semiconductor, Inc... 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 13.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 13.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 13.4.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.2 Introduction This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) 13.3 Features Freescale Semiconductor, Inc... Features of the monitor ROM include: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • 4800 baud–28.8 Kbaud communication with host computer • Execution of code in RAM or FLASH • FLASH security • FLASH programming 13.4 Functional Description Monitor ROM receives and executes commands from a host computer. Figure 13-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. While simple monitor commands can access any memory address, the MC68HC908AS60 has a FLASH security feature to prevent external viewing of the contents of FLASH. Proper procedures must be followed to verify FLASH content. Access to the FLASH is denied to unauthorized users of customer-specified software (see 13.4.7 Security). In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0 retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description VDD 10 kΩ M68HC08 RST 0.1 µ F VHI 10 Ω Freescale Semiconductor, Inc... IRQ VDDA VDDA/VDDAREF CGMXFC 1 10 µF + MC145407 3 0.022 µF 20 + 10 µF OSC1 18 20 pF 4 10 µF 17 + + 2 10 µF X1 4.9152 MHz 10 MΩ OSC2 VDD 20 pF 19 VSSA VSS DB-25 2 5 16 3 6 15 VDD VDD 0.1 µF 7 VDD 1 MC74HC125 2 3 6 5 4 7 Notes: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 VDD 14 10 kΩ PTA0 PTC3 VDD VDD 10 kΩ A (SEE NOTE.) 10 kΩ B PTC0 PTC1 Figure 13-1. Monitor Mode Circuit MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) 13.4.1 Entering Monitor Mode Table 13-1 shows the pin conditions for entering monitor mode. PTC1 Pin PTA0 Pin PTC3 Pin Mode VHI(1) 1 0 1 1 Monitor CGMVCLK CGMXCLK ----------------------------- or ----------------------------2 2 CGMOUT -------------------------2 VHI(1) 1 0 1 0 Monitor CGMXCLK CGMOUT -------------------------2 Freescale Semiconductor, Inc... IRQ Pin PTC0 Pin Table 13-1. Mode Selection CGMOUT Bus Frequency 1. For VHI, see 24.5 5.0 Volt DC Electrical Characteristics and 24.2 Maximum Ratings. Enter monitor mode by either: • Executing a software interrupt instruction (SWI), or • Applying a logic 0 and then a logic 1 to the RST pin Once out of reset, the MCU waits for the host to send eight security bytes (see 13.4.7 Security). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. The COP module is disabled in monitor mode as long as VHI (see 24.5 5.0 Volt DC Electrical Characteristics), is applied to either the IRQ pin or the RST pin. See Section 9. System Integration Module (SIM) for more information on modes of operation. NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50 percent duty cycle at maximum bus frequency. Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 13-2 is a summary of the differences between user mode and monitor mode. Table 13-2. Mode Differences Functions Freescale Semiconductor, Inc... Modes COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 1. If the high voltage (VHI) is removed from the IRQ pin while in monitor mode, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. See 24.5 5.0 Volt DC Electrical Characteristics. 13.4.2 Data Format Communication with the MON is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 13-2 and Figure 13-3.) The data transmit and receive rate can be anywhere from 4800 baud to 28.8 Kbaud. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 13-2. Monitor Data Format $A5 START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BREAK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT STOP BIT NEXT START BIT NEXT START BIT Figure 13-3. Sample Monitor Waveforms MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) 13.4.3 Echoing As shown in Figure 13-4, the MON immediately echoes each received byte back to the PTA0 pin for error checking. Freescale Semiconductor, Inc... Any result of a command appears after the echo of the last byte of the command. SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT Figure 13-4. Read Transaction 13.4.4 Break Signal A start bit followed by nine low bits is a break signal. See Figure 13-5. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 13-5. Break Transaction Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description 13.4.5 Commands Freescale Semiconductor, Inc... The monitor ROM uses these commands: • READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 13-3. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW ECHO DATA RESULT Table 13-4. WRITE (Write Memory) Command Description Write byte to memory Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA ECHO MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Table 13-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR Freescale Semiconductor, Inc... IREAD IREAD DATA DATA RESULT ECHO Table 13-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE DATA DATA ECHO Table 13-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP ECHO READSP SP HIGH SP LOW RESULT Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 13-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR Freescale Semiconductor, Inc... RUN RUN ECHO 13.4.6 Baud Rate With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. If the PTC3 pin is at logic 0 during reset, the monitor baud rate is 9600. When the CGM output, CGMOUT, is driven by the PLL, the baud rate is determined by the MUL[7:4] bits in the PLL programming register (PPG). See Section 10. Clock Generator Module (CGM). Table 13-9. Monitor Baud Rate Selection Monitor Baud Rate VCO Frequency Multiplier (N) 1 2 3 4 5 6 4.9152 MHz 4800 9600 14,400 19,200 24,000 28,800 4.194 MHz 4096 8192 12,288 16,384 20,480 24,576 13.4.7 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. If FLASH is unprogrammed, the eight security byte values to be sent are $FF, the unprogrammed state of FLASH. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0. Freescale Semiconductor, Inc... VDD 4096 + 32 CGMXCLK CYCLES RST 24 CGMXCLK CYCLES PA7 COMMAND BYTE 8 BYTE 2 BYTE 1 256 CGMXCLK CYCLES (ONE BIT TIME) FROM HOST PA0 4 BREAK 2 1 COMMAND ECHO Notes: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte. 1 BYTE 8 ECHO BYTE 1 ECHO FROM MCU 1 BYTE 2 ECHO 4 1 Figure 13-6. Monitor Mode Entry Timing If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. If the reset was not a power-on reset, the security remains bypassed regardless of the data that the host sends. If the received bytes do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description mode, but reading FLASH locations returns undefined data, and trying to execute code from FLASH causes an illegal address reset. After the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. The MCU does not transmit a break character until after the host sends the eight security bytes. Freescale Semiconductor, Inc... NOTE: MC68HC908AS60 — Rev. 1.0 Technical Data Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Monitor ROM (MON) Technical Data MC68HC908AS60 — Rev. 1.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 14. Computer Operating Properly (COP) Module Freescale Semiconductor, Inc... 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 14.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 14.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 14.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.7 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.4.8 COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 14.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .208 14.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. MC68HC908AS60 — Rev. 1.0 Technical Data Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module 14.3 Functional Description The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 8,176 or 262,128 CGMXCLK cycles, depending on the state of the COP long timeout bit, COPL, in the CONFIG-1. COP timeout period = 8,176 or 22,128 / fOSC Freescale Semiconductor, Inc... When COPL = 1, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 4–12 of the SIM counter. NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at VHI. During the break state, VHI on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. Technical Data MC68HC908AS60 — Rev. 1.0 Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module I/O Signals 14.4 I/O Signals This subsection describes the signals shown in Figure 14-1. 12-BIT COP PRESCALER CLEAR STAGES 4–12 STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH CLEAR ALL STAGES Freescale Semiconductor, Inc... CGMXCLK COPCTL WRITE RESET RESET STATUS REGISTER 6-BIT COP COUNTER COPD FROM CONFIG-1 RESET COPCTL WRITE CLEAR COP COUNTER COPL FROM CONFIG-1 Figure 14-1. COP Block Diagram 14.4.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency. 14.4.2 STOP Instruction The STOP instruction clears the COP prescaler. MC68HC908AS60 — Rev. 1.0 Technical Data Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module 14.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 14.5 COP Control Register) clears the COP counter and clears stages 12 through 4 of the COP prescaler. Reading the COP control register returns the reset vector. Freescale Semiconductor, Inc... 14.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 14.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 14.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 14.4.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Section 11. Configuration Register (CONFIG-1). 14.4.8 COPL The COPL signal reflects the state of the COP rate select bit (COPL) in the configuration register. See Section 11. Configuration Register (CONFIG-1). Technical Data MC68HC908AS60 — Rev. 1.0 Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module COP Control Register 14.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Freescale Semiconductor, Inc... Bit 7 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 14-2. COP Control Register (COPCTL) 14.6 Interrupts The COP does not generate CPU interrupt requests. 14.7 Monitor Mode The COP is disabled in monitor mode when VHI is present on the IRQ pin or on the RST pin. 14.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 14.8.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68HC908AS60 — Rev. 1.0 Technical Data Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module 14.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. Freescale Semiconductor, Inc... The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 14.9 COP Module During Break Interrupts The COP is disabled during a break interrupt when VHI is present on the RST pin. Technical Data MC68HC908AS60 — Rev. 1.0 Computer Operating Properly (COP) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 15. Low-Voltage Inhibit (LVI) Module Freescale Semiconductor, Inc... 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 15.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 15.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 15.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 15.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 15.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 15.2 Introduction This section describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage. MC68HC908AS60 — Rev. 1.0 Technical Data Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Module 15.3 Features Freescale Semiconductor, Inc... Features of the LVI module include: • Programmable LVI reset • Programmable power consumption • Digital filtering of VDD pin level 15.4 Functional Description Figure 15-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD falls below a voltage, LVITRIPF, and remains at or below that level for nine or more consecutive CPU cycles. LVISTOP enables the LVI module during stop mode. This will ensure when the STOP instruction is implemented, and the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST are in the configuration register (CONFIG-1). See Section 11. Configuration Register (CONFIG-1). VDD LVIPWR FROM CONFIG-1 FROM CONFIG-1 CPU CLOCK LOW VDD DETECTOR VDD > LVITRIP = 0 LVIRST VDD DIGITAL FILTER LVI RESET VDD < LVITRIP = 1 STOP MODE FILTER BYPASS ANLGTRIP LVIOUT LVISTOP FROM CONFIG-1 Figure 15-1. LVI Module Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Module Functional Description Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. See 15.4.2 Forced Reset Operation. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). Freescale Semiconductor, Inc... An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. Addr. $FE0F Register Name Bit 7 Read: LVIOUT LVI Status Register (LVISR) Write: See page 212. Reset: 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-2. LVI I/O Register Summary 15.4.1 Polled LVI Operation In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST bit must be at logic 0 to disable LVI resets. 15.4.2 Forced Reset Operation In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for nine or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at logic 1 to enable the LVI module and to enable LVI resets. MC68HC908AS60 — Rev. 1.0 Technical Data Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Module 15.4.3 False Reset Protection The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI module to reset the MCU, VDD must remain at or below the LVITRIPF level for nine or more consecutive CPU cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. Freescale Semiconductor, Inc... 15.5 LVI Status Register The LVI status register (LVISR) flags VDD voltages below the LVITRIPF level. Address: $FE0F Bit 7 Read: LVIOUT 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: 0 = Unimplemented Figure 15-3. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the LVITRIPF voltage for 32 to 40 CGMXCLK cycles. See Table 15-1. Reset clears the LVIOUT bit. Table 15-1. LVIOUT Bit Indication VDD At Level: For Number of CGMXCLK Cycles: LVIOUT VDD > LVITRIPR Any 0 VDD < LVITRIPF < 32 CGMXCLK cycles 0 VDD < LVITRIPF Between 32 and 40 CGMXCLK Ccycles 0 or 1 VDD < LVITRIPF > 40 CGMXCLK cycles 1 LVITRIPF < VDD < LVITRIPR Any Previous value Technical Data MC68HC908AS60 — Rev. 1.0 Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Module LVI Interrupts 15.6 LVI Interrupts The LVI module does not generate interrupt requests. 15.7 Low-Power Modes Freescale Semiconductor, Inc... The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 15.7.1 Wait Mode With the LVIPWR bit in the configuration register programmed to logic 1, the LVI module is active after a WAIT instruction. With the LVIRST bit in the configuration register programmed to logic 1, the LVI module can generate a reset and bring the MCU out of wait mode. 15.7.2 Stop Mode With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 1, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter to generate a reset and bring the MCU out of stop. With the LVIPWR bit in the configuration register programmed to logic 1 and the LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP instruction. MC68HC908AS60 — Rev. 1.0 Technical Data Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Low-Voltage Inhibit (LVI) Module Technical Data MC68HC908AS60 — Rev. 1.0 Low-Voltage Inhibit (LVI) Module For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 16. External Interrupt Module (IRQ) Freescale Semiconductor, Inc... 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 16.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 220 16.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 220 16.2 Introduction This section describes the non-maskable external interrupt (IRQ) input. 16.3 Features Features include: • Dedicated external interrupt pin (IRQ) • Hysteresis buffer • Programmable edge-only or edge- and level-interrupt sensitivity • Automatic interrupt acknowledge MC68HC908AS60 — Rev. 1.0 Technical Data External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) 16.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 16-1 shows the structure of the IRQ module. • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. • Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK1 bit clears the IRQ1 latch. • Reset — A reset automatically clears both interrupt latches. ACK1 INTERNAL ADDRESS BUS Freescale Semiconductor, Inc... Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs: TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD IRQ1F D CLR Q SYNCHRONIZER CK IRQ IRQ1 INTERRUPT REQUEST IRQ1 LATCH IMASK1 MODE1 HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 16-1. IRQ Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) Functional Description Addr. $001A Register Name Bit 7 6 5 4 3 2 Read: IRQ Status and Control Register (ISCR) Write: See page 220. Reset: 0 0 0 0 IRQF1 0 R R R R R ACK1 0 0 0 0 0 0 R 1 Bit 0 IMASK1 MODE1 0 0 = Reserved Freescale Semiconductor, Inc... Figure 16-2. IRQ I/O Register Summary The external interrupt pin is falling-edge triggered and is softwareconfigurable to be both falling-edge and low-level triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See Figure 16-3.) MC68HC908AS60 — Rev. 1.0 Technical Data External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) FROM RESET YES I BIT SET? NO Freescale Semiconductor, Inc... INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 16-3. IRQ Interrupt Flowchart Technical Data MC68HC908AS60 — Rev. 1.0 External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) IRQ Pin 16.5 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch. Freescale Semiconductor, Inc... If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE1 set, both of the following actions must occur to clear the IRQ1 latch: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ pin. A falling edge on IRQ that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. • Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set. The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. If the MODE1 bit is clear, the IRQ pin is falling-edge sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch. The IRQF1 bit in ISCR can be used to check for pending interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. MC68HC908AS60 — Rev. 1.0 Technical Data External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) 16.6 IRQ Module During Break Interrupts Freescale Semiconductor, Inc... The system integration module (SIM) controls whether the IRQ1 interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latches during the break state. See 9.8.3 SIM Break Flag Control Register. To allow software to clear the IRQ1 latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect on the IRQ latch. 16.7 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has these functions: • Shows the state of the IRQ1 interrupt flag • Clears the IRQ1 interrupt latch • Masks IRQ1 interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Address: $001A Bit 7 6 5 4 3 2 Read: 0 0 0 0 IRQF1 0 Write: R R R R R ACK1 Reset: 0 0 0 0 0 0 R 1 Bit 0 IMASK1 MODE1 0 0 = Reserved Figure 16-4. IRQ Status and Control Register (ISCR) Technical Data MC68HC908AS60 — Rev. 1.0 External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Interrupt Module (IRQ) IRQ Status and Control Register IRQ1F — IRQ1 Flag Bit This read-only status bit is high when the IRQ1 interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic 0. Reset clears ACK1. Freescale Semiconductor, Inc... IMASK1 — IRQ1 Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1. 1 = IRQ1 interrupt requests disabled 0 = IRQ1 interrupt requests enabled MODE1 — IRQ1 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE1. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908AS60 — Rev. 1.0 Technical Data External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... External Interrupt Module (IRQ) Technical Data MC68HC908AS60 — Rev. 1.0 External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 17. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 17.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 17.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .231 17.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 231 17.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 17.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 241 17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.8.1 PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . 241 17.8.2 PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . 242 MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... 17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 17.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 17.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.2 Introduction The serial communications interface (SCI) allows asynchronous communications with peripheral devices and other MCUs. 17.3 Features The SCI module’s features include: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • 32 programmable baud rates • Programmable 8-bit or 9-bit character length • Separately enabled transmitter and receiver • Separate receiver and transmitter CPU interrupt requests • Programmable transmitter output polarity • Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Pin Name Conventions • Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun Freescale Semiconductor, Inc... – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection 17.4 Pin Name Conventions The generic names of the SCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 17-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 17-1. Pin Name Conventions Generic Pin Names RxD TxD Full Pin Names PTE1/SCRxD PTE0/SCTxD MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.5 Functional Description Figure 17-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. ERROR INTERRUPT CONTROL RECEIVE SHIFT REGISTER RxD SCI DATA REGISTER RECEIVER INTERRUPT CONTROL SCI DATA REGISTER TRANSMITTER INTERRUPT CONTROL Freescale Semiconductor, Inc... INTERNAL BUS TRANSMIT SHIFT REGISTER TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE TE SCTE RE TC RWU SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL ENSCI ENSCI TRANSMIT CONTROL FLAG CONTROL BKF M RPF WAKE ILTY CGMXCLK ÷4 PRESCALER BAUD RATE GENERATOR ÷ 16 PEN PTY DATA SELECTION CONTROL Figure 17-1. SCI Module Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Addr. $0013 Freescale Semiconductor, Inc... $0014 $0015 $0016 $0017 $0018 $0019 Register Name Bit 7 6 5 4 3 2 1 Bit 0 ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 T8 R R ORIE NEIE FEIE PEIE Read: SCI Control Register 1 LOOPS (SCC1) Write: See page 243. Reset: 0 Read: SCI Control Register 2 (SCC2) Write: See page 246. Reset: Read: SCI Control Register 3 (SCC3) Write: See page 248. Reset: R8 U U 0 0 0 0 0 0 Read: SCI Status Register 1 (SCS1) Write: See page 250. Reset: SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 BKF RPF Read: SCI Status Register 2 (SCS2) Write: See page 253. Reset: Read: SCI Data Register (SCDR) Write: See page 254. Reset: Read: SCI Baud Rate Register (SCBR) Write: See page 255. Reset: 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 Unaffected by reset 0 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected Figure 17-2. SCI I/O Register Summary MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 17-3. 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 PARITY OR DATA BIT BIT 6 Freescale Semiconductor, Inc... 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 17-3. SCI Data Formats 17.5.2 Transmitter Figure 17-4 shows the structure of the SCI transmitter. 17.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 17.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description INTERNAL BUS ÷ 16 SCI DATA REGISTER SCP1 SCP0 SCR1 H SCR2 8 7 6 5 4 3 2 START 11-BIT TRANSMIT SHIFT REGISTER STOP CGMXCLK BAUD DIVIDER PRESCALER ÷4 1 0 L TxD MSB TRANSMITTER CPU INTERRUPT REQUEST TXINV PARITY GENERATION T8 BREAK (ALL 0s) PTY PREAMBLE (ALL 1s) PEN SHIFT ENABLE M LOAD FROM SCDR Freescale Semiconductor, Inc... SCR0 TRANSMITTER CONTROL LOGIC SCTE SCTE SCTIE TC TCIE SBK LOOPS SCTIE ENSCI TC TE TCIE Figure 17-4. SCI Transmitter At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. Freescale Semiconductor, Inc... 17.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the SCI receiver full bit (SCRF) in SCS1 • Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception-in-progress flag (RPF) bits 17.5.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. Freescale Semiconductor, Inc... NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR. 17.5.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. See 17.9.1 SCI Control Register 1. 17.5.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter: • SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. • Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.5.3 Receiver Figure 17-5 shows the structure of the SCI receiver. INTERNAL BUS SCR1 SCR2 SCP0 SCR0 BAUD DIVIDER ÷ 16 DATA RECOVERY RxD CPU INTERRUPT REQUEST ALL 1s M ILTY PEN PTY 8 7 6 5 4 3 2 1 0 L ALL 0s RPF WAKE H 11-BIT RECEIVE SHIFT REGISTER MSB BKF STOP PRESCALER CGMXCLK ERROR CPU INTERRUPT REQUEST Freescale Semiconductor, Inc... ÷4 SCI DATA REGISTER START SCP1 SCRF WAKEUP LOGIC IDLE R8 PARITY CHECKING IDLE ILIE SCRF SCRIE ILIE SCRIE OR ORIE OR ORIE NF NEIE NF NEIE FE FEIE FE FEIE PE PEIE RWU PE PEIE Figure 17-5. SCI Receiver Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description 17.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). Freescale Semiconductor, Inc... 17.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 17.5.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 17-6): • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) START BIT RxD START BIT QUALIFICATION SAMPLES LSB START BIT DATA VERIFICATION SAMPLING RT CLOCK STATE RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT CLOCK Freescale Semiconductor, Inc... RT CLOCK RESET Figure 17-6. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 17-2 summarizes the results of the start bit verification samples. Table 17-2. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 17-3 summarizes the results of the data bit samples. Freescale Semiconductor, Inc... Table 17-3. Data Bit Recovery NOTE: RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 17-4 summarizes the results of the stop bit samples. Table 17-4. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.5.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. Freescale Semiconductor, Inc... 17.5.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 17-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 17-7. Slow Data Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 17-7, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 17-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.12% -------------------------170 Fast Data Tolerance Figure 17-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RECEIVER RT CLOCK RT1 Freescale Semiconductor, Inc... 154 – 147 × 100 = 4.54% -------------------------154 DATA SAMPLES Figure 17-8. Fast Data MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 17-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. Freescale Semiconductor, Inc... The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 – 160 × 100 = 3.90% -------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 17-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 × 100 = 3.53% -------------------------170 17.5.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. Freescale Semiconductor, Inc... • NOTE: Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 17.5.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the SCI receiver: • SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. • Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests. 17.5.3.8 Error Interrupts These receiver error flags in SCS1 can generate CPU interrupt requests: • Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. • Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. 17.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 17.6.1 Wait Mode The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 17.6.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI During Break Module Interrupts Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. 17.7 SCI During Break Module Interrupts Freescale Semiconductor, Inc... The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See Section 12. Break Module.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 17.8 I/O Signals Port E shares two of its pins with the SCI module. The two SCI I/O pins are: 1. PTE0/SCTxD — Transmit data 2. PTE1/SCRxD — Receive data 17.8.1 PTE0/SCTxD (Transmit Data) The PTE0/SCTxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/SCTxD pin with port E. When the SCI is enabled, the PTE0/SCTxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE). MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.8.2 PTE1/SCRxD (Receive Data) The PTE1/SCRxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled, the PTE1/SCRxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). Freescale Semiconductor, Inc... 17.9 I/O Registers These I/O registers control and monitor SCI operation: • SCI control register 1 (SCC1) • SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) 17.9.1 SCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 17-9. SCI Control Register 1 (SCC1) Freescale Semiconductor, Inc... LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 17-5.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit Freescale Semiconductor, Inc... This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit. 0 = Idle character bit count begins after start bit. PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 17-5.) When enabled, the parity function inserts a parity bit in the most significant bit position. (See Table 17-4.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 17-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Table 17-5. Character Format Selection Freescale Semiconductor, Inc... Control Bits Character Format M PEN:PTY Start Bits Data Bits Parity Stop Bits Character Length 0 0X 1 8 None 1 10 Bits 1 0X 1 9 None 1 11 Bits 0 10 1 7 Even 1 10 Bits 0 11 1 7 Odd 1 10 Bits 1 10 1 8 Even 1 11 Bits 1 11 1 8 Odd 1 11 Bits 17.9.2 SCI Control Register 2 SCI control register 2: • Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests • Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Address: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 17-10. SCI Control Register 2 (SCC2) Freescale Semiconductor, Inc... SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Freescale Semiconductor, Inc... TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK — Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted Freescale Semiconductor, Inc... NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. 17.9.3 SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts Address: $0015 Bit 7 Read: 6 5 4 3 2 1 Bit 0 T8 R R ORIE NEIE FEIE PEIE U 0 0 0 0 0 0 = Unimplemented R R8 Write: Reset: U = Reserved U = Unaffected Figure 17-11. SCI Control Register 3 (SCC3) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other eight bits. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. Freescale Semiconductor, Inc... ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 17.9.4 SCI Status Register 1 Freescale Semiconductor, Inc... SCI status register 1 contains flags to signal these conditions: • Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: Read: $0016 Bit 7 6 5 4 3 2 1 Bit 0 SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 17-12. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress Freescale Semiconductor, Inc... SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 17-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. Freescale Semiconductor, Inc... In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 BYTE 3 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 1 READ SCDR BYTE 3 Figure 17-13. Flag Clearing Sequence NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected Freescale Semiconductor, Inc... PE — Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected 17.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal these conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 17-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected Freescale Semiconductor, Inc... RPF — Reception-in-Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress 17.9.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 17-15. SCI Data Register (SCDR) R7/T7:R0/T0 — Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register. NOTE: Do not use read-modify-write instructions on the SCI data register. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers 17.9.7 SCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 6 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 = Unimplemented R Read: Freescale Semiconductor, Inc... Write: Reset: 0 0 = Reserved Figure 17-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 17-6. Reset clears SCP1 and SCP0. Table 17-6. SCI Baud Rate Prescaling SCP[1:0] Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCR2 – SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 17-7. Reset clears SCR2–SCR0. Freescale Semiconductor, Inc... Table 17-7. SCI Baud Rate Selection SCR[2:1:0] Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: f Crystal Baud rate = -----------------------------------64 × PD × BD where: fCrystal = crystal frequency PD = prescaler divisor BD = baud rate divisor Table 17-8 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Table 17-8. SCI Baud Rate Selection Examples Prescaler Divisor (PD) SCR[2:1:0] Baud Rate Divisor (BD) Baud Rate (fCrystal = 4.9152 MHz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 Freescale Semiconductor, Inc... SCP[1:0] MC68HC908AS60 — Rev. 1.0 Technical Data Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Communications Interface (SCI) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 18. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.4 Pin Name and Register Name Conventions . . . . . . . . . . . . . .261 18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 18.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 18.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .266 18.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 267 18.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 268 18.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 269 18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 18.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 276 18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 280 18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 280 MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 18.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 18.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18.13.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Freescale Semiconductor, Inc... 18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 285 18.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 18.2 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 18.3 Features Features of the SPI module include: • Full-duplex operation • Master and slave modes • Double-buffered operation with separate transmit and receive registers • Four master mode frequencies (maximum = bus frequency ÷ 2) • Maximum slave mode frequency = bus frequency • Serial clock with programmable polarity and phase • Two separately enabled interrupts with CPU service: – SPRF (SPI receiver full) – SPTE (SPI transmitter empty) • Mode fault error flag with CPU interrupt capability • Overflow error flag with CPU interrupt capability • Programmable wired-OR mode • I2C (inter-integrated circuit) compatibility Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Pin Name and Register Name Conventions 18.4 Pin Name and Register Name Conventions Freescale Semiconductor, Inc... The generic names of the SPI input/output (I/O) pins are: • SS (slave select) • SPSCK (SPI serial clock) • MOSI (master out/slave in) • MISO (master in/slave out) The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the shared port pin. Table 18-1 shows the full names of the SPI I/O pins. The generic pin names appear in the text that follows. Table 18-1. Pin Name Conventions SPI Generic Pin Name Full SPI Pin Name MISO MOSI SS SPSCK PTE5/MISO PTE6/MOSI PTE4/SS PTE7/SPSCK The generic names of the SPI I/O registers are: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) Table 18-2 shows the names and the addresses of the SPI I/O registers. Table 18-2. I/O Register Addresses Register Name Address SPI control register (SPCR) $0010 SPI status and control register (SPSCR) $0011 SPI data register (SPDR) $0012 MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 18.5 Functional Description Figure 18-1 summarizes the SPI I/O registers and Figure 18-2 shows the structure of the SPI module. Addr. Freescale Semiconductor, Inc... $0010 $0011 $0012 Register Name Bit 7 Read: SPI Control Register SPRIE (SPCR) Write: See page 283. Reset: 0 Read: SPI Status and Control Register (SPSCR) Write: See page 286. Reset: Read: SPI Data Register (SPDR) Write: See page 289. Reset: 6 5 4 3 2 1 Bit 0 R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 1 0 1 0 0 0 OVRF MODF SPTE MODFEN SPR1 SPR0 R R R SPRF ERRIE R 0 0 0 0 1 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 Unaffected by reset R = Reserved Figure 18-1. SPI I/O Register Summary The SPI module allows full-duplex, synchronous, serial communication among the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. All SPI interrupts can be serviced by the CPU. This subsection describes the operation of the SPI module. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUS CLOCK 7 6 5 4 3 2 1 MISO 0 ÷2 Freescale Semiconductor, Inc... CLOCK DIVIDER MOSI ÷8 RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR CLOCK SELECT SPE SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR TRANSMITTER CPU INTERRUPT REQUEST CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPRIE SPE SPRF SPTE OVRF MODF Figure 18-2. SPI Module Block Diagram 18.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set. NOTE: Configure the SPI modules as master and slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 18.14.1 SPI Control Register. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting out on the MOSI pin under the control of the serial clock. (See 18.8 Interrupts.) Freescale Semiconductor, Inc... The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 18.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF (SPSCR), becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit. MASTER MCU SHIFT REGISTER SLAVE MCU MISO MISO MOSI MOSI SHIFT REGISTER SPSCK BAUD RATE GENERATOR SS SPSCK VDD SS Figure 18-3. Full-Duplex Master-Slave Connections Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description 18.5.2 Slave Mode Freescale Semiconductor, Inc... The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010) is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave MCU must be at logic 0. SS must remain low until the transmission is complete. (See 18.7.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it is transferred to the receive data register, and the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave software then must read the SPI data register before another byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed, which is twice as fast as the fastest master SPSCK clock that can be generated. The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See 18.6 Transmission Formats.) MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission. NOTE: To prevent SPSCK from appearing as a clock edge, SPSCK must be in the proper idle state before the slave is enabled. Freescale Semiconductor, Inc... 18.6 Transmission Formats During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can be used optionally to indicate a multiple-master bus contention. 18.6.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit (SPCR) selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by clearing the SPI enable bit (SPE). Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats Freescale Semiconductor, Inc... 18.6.2 Transmission Format When CPHA = 0 Figure 18-4 shows an SPI transmission in which CPHA (SPCR) is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low again between each byte transmitted. SCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SCK CPOL = 0 SCK CPOL = 1 MOSI FROM MASTER MISO FROM SLAVE MSB SS TO SLAVE CAPTURE STROBE Figure 18-4. Transmission Format (CPHA = 0) MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... 18.6.3 Transmission Format When CPHA = 1 Figure 18-5 shows an SPI transmission in which CPHA (SPCR) is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. SCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MOSI FROM MASTER MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 SCK CPOL = 0 SCK CPOL = 1 LSB SS TO SLAVE CAPTURE STROBE Figure 18-5. Transmission Format (CPHA = 1) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions Freescale Semiconductor, Inc... 18.6.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The SPI clock rate (selected by SPR1–SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 18-6.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 18-6. This delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. 18.7 Error Conditions Two flags signal SPI error conditions: 1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register before the next byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. 2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 BIT 5 SCK CPHA = 1 SCK CPHA = 0 Freescale Semiconductor, Inc... SCK CYCLE NUMBER 1 2 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST SCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR SCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SCK = INTERNAL CLOCK ÷ 128; 128 POSSIBLE START POINTS LATEST BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST Figure 18-6. Transmission Start Delay (Master) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions 18.7.1 Overflow Error Freescale Semiconductor, Inc... The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (See Figure 18-4 and Figure 18-5.) If an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. Therefore, an overflow error always indicates the loss of data. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 18-9.) It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull the MCU out of wait mode instead. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 18-7 shows how it is possible to miss an overflow. BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8 SPRF OVRF READ SPSCR READ SPDR 2 5 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 3 4 7 5 6 7 8 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS SET. BYTE 4 IS LOST. Figure 18-7. Missed Read of Overflow Condition MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... The first part of Figure 18-7 shows how to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF flag can be set in between the time that SPSCR and SPDR are read. In this case, an overflow can be easily missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR after the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions will complete with an SPRF interrupt. Figure 18-8 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit (SPSCR). BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 5 7 11 SPI RECEIVE COMPLETE SPRF OVRF 2 READ SPSCR 4 6 9 3 READ SPDR 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 5 BYTE 2 SETS SPRF BIT. 12 CPU READS SPSCR. 6 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 18-8. Clearing SPRF When OVRF Interrupt Is Not Enabled Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions 18.7.2 Mode Fault Error Freescale Semiconductor, Inc... For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 18-9.) It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared. • The data direction register of the shared I/O port regains control of port drivers. NOTE: To prevent bus contention with another master SPI after a mode fault error, clear all data direction register (DDR) bits associated with the SPI shared port pins. NOTE: Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading SPMSTR when MODF = 1 will indicate a MODE fault error occurred in either master mode or slave mode. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK returns to its idle level after the shift of the eighth data bit. When CPHA = 1, the MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its IDLE level after the shift of the last data bit. (See 18.6 Transmission Formats). Freescale Semiconductor, Inc... NOTE: When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by toggling the SPE bit of the slave. NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a transmission has begun. To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared. 18.8 Interrupts The four SPI status flags that can be enabled to generate CPU interrupt requests are listed in Table 18-3. Table 18-3. SPI Interrupts Flag Request SPTE (transmitter empty) SPI transmitter CPU interrupt request (SPTIE = 1) SPRF (receiver full) SPI receiver CPU interrupt request (SPRIE = 1) OVRF (overflow) SPI receiver/error interrupt request (ERRIE = 1) MODF (mode fault) SPI receiver/error interrupt request (ERRIE = 1, MODFEN = 1) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Interrupts The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests. The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt, provided that the SPI is enabled (SPE = 1). Freescale Semiconductor, Inc... The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF flag is enabled to generate receiver/error CPU interrupt requests. SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 18-9. SPI Interrupt Request Generation Two sources in the SPI status and control register can generate CPU interrupt requests: 1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF can generate an SPI receiver/error CPU interrupt request. 2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate an SPTE CPU interrupt request. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 18.9 Queuing Transmission Data Freescale Semiconductor, Inc... The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer is ready to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 18-10 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA:CPOL = 1:0). WRITE TO SPDR SPTE 1 3 8 5 2 10 SPSCK (CPHA:CPOL = 1:0) MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 BYTE 1 BYTE 2 BYTE 3 9 4 SPRF 6 READ SPSCR 11 7 READ SPDR 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET. 12 7 CPU READS SPDR, CLEARING SPRF BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. Figure 18-10. SPRF/SPTE CPU Interrupt Timing Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Resetting the SPI For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted. Freescale Semiconductor, Inc... 18.10 Resetting the SPI Any system reset completely resets the SPI. Partial reset occurs whenever the SPI enable bit (SPE) is low. Whenever SPE is low, these occur: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O. These additional items are reset only by a system reset: • All control bits in the SPCR register • All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) • The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to reset all control bits when SPE is set back to high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 18.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. Freescale Semiconductor, Inc... 18.11.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode, the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). (See 18.8 Interrupts.) 18.11.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after the MCU exits stop mode. If stop mode is exited by reset, any transfer in progress is aborted and the SPI is reset. 18.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR, $FE03) enables software to clear status bits during the break state. See 9.8.3 SIM Break Flag Control Register. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Signals Freescale Semiconductor, Inc... To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. 18.13 I/O Signals The SPI module has four I/O pins and shares three of them with a parallel I/O port. • MISO — Data received • MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select • VSS — Clock ground The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 18.13.1 MISO (Master In/Slave Out) Freescale Semiconductor, Inc... MISO is one of the two SPI module pins that transmit serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port. 18.13.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmit serial data. In full duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. 18.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Signals 18.13.4 SS (Slave Select) Freescale Semiconductor, Inc... The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 18.6 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low throughout the transmission for the CPHA = 1 format. See Figure 18-11. MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 18-11. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. (See 18.14.2 SPI Status and Control Register.) NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if a transmission already has begun. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 18.7.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the data register. See Table 18-4. Table 18-4. SPI Configuration Freescale Semiconductor, Inc... SPE SPMSTR MODFEN SPI Configuration State of SS Logic 0 X X Not enabled General-purpose I/O; SS ignored by SPI 1 0 X Slave Input-only to SPI 1 1 0 Master without MODF General-purpose I/O; SS ignored by SPI 1 1 1 Master with MODF Input-only to SPI X = Don’t care 18.13.5 VSS (Clock Ground) VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin of the slave to the VSS pin. 18.14 I/O Registers Three registers control and monitor SPI operation: 1. SPI control register (SPCR, $0010) 2. SPI status and control register (SPSCR, $0011) 3. SPI data register (SPDR, $0012) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers 18.14.1 SPI Control Register Freescale Semiconductor, Inc... The SPI control register: • Enables SPI module interrupt requests • Selects CPU interrupt requests • Configures the SPI module as master or slave • Selects serial clock polarity and phase • Configures the SPSCK, MOSI, and MISO pins as open-drain outputs • Enables the SPI module Address: $0010 Bit 7 6 5 4 3 2 1 Bit 0 SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 0 1 0 1 0 0 0 Read: Write: Reset: R = Reserved Figure 18-12. SPI Control Register (SPCR) SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 18-4 and Figure 18-5.) To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit. CPHA — Clock Phase Bit Freescale Semiconductor, Inc... This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 18-4 and Figure 18-5.) To transmit data between SPI modules, the SPI modules must have identical CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 18-11.) Reset sets the CPHA bit. When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the most significant bit (MSB) of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. (See 18.7.2 Mode Fault Error.) A logic 1 on the SS pin does not in any way affect the state of the SPI state machine. SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers SPE — SPI Enable Bit This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 18.10 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled Freescale Semiconductor, Inc... SPTIE — SPI Transmit Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled 18.14.2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions: • Receive data register full • Failure to clear SPRF bit before next byte is received (overflow error) • Inconsistent logic level on SS pin (mode fault error) • Transmit data register empty The SPI status and control register also contains bits that perform these functions: • Enable error interrupts • Enable mode fault error detection • Select master SPI baud rate MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Address: $0011 Bit 7 Read: 6 SPRF 5 4 3 OVRF MODF SPTE R R R 0 0 1 ERRIE Write: R Reset: 0 R 0 2 1 Bit 0 MODFEN SPR1 SPR0 0 0 0 = Reserved Freescale Semiconductor, Inc... Figure 18-13. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the SPRF bit. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full ERRIE — Error Interrupt Enable Bit This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests. 0 = MODF and OVRF cannot generate CPU interrupt requests. OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the SPI data register. Reset clears the OVRF flag. 1 = Overflow 0 = No overflow Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers MODF — Mode Fault Bit Freescale Semiconductor, Inc... This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading the SPI status and control register with MODF set and then writing to the SPI status and control register. Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE — SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also. NOTE: Do not write to the SPI data register unless the SPTE bit is high. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN — Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a generalpurpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See 18.13.4 SS (Slave Select).) MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See 18.7.2 Mode Fault Error.) SPR1 and SPR0 — SPI Baud Rate Select Bits Freescale Semiconductor, Inc... In master mode, these read/write bits select one of four baud rates as shown in Table 18-5. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 18-5. SPI Master Baud Rate Selection SPR1:SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = -------------------------2 × BD where: CGMOUT = base clock output of the clock generator module (CGM); see Section 10. Clock Generator Module (CGM) BD = baud rate divisor 18.14.3 SPI Data Register The SPI data register is the read/write buffer for the receive data register and the transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate buffers that can contain different values. See Figure 18-2. Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers Address: $0012 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Indeterminate after reset Figure 18-14. SPI Data Register (SPDR) Freescale Semiconductor, Inc... R7–R0/T7–T0 — Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the buffer read is not the same as the buffer written. MC68HC908AS60 — Rev. 1.0 Technical Data Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Peripheral Interface (SPI) Technical Data MC68HC908AS60 — Rev. 1.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 19. Modulo Timer (TIM) Freescale Semiconductor, Inc... 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.5 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 19.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 295 19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 19.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 296 19.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 19.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 299 19.2 Introduction This section describes the modulo timer (TIM) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. Figure 19-1 is a block diagram of the TIM. MC68HC908AS60 — Rev. 1.0 Technical Data Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) 19.3 Features Freescale Semiconductor, Inc... Features of the TIM include: • Programmable TIM clock input • Free-running or modulo up-count operation • TIM counter stop and reset bits 19.4 Functional Description Figure 19-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The TIM counter modulo registers, TMODH–TMODL, control the modulo value of the counter. Software can read the counter value at any time without affecting the counting sequence. PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER CSTOP PS2 CRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TIMTMODH:TIMTMODL Figure 19-1. TIM Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) Functional Description Addr. $004B Freescale Semiconductor, Inc... $004C $004D $004E $004F Register Name Bit 7 Read: TIM Status and Control Register (TSC) Write: See page 296. Reset: TOF 0 0 1 0 Read: TIM Counter Register High (TCNTH) Write: See page 298. Reset: Bit 15 14 13 0 0 Read: TIM Counter Register Low (TCNTL) Write: See page 298. Reset: Bit 7 Read: TIM Modulo Register High (TMODH) Write: See page 299. Reset: Read: TIM Modulo Register Low (TMODL) Write: See page 299. Reset: 6 5 TOIE TSTOP 2 1 Bit 0 PS2 PS1 PS0 0 0 0 0 12 11 10 9 Bit 8 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 0 4 3 0 0 TRST = Unimplemented R = Reserved Figure 19-2. TIM I/O Register Summary MC68HC908AS60 — Rev. 1.0 Technical Data Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) 19.5 TIM Counter Prescaler Freescale Semiconductor, Inc... The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS2–PS0, in the status and control register select the TIM clock source. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. The TIM overflow flag (TOF) is set when the TIM counter value rolls over to $0000 after matching the value in the TIM counter modulo registers. The TIM interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. 19.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 19.6.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 19.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. Technical Data MC68HC908AS60 — Rev. 1.0 Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) TIM During Break Interrupts 19.7 TIM During Break Interrupts A break interrupt stops the TIM counter. Freescale Semiconductor, Inc... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 9.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 19.8 I/O Registers These I/O registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM counter registers (TCNTH–TCNTL) • TIM counter modulo registers (TMODH–TMODL) MC68HC908AS60 — Rev. 1.0 Technical Data Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) 19.8.1 TIM Status and Control Register Freescale Semiconductor, Inc... The TIM status and control register: • Enables TIM interrupt • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: $004B Bit 7 Read: 6 5 TOIE TSTOP TOF Write: 0 Reset: 0 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 TRST 0 1 0 0 = Unimplemented Figure 19-3. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter resets to $0000 after reaching the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value. 0 = TIM counter has not reached modulo value. TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Technical Data MC68HC908AS60 — Rev. 1.0 Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) I/O Registers TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active Freescale Semiconductor, Inc... NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS2–PS0 — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 19-1 shows. Reset clears the PS2–PS0 bits. Table 19-1. Prescaler Selection PS2–PS0 TIM Clock Source 000 Internal bus clock ÷1 001 Internal bus clock ÷ 2 010 Internal bus clock ÷ 4 011 Internal bus clock ÷ 8 100 Internal bus clock ÷ 16 101 Internal bus clock ÷ 32 110 Internal bus clock ÷ 64 111 Internal bus clock ÷ 64 MC68HC908AS60 — Rev. 1.0 Technical Data Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) 19.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Freescale Semiconductor, Inc... NOTE: If TCNTH is read during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Address: $004C Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: Address: $004D Read: Write: Reset: = Unimplemented Figure 19-4. TIM Counter Registers (TCNTH–TCNTL) Technical Data MC68HC908AS60 — Rev. 1.0 Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modulo Timer (TIM) I/O Registers 19.8.3 TIM Counter Modulo Registers Freescale Semiconductor, Inc... The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Address: $004E Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Address: $004F Read: Write: Reset: Figure 19-5. TIM Counter Modulo Registers (TMODH–TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908AS60 — Rev. 1.0 Technical Data Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Modulo Timer (TIM) Technical Data MC68HC908AS60 — Rev. 1.0 Modulo Timer (TIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 20. Input/Output (I/O) Ports 20.1 Contents Freescale Semiconductor, Inc... 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 20.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 20.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 307 20.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 20.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 20.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 309 20.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 312 20.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.8.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 20.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 20.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . 321 20.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 20.10.1 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 20.10.2 Data Direction Register H. . . . . . . . . . . . . . . . . . . . . . . . . . 324 MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.2 Introduction Forty bidirectional input/output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs or outputs. Freescale Semiconductor, Inc... NOTE: Addr. Register Name Read: Port A Data Register (PTA) Write: See page 304. Reset: $0000 Read: Port B Data Register (PTB) Write: See page 306. Reset: $0001 Read: Port C Data Register (PTC) Write: See page 308. Reset: $0002 Read: Port D Data Register (PTD) Write: See page 311. Reset: $0003 $0004 $0005 $0006 Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTC2 PTC1 PTC0 PTD2 PTD1 PTD0 DDRA2 DDRA1 DDRA0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 Unaffected by reset 0 0 R R PTC5 PTC4 PTC3 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset Read: Data Direction Register A DDRA7 (DDRA) Write: See page 304. Reset: Read: Data Direction Register B DDRB7 (DDRB) Write: See page 307. Reset: 0 Read: Data Direction Register C MCLKEN (DDRC) Write: See page 309. Reset: 0 R DDRA6 DDRA5 DDRA4 DDRA3 Unaffected by reset DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 R 0 = Reserved Figure 20-1. I/O Port Register Summary Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Introduction Addr. $0007 Freescale Semiconductor, Inc... $0008 $0009 $000A $000B $000C $000D $000E $000F Register Name Bit 7 Read: Data Direction Register D DDRD7 (DDRD) Write: See page 312. Reset: 0 Read: Port E Data Register (PTE) Write: See page 314. Reset: Port F Data Register Read: (PTF) Write: See page 318. Reset: Read: Port G Data Register (1) (PTG) Write: See page 320. Reset: Read: Port H Data Register (PTH)(1) Write: See page 323. Reset: PTE7 Read: Data Direction Register G (1) (DDRG) Write: See page 321. Reset: Read: Data Direction Register H (DDRH)(1) Write: See page 324. Reset: 5 4 3 2 1 Bit 0 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 0 0 0 0 0 0 0 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 PTF2 PTF1 PTF0 PTG2 PTG1 PTG0 PTH1 PTH0 Unaffected by reset 0 PTF6 PTF5 PTF4 PTF3 R Unaffected by reset 0 0 0 0 0 R R R R R Unaffected by reset 0 0 0 0 0 0 R R R R R R Unaffected by reset Read: Data Direction Register E DDRE7 (DDRE) Write: See page 316. Reset: 0 Read: Data Direction Register F (DDRF) Write: See page 319. Reset: 6 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRG2 DDRG1 DDRG0 R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRH1 DDRH0 R R R R R R 0 0 0 0 0 0 0 0 0 R 1. The pins associated with port G and port H are available only in the 64-pin quad flat pack (QFP). R = Reserved Figure 20-1. I/O Port Register Summary (Continued) MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.3 Port A Port A is an 8-bit, general-purpose, bidirectional I/O port. 20.3.1 Port A Data Register Freescale Semiconductor, Inc... The port A data register (PTA) contains a data latch for each of the eight port A pins. Address: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Read: Write: Reset: Unaffected by reset Figure 20-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. 20.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Read: Write: Reset: Unaffected by reset Figure 20-3. Data Direction Register A (DDRA) Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port A DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. READ DDRA ($0004) WRITE DDRA ($0004) INTERNAL DATA BUS Freescale Semiconductor, Inc... Figure 20-4 shows the port A I/O logic. DDRAx RESET WRITE PTA ($0000) PTAx PTAx READ PTA ($0000) Figure 20-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-1 summarizes the operation of the port A pins. Table 20-1. Port A Pin Functions DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 0 X Input, Hi-Z DDRA[7:0] Pin PTA[7:0](1) 1 X Output DDRA[7:0] PTA[7:0] PTA[7:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.4 Port B Port B is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (ADC). 20.4.1 Port B Data Register Freescale Semiconductor, Inc... The port B data register (PTB) contains a data latch for each of the eight port B pins. Address: $0001 Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 ATD2 ATD1 ATD0 Read: Write: Reset: Alternate Functions: Unaffected by reset ATD7 ATD6 ATD5 ATD4 ATD3 Figure 20-5. Port B Data Register (PTB) PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. ATD[7:0] — ADC Channels PTB7/ATD7–PTB0/ATD0 are eight of the 15 analog-to-digital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. Data direction register B (DDRB) does not affect the data direction of port B pins that are being used by the ADC. However, the DDRB bits always determine whether reading port B returns to the states of the latches or logic 0. See Section 23. Analog-to-Digital Converter (ADC-15). Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port B 20.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 20-6. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 20-7 shows the port B I/O logic. READ DDRB ($0005) WRITE DDRB ($0005) INTERNAL DATA BUS Freescale Semiconductor, Inc... Address: DDRBx RESET WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) Figure 20-7. Port B I/O Circuit MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-2 summarizes the operation of the port B pins. Freescale Semiconductor, Inc... Table 20-2. Port B Pin Functions DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB Read/Write Read Write 0 X Input, Hi-Z DDRB[7:0] Pin PTB[7:0](1) 1 X Output DDRB[7:0] PTB[7:0] PTB[7:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. 20.5 Port C Port C is a 6-bit, general-purpose, bidirectional I/O port. 20.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the five port C pins. NOTE: The pin associated with PTC5 is availble only in the 64-pin quad flat pack (QFP). Address: $0002 Bit 7 6 Read: 0 0 Write: R R 5 4 3 2 1 Bit 0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 MCLK R R Reset: Alternate Functions: Unaffected by reset R R R R R R = Reserved Figure 20-8. Port C Data Register (PTC) Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port C PTC[5:0] — Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. MCLK — T12 System Clock Bit Freescale Semiconductor, Inc... The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7. 20.5.2 Data Direction Register C Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: $0006 Bit 7 Read: 6 4 3 2 1 Bit 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 MCLKEN Write: Reset: 5 R 0 R 0 = Reserved Figure 20-9. Data Direction Register C (DDRC) MCLKEN — MCLK Enable Bit This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, PTC2 is under the control of MCLKEN. Reset clears this bit. 1 = MCLK output enabled 0 = MCLK output disabled DDRC[5:0] — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports NOTE: Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 20-10 shows the port C I/O logic. READ DDRC ($0006) Freescale Semiconductor, Inc... INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx READ PTC ($0002) Figure 20-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-3 summarizes the operation of the port C pins. Table 20-3. Port C Pin Functions DDRC Bit PTC Bit I/O Pin Mode Accesses to DDRC Accesses to PTC Read/Write Read Write 0 2 Input, Hi-Z DDRC[5:0] Pin PTC2 1 2 Output DDRC[5:0] 0 — 0 X Input, Hi-Z DDRC[5:0] Pin PTC[5:0](1) 1 X Output DDRC[5:0] PTC[5:0] PTC[5:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port D 20.6 Port D Port D is an 8-bit general-purpose I/O port. NOTE: The pin associated with PTD7 is available only in the 64-pin QFP. Freescale Semiconductor, Inc... 20.6.1 Port D Data Register Port D is an 8-bit special function port that shares all of its pins with the analog-to-digital converter and one of its pins with the timer interface module A (TIMA). Address: $0003 Bit 7 6 5 4 3 2 1 Bit 0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 ATD10 ATD9 ATD8 Read: Write: Reset: Alternate Functions: Unaffected by reset R ATD14/ TACLK R = Reserved ATD13 ATD12 ATD11 Figure 20-11. Port D Data Register (PTD) PTD[7:0] — Port D Data Bits PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the control of the corresponding bit in data direction register D. ATD[14:8] — ADC Channel Status Bits PTD6/TACLK–PTD0 are seven of the 15 analog-to-digital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTD6/TACLK–PTD0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. See Section 23. Analog-to-Digital Converter (ADC-15). MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports NOTE: Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the ADC. However, the DDRD bits always determine whether reading port D returns the states of the latches or logic 0. Freescale Semiconductor, Inc... TACLK — Timer Clock Input Bit The PTD6/TACLK pin is the external clock input for the TIMA. The prescaler select bits, PS[2:0], select PTD6/TACLK as the TIMA clock input. (See 22.9.1 TIMA Status and Control Register.) When not selected as the TIMA clock, PTD6/TACLK is available for general-purpose I/O or as an ADC channel. NOTE: Do not use ADC channel ATD14 when using the PTD6/TACLK pin as the clock input for the TIMA. 20.6.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 20-12. Data Direction Register D (DDRD) DDRD[7:0] — Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port D Figure 20-13 shows the port D I/O logic. READ DDRD ($0007) INTERNAL DATA BUS Freescale Semiconductor, Inc... WRITE DDRD ($0007) RESET DDRDx WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) Figure 20-13. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-4 summarizes the operation of the port D pins. Table 20-4. Port D Pin Functions DDRD Bit PTD Bit I/O Pin Mode Accesses to DDRD Accesses to PTD Read/Write Read Write 0 X Input, Hi-Z DDRD[7:0] Pin PTD[7:0](1) 1 X Output DDRD[7:0] PTD[7:0] PTD[7:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.7 Port E Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI), and four of its pins with the serial peripheral interface module (SPI). 20.7.1 Port E Data Register Freescale Semiconductor, Inc... The port E data register (PTE) contains a data latch for each of the eight port E pins. Address: $0008 Bit 7 6 5 4 3 2 1 Bit 0 PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 TACH0 RxD TxD Read: Write: Reset: Alternate Function: Unaffected by reset SPSCK MOSI MISO SS TACH1 Figure 20-14. Port E Data Register (PTE) PTE[7:0] — Port E Data Bits PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. SPSCK — SPI Serial Clock Bit The PTE7/SPSCK pin is the serial clock input of an SPI slave module and serial clock output of an SPI master module. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O. MOSI — Master Out/Slave In Bit The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTE6/MOSI pin is available for general-purpose I/O. (See 18.14.1 SPI Control Register.) Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port E MISO — Master In/Slave Out Bit The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. (See 18.14.1 SPI Control Register.) Freescale Semiconductor, Inc... SS — Slave Select Bit The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for general-purpose I/O. (See 18.13.4 SS (Slave Select).) When the SPI is enabled as a slave, the DDRF4 bit in data direction register E (DDRE) has no effect on the PTE4/SS pin. NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 20-5.) TACH[1:0] — Timer Channel I/O Bits The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input capture/output compare pins. The edge/level select bits, ELSxB–ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel I/O pins or general-purpose I/O pins. (See 22.9.4 TIMA Channel Status and Control Registers.) NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIMA. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 20-5.) RxD — SCI Receive Data Input Bit The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See 17.9.1 SCI Control Register 1.) MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. (See 17.9.1 SCI Control Register 1.) Freescale Semiconductor, Inc... NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 20-5.) 20.7.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: $000C Bit 7 6 5 4 3 2 1 Bit 0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 20-15. Data Direction Register E (DDRE) DDRE[7:0] — Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE: Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 20-16 shows the port E I/O logic. Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port E READ DDRE ($000C) INTERNAL DATA BUS WRITE DDRE ($000C) DDREx RESET WRITE PTE ($0008) PTEx PTEx Freescale Semiconductor, Inc... READ PTE ($0008) Figure 20-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-5 summarizes the operation of the port E pins. Table 20-5. Port E Pin Functions DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Accesses to PTE Read/Write Read Write 0 X Input, Hi-Z DDRE[7:0] Pin PTE[7:0](1) 1 X Output DDRE[7:0] PTE[7:0] PTE[7:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.8 Port F Port F is a 7-bit special function port that shares four of its pins with the timer interface module (TIMA). NOTE: The pins associated with PTF6, PTF5, and PTF4 are available only in the 64-pin QFP. Freescale Semiconductor, Inc... 20.8.1 Port F Data Register The port F data register (PTF) contains a data latch for each of the six port F pins. Address: $0009 Bit 7 Read: 0 Write: R 6 5 4 3 2 1 Bit 0 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 TACH4 TACH3 TACH2 Reset: Unaffected by reset Alternate Function: TACH5 R = Reserved Figure 20-17. Port F Data Register (PTF) PTF[6:0] — Port F Data Bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0]. TACH[5:2] — Timer Channel I/O Bits The PTF3–PTF0/TACH2 pins are the TIMA input capture/output compare pins. The edge/level select bits, ELSxB–ELSxA, determine whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or general-purpose I/O pins. See 22.9.4 TIMA Channel Status and Control Registers. NOTE: Data direction register F (DDRF) does not affect the data direction of port F pins that are being used by the TIMA. However, the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins. (See Table 20-6.) Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port F 20.8.2 Data Direction Register F Data direction register F (DDRF)determines whether each port F pin is an input or an output. Writing a logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer. Address: $000D Read: 0 Write: R Reset: 0 R 6 5 4 3 2 1 Bit 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 = Reserved Figure 20-18. Data Direction Register F (DDRF) DDRF[6:0] — Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input NOTE: Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 20-19 shows the port F I/O logic. READ DDRF ($000D) WRITE DDRF ($000D) INTERNAL DATA BUS Freescale Semiconductor, Inc... Bit 7 RESET DDRFx WRITE PTF ($0009) PTFx PTFx READ PTF ($0009) Figure 20-19. Port F I/O Circuit MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-6 summarizes the operation of the port F pins. Table 20-6. Port F Pin Functions Freescale Semiconductor, Inc... DDRF Bit PTF Bit Accesses to DDRF I/O Pin Mode Accesses to PTF Read/Write Read Write 0 X Input, Hi-Z DDRF[6:0] Pin PTF[6:0](1) 1 X Output DDRF[6:0] PTF[6:0] PTF[6:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. 20.9 Port G Port G is a 3-bit, general-purpose, bidirectional I/O port. NOTE: The pins of port G are available only in the 64-pin QFP. 20.9.1 Port G Data Register The port G data register (PTG) contains a data latch for each of the three port G pins. Address: $000A Bit 7 6 5 4 3 Read: 0 0 0 0 0 Write: R R R R R Reset: 2 1 Bit 0 PTG2 PTG1 PTG0 Unaffected by reset R = Reserved Figure 20-20. Port G Data Register (PTG) Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port G PTG[2:0] — Port G Data Bits These read/write bits are software programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0]. Freescale Semiconductor, Inc... 20.9.2 Data Direction Register G Data direction register G (DDRG) determines whether each port G pin is an input or an output. Writing a logic 1 to a DDRG bit enables the output buffer for the corresponding port G pin; a logic 0 disables the output buffer. Address: $000E Bit 7 6 5 4 3 Read: 0 0 0 0 0 Write: R R R R R Reset: 0 0 0 0 0 R 2 1 Bit 0 DDRG2 DDRG1 DDRG0 0 0 0 = Reserved Figure 20-21. Data Direction Register G (DDRG) DDRG[2:0] — Data Direction Register G Bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input NOTE: Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1. Figure 20-22 shows the port G I/O logic. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports READ DDRG ($000E) INTERNAL DATA BUS WRITE DDRG ($000E) DDRGx RESET WRITE PTG ($000A) PTGx PTGx Freescale Semiconductor, Inc... READ PTG ($000A) Figure 20-22. Port G I/O Circuit When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-7 summarizes the operation of the port G pins. Table 20-7. Port G Pin Functions DDRG Bit PTG Bit I/O Pin Mode Accesses to DDRG Accesses to PTG Read/Write Read Write 0 X Input, Hi-Z DDRG[2:0] Pin PTG[2:0](1) 1 X Output DDRG[2:0] PTG[2:0] PTG[2:0] X = Don’t care Hi-Z = High impedance 1. Writing affects data register, but does not affect input. Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port H 20.10 Port H Port H is a 2-bit, general-purpose, bidirectional I/O port. NOTE: The pins of port H are available only in the 64-pin QFP. 20.10.1 Port H Data Register Freescale Semiconductor, Inc... The port H data register (PTH) contains a data latch for each of the two port H pins. Address: $000B Bit 7 6 5 4 3 2 Read: 0 0 0 0 0 0 Write: R R R R R R Reset: 1 Bit 0 PTH1 PTH0 Unaffected by reset R = Reserved Figure 20-23. Port H Data Register (PTH) PTH[1:0] — Port H Data Bits These read/write bits are software programmable. Data direction of each port H pin is under the control of the corresponding bit in data direction register H. Reset has no effect on PTH[1:0]. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports 20.10.2 Data Direction Register H Data direction register H (DDRH) determines whether each port H pin is an input or an output. Writing a logic 1 to a DDRH bit enables the output buffer for the corresponding port H pin; a logic 0 disables the output buffer. Freescale Semiconductor, Inc... Address: $000F Bit 7 6 5 4 3 2 Read: 0 0 0 0 0 0 Write: R R R R R R Reset: 0 0 0 0 0 0 R 1 Bit 0 DDRH1 DDRH0 0 0 = Reserved Figure 20-24. Data Direction Register H (DDRH) DDRH[1:0] — Data Direction Register H Bits These read/write bits control port H data direction. Reset clears DDRG[1:0], configuring all port H pins as inputs. 1 = Corresponding port H pin configured as output 0 = Corresponding port H pin configured as input NOTE: Avoid glitches on port H pins by writing to the port H data register before changing data direction register H bits from 0 to 1. Figure 20-25 shows the port H I/O logic. READ DDRH ($000F) INTERNAL DATA BUS WRITE DDRH ($000F) RESET DDRHx WRITE PTH ($000B) PTHx PTHx READ PTH ($000B) Figure 20-25. Port H I/O Circuit Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Input/Output (I/O) Ports Port H When bit DDRHx is a logic 1, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic 0, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-8 summarizes the operation of the port H pins. Table 20-8. Port H Pin Functions Freescale Semiconductor, Inc... DDRH Bit PTH Bit I/O Pin Mode Accesses to DDRH Accesses to PTH Read/Write Read Write 0 X Input, Hi-Z DDRH[1:0] Pin PTH[1:0](1) 1 X Output DDRH[1:0] PTH[1:0] PTH[1:0] X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. MC68HC908AS60 — Rev. 1.0 Technical Data Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Input/Output (I/O) Ports Technical Data MC68HC908AS60 — Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 21. Byte Data Link Controller-Digital (BDLC-D) Freescale Semiconductor, Inc... 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 21.4.1 BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 21.4.1.1 Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 21.4.1.2 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 21.4.1.3 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 21.4.1.6 Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 334 21.4.1.7 Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 334 21.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 21.5.1 Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 21.5.1.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 21.5.1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 21.5.2 J1850 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 21.5.2.1 Start-of-Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . . 337 21.5.2.2 In-Message Data Bytes (Data). . . . . . . . . . . . . . . . . . . . 338 21.5.2.3 Cyclical Redundancy Check Byte (CRC) . . . . . . . . . . . . 338 21.5.2.4 End-of-Data Symbol (EOD) . . . . . . . . . . . . . . . . . . . . . . 339 21.5.2.5 In-Frame Response Bytes (IFR) . . . . . . . . . . . . . . . . . .339 21.5.2.6 End-of-Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . . 340 21.5.2.7 Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . . 340 21.5.2.8 Break (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.2.9 Idle Bus (IDLE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.3 J1850 VPW Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 21.5.3.1 Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 21.5.3.2 Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 21.5.3.3 Normalization Bit (NB) . . . . . . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.4 Break Signal (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . 344 MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Freescale Semiconductor, Inc... 21.5.3.5 Start-of-Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . . 344 21.5.3.6 End-of-Data Symbol (EOD) . . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.7 End-of-Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . . 344 21.5.3.8 Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . . 344 21.5.3.9 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 21.5.4 J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . . . 345 21.5.4.1 Invalid Passive Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.5.4.2 Valid Passive Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.5.4.3 Valid Passive Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.4 Valid EOD Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.5 Valid EOF and IFS Symbols . . . . . . . . . . . . . . . . . . . . . 346 21.5.4.6 Idle Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 21.5.4.7 Invalid Active Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.8 Valid Active Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.9 Valid Active Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.4.10 Valid SOF Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.5.4.11 Valid BREAK Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.5.5 Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.6.1 Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 21.6.2 Rx and Tx Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 352 21.6.3 Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . . .353 21.6.4 Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .353 21.6.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.6.5.1 4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 21.6.5.2 Receiving a Message in Block Mode . . . . . . . . . . . . . . . 354 21.6.5.3 Transmitting a Message in Block Mode . . . . . . . . . . . . . 354 21.6.5.4 J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.6.5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 21.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 21.7.1 BDLC Analog and Roundtrip Delay . . . . . . . . . . . . . . . . . .358 21.7.2 BDLC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.7.3 BDLC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.7.4 BDLC State Vector Register. . . . . . . . . . . . . . . . . . . . . . . . 370 21.7.5 BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Introduction 21.2 Introduction The byte data link controller (BDLC) provides access to an external serial communication multiplex bus, operating according to the SAE J1850 protocol. 21.3 Features Freescale Semiconductor, Inc... Features of the BDLC module include: • SAE J1850 Class B Data Communications Network Interface compatible and ISO compatible for low-speed (<125 kbps) serial data communications in automotive applications • 10.4 kbps variable pulse width (VPW) bit format • Digital noise filter • Collision detection • Hardware cyclical redundancy check (CRC) generation and checking • Two power-saving modes with automatic wakeup on network activity • Polling or CPU interrupts • Block mode receive and transmit supported • 4X receive mode, 41.6 kbps, supported • Digital loopback mode • Analog loopback mode • In-frame response (IFR) types 0, 1, 2, and 3 supported MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.4 Functional Description Freescale Semiconductor, Inc... Figure 21-1 shows the organization of the BDLC module. The CPU interface contains the software addressable registers and provides the link between the CPU and the buffers. The buffers provide storage for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for the encoding and decoding of data bits and special message symbols during transmission and reception. The multiplex (MUX) interface provides the link between the BDLC digital section and the analog physical interface. The wave shaping, driving, and digitizing of data is performed by the physical interface. Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data Communication Network Interface specification. NOTE: It is recommended that the reader be familiar with the SAE J1850 document and ISO Serial Communication document prior to proceeding with this section of the MC68HC908AS60 specification. TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 21-1. BDLC Block Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Functional Description Addr. $003B Freescale Semiconductor, Inc... $003C $003D $003E $003F Register Name Read: BDLC Analog and Roundtrip Delay Register (BARD) Write: See page 358. Reset: Read: BDLC Control Register 1 (BCR1) Write: See page 359. Reset: Bit 7 6 ATE RXPOL 1 1 0 0 IMSG CLKS R1 R0 1 Read: BDLC Data Register (BDR) Write: See page 372. Reset: 4 0 0 3 2 1 Bit 0 BO3 BO2 BO1 BO0 0 1 1 1 0 0 IE WCM R R 1 1 0 0 0 0 0 DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 1 0 0 0 0 0 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 Read: BDLC Control Register 2 ALOOP (BCR2) Write: See page 362. Reset: 1 Read: BDLC State Vector Register (BSVR) Write: See page 370. Reset: 5 Indeterminate after reset = Unimplemented R = Reserved Figure 21-2. BDLC I/O Register Summary 21.4.1 BDLC Operating Modes The BDLC has five main modes of operation which interact with the power supplies, pins, and rest of the MCU as shown in Figure 21-3. 21.4.1.1 Power Off Mode For the BDLC to guarantee operation, this mode is entered from reset mode whenever the BDLC supply voltage, VDD, drops below its minimum specified value. The BDLC will be placed in reset mode by low-voltage reset (LVR) before being powered down. In power off mode, the pin input and output specifications are not guaranteed. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) POWER OFF VDD > VDD (MINIMUM) AND ANY MCU RESET SOURCE ASSERTED V DD ≤ VDD (MINIMUM) Freescale Semiconductor, Inc... RESET ANY MCU RESET SOURCE ASSERTED FROM ANY MODE (COP, ILLADDR, PU, RESET, LVR, POR) NETWORK ACTIVITY OR OTHER MCU WAKEUP RUN NO MCU RESET SOURCE ASSERTED NETWORK ACTIVITY OR OTHER MCU WAKEUP BDLC WAIT BDLC STOP STOP INSTRUCTION OR WAIT INSTRUCTION AND WCM = 1 WAIT INSTRUCTION AND WCM = 0 Figure 21-3. BDLC Operating Modes State Diagram 21.4.1.2 Reset Mode This mode is entered from power off mode whenever the BDLC supply voltage, VDD, rises above its minimum specified value (VDD –10%) and some MCU reset source is asserted. The internal MCU reset must be asserted while powering up the BDLC or an unknown state will be entered and correct operation cannot be guaranteed. Reset mode is also entered from any other mode as soon as one of the MCU’s possible reset sources (such as LVR, POR, COP watchdog, reset pin, etc.) is asserted. In reset mode, the internal BDLC voltage references are operative, V DD is supplied to the internal circuits which are held in their reset state, and the internal BDLC system clock is running. Registers will assume their reset condition. Because outputs are held in their programmed reset state, inputs and network activity are ignored. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Functional Description 21.4.1.3 Run Mode This mode is entered from reset mode after all MCU reset sources are no longer asserted. Run mode is entered from the BDLC wait mode whenever activity is sensed on the J1850 bus. Freescale Semiconductor, Inc... Run mode is entered from the BDLC stop mode whenever network activity is sensed, although messages will not be received properly until the clocks have stabilized and the CPU is also in run mode. In this mode, normal network operation takes place. The user should ensure that all BDLC transmissions have ceased before exiting this mode. 21.4.1.4 Wait Mode This power-conserving mode is entered automatically from run mode whenever the CPU executes a WAIT instruction and if the WCM bit in the BCR1 register is cleared previously. In this mode, the BDLC internal clocks continue to run. The first passive-to-active transition of the bus generates a CPU interrupt request from the BDLC, which wakes up the BDLC and the CPU. In addition, if the BDLC receives a valid end-of-frame (EOF) symbol while operating in wait mode, then the BDLC also will generate a CPU interrupt request, which wakes up the BDLC and the CPU. See 21.8.1 Wait Mode. 21.4.1.5 Stop Mode This power-conserving mode is entered automatically from run mode whenever the CPU executes a STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR1 is set previously. In this mode, the BDLC internal clocks are stopped but the physical interface circuitry is placed in a low-power mode and awaits network activity. If network activity is sensed, then a CPU interrupt request will be generated, restarting the BDLC internal clocks. See 21.8.2 Stop Mode. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.4.1.6 Digital Loopback Mode Freescale Semiconductor, Inc... When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition is caused by failure in the node’s internal circuits or elsewhere in the network, including the node’s analog physical interface. In this mode, the transmit digital output pin (BDTxD) and the receive digital input pin (BDRxD) of the digital interface are disconnected from the analog physical interface and tied together to allow the digital portion of the BDLC to transmit and receive its own messages without driving the J1850 bus. 21.4.1.7 Analog Loopback Mode Analog loopback mode is used to determine if a bus fault has been caused by a failure in the node’s off-chip analog transceiver or elsewhere in the network. The BDLC analog loopback mode does not modify the digital transmit or receive functions of the BDLC. It does, however, ensure that once analog loopback mode is exited, the BDLC will wait for an idle bus condition before participation in network communication resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the J1850 bus. In this mode, the output to the J1850 bus typically is high impedance. This allows the communication path through the analog transceiver to be tested without interfering with network activity. Using the BDLC analog loopback mode in conjunction with the analog transceiver’s loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, the BCLD will not begin communicating before a known condition exists on the J1850 bus. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface 21.5 BDLC MUX Interface The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. TO CPU Freescale Semiconductor, Inc... CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 21-4. BDLC Block Diagram 21.5.1 Rx Digital Filter The receiver section of the BDLC includes a digital low-pass filter to remove narrow noise pulses from the incoming message. An outline of the digital filter is shown in Figure 21-5. Rx DATA FROM PHYSICAL INTERFACE (BDRxD) INPUT SYNC 4-BIT UP/DOWN COUNTER DATA LATCH FILTERED Rx DATA OUT D Q UP/DOWN OUT D Q MUX INTERFACE CLOCK Figure 21-5. BDLC Rx Digital Filter Block Diagram MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.5.1.1 Operation Freescale Semiconductor, Inc... The clock for the digital filter is provided by the MUX interface clock (see fBDLC parameter in Table 21-3). At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD) signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or decrement at the next negative edge of the clock signal. The counter will increment if the input data sample is high but decrement if the input sample is low. Therefore, the counter will thus progress either up toward 15 if, on average, the BDRxD signal remains high or progress down toward 0 if, on average, the BDRxD signal remains low. When the counter eventually reaches the value 15, the digital filter decides that the condition of the BDRxD signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to become a logic level 1. Furthermore, the counter is prevented from overflowing and can be decremented only from this state. Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition of the BDRxD signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only be incremented from this state. The data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the signal. 21.5.1.2 Performance The performance of the digital filter is best described in the time domain rather than the frequency domain. If the signal on the BDRxD signal transitions, then there will be a delay before that transition appears at the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. This filter delay must be taken into account when performing message arbitration. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface For example, if the frequency of the MUX interface clock (fBDLC) is 1.0486 MHz, then the period (tBDLC) is 954 ns and the maximum filter delay in the absence of noise will be 15.259 µs. Freescale Semiconductor, Inc... The effect of random noise on the BDRxD signal depends on the characteristics of the noise itself. Narrow noise pulses on the BDRxD signal will be ignored completely if they are shorter than the filter delay. This provides a degree of low pass filtering. If noise occurs during a symbol transition, the detection of that transition can be delayed by an amount equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is truly occurring within the noise. Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, will be detected by the next stage of the BDLC’s receiver as an invalid symbol. Noise pulses that are longer than the shortest allowable symbol length will be detected normally as an invalid symbol or as invalid data when the frame’s CRC is checked. 21.5.2 J1850 Frame Format All messages transmitted on the J1850 bus are structured using the format shown in Figure 21-6. J1850 states that each message has a maximum length of 101 PWM bit times or 12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each byte transmitted most significant bit (MSB) first. All VPW symbol lengths described here are typical values at a 10.4-kbps bit rate. 21.5.2.1 Start-of-Frame Symbol (SOF) All messages transmitted onto the J1850 bus must begin with a long-active 200-µs period SOF symbol. This indicates the start of a new message transmission. The SOF symbol is not used in the CRC calculation. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.5.2.2 In-Message Data Bytes (Data) Freescale Semiconductor, Inc... The data bytes contained in the message include the message priority/type, message ID byte (typically the physical address of the responder), and any actual data being transmitted to the receiving node. The message format used by the BDLC is similar to the 3-byte consolidated header message format outlined by the SAE J1850 document. See SAE J1850 Class B Data Communications Network Interface for more information about 1- and 3-byte headers. Messages transmitted by the BDLC onto the J1850 bus must contain at least one data byte, and, therefore, can be as short as one data byte and one CRC byte. Each data byte in the message is eight bits in length and is transmitted MSB to LSB (least significant bit). DATA IDLE SOF PRIORITY (DATA0) MESSAGE ID (DATA1) DATAN CRC E O D OPTIONAL N B IFR EOF I F S IDLE Figure 21-6. J1850 Bus Message Format (VPW) 21.5.2.3 Cyclical Redundancy Check Byte (CRC) This byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message. The BDLC calculates the CRC byte and appends it onto any messages transmitted onto the J1850 bus. It also performs CRC detection on any messages it receives from the J1850 bus. CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1. The remainder polynomial initially is set to all 1s. Each byte in the message after the start-of-frame (SOF) symbol is processed serially through the CRC generation circuitry. The one’s complement of the remainder then becomes the 8-bit CRC byte, which is appended to the message after the data bytes, in MSB-to-LSB order. When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the SOF and end of data symbols (EOD) but including the CRC byte, are used to check the CRC. If the message is error free, the remainder polynomial will equal Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface X7 + X6 + X2 = $C4, regardless of the data contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as a CRC error and set the CRC error flag in the BSVR. Freescale Semiconductor, Inc... 21.5.2.4 End-of-Data Symbol (EOD) The EOD symbol is a long 200-µs passive period on the J1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. No flag is set upon reception of the EOD symbol. 21.5.2.5 In-Frame Response Bytes (IFR) The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame response should review the SAE J1850 Class B Data Communications Network Interface specification. WARNING: NOTE: When the BDLC is programmed to transmit a single byte Type 2 IFR (byte loaded in the BDR and TSIFR bit set in BCR2), the BDLC will attempt to transmit a single IFR byte following the EOD of the message currently being received. If the byte to be transmitted loses arbitration, the BDLC will continue to retry transmission until it is successful or an error occurs or the TEOD bit is set. When the BDLC does win arbitration and transmits its single byte IFR, it does not receive additional IFR bytes transmitted from other nodes properly, instead generates an invalid symbol interrupt. The user can compensate for the condition described in the preivous paragraph by following this procedure: • When the first RXIFR interrupt occurs, the requester message has been received without errors (invalid symbol or CRC). • When the BDLC receives back correctly the IFR byte it was trying to transmit, then response by this node is complete. The requester message received can be passed to the application layer. • Ignore any invalid symbol error that occurs after the first RXIFR interrupt, since transmission of IFRs are not retried. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.5.2.6 End-of-Frame Symbol (EOF) Freescale Semiconductor, Inc... This symbol is a long 280-µs passive period on the J1850 bus and is longer than an end-of-data (EOD) symbol, which signifies the end of a message. Since an EOF symbol is longer than a 200-µs EOD symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is assumed to be completed. The EOF flag is set upon receiving the EOF symbol. 21.5.2.7 Inter-Frame Separation Symbol (IFS) The IFS symbol is a 20-µs passive period on the J1850 bus which allows proper synchronization between nodes during continuous message transmission. The IFS symbol is transmitted by a node after the completion of the end-of-frame (EOF) period and, therefore, is seen as a 300-µs passive period. When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time has expired, all nodes then must wait for the IFS symbol time to expire before transmitting a start-of-frame (SOF) symbol, marking the beginning of another message. However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a rising edge is detected before the IFS time has expired, it will synchronize internally to that edge. A rising edge may occur during the IFS period because of varying clock tolerances and loading of the J1850 bus, causing different nodes to observe the completion of the IFS period at different times. To allow for individual clock tolerances, receivers must synchronize to any SOF occurring during an IFS period. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface 21.5.2.8 Break (BREAK) The BDLC cannot transmit a BREAK symbol. Freescale Semiconductor, Inc... If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission error had occurred and halts transmission. If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception error and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while receiving a message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a reception error, sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2 is cleared automatically). If bus control is required after the BREAK symbol is received and the IFS time has elapsed, the programmer must resend the transmission byte using highest priority. NOTE: The J1850 protocol BREAK symbol is not related to the M68HC08 break module (see Section 12. Break Module). 21.5.2.9 Idle Bus (IDLE) An idle condition exists on the bus during any passive period after expiration of the IFS period (for example, > 300 µs). Any node sensing an idle bus condition can begin transmission immediately. 21.5.3 J1850 VPW Symbols Huntsinger’s variable pulse-width modulation (VPW) is an encoding technique in which each bit is defined by the time between successive transitions and by the level of the bus between transitions (for instance, active or passive). Active and passive bits are used alternately. This encoding technique is used to reduce the number of bus transitions for a given bit rate. Each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one of two lengths, either 64 µs or 128 µs (tNOM at 10.4 kbps baud rate), depending on the encoding of the previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) (EOF), and inter-frame separation (IFS) symbols always will be encoded at an assigned level and length. See Figure 21-7. Freescale Semiconductor, Inc... Each message will begin with an SOF symbol, an active symbol, and, therefore, each data byte (including the CRC byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. All VPW bit lengths stated in the following descriptions are typical values at a 10.4-kbps bit rate. EOF, EOD, IFS, and IDLE, however, are not driven J1850 bus states. They are passive bus periods observed by each node’s CPU. 21.5.3.1 Logic 0 A logic 0 is defined as either: • An active-to-passive transition followed by a passive period 64 µs in length, or • A passive-to-active transition followed by an active period 128 µs in length See Figure 21-7 (a). 21.5.3.2 Logic 1 A logic 1 is defined as either: • An active-to-passive transition followed by a passive period 128 µs in length, or • A passive-to-active transition followed by an active period 64 µs in length See Figure 21-7 (b). Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface ACTIVE 128 µs OR 64 µs OR 64 µs PASSIVE (A) LOGIC 0 Freescale Semiconductor, Inc... ACTIVE 128 µs PASSIVE (B) LOGIC 1 ACTIVE ≥ 240 µ s 200 µs 200 µs PASSIVE (C) BREAK (D) START OF FRAME (E) END OF DATA 300 µ s ACTIVE 280 µs 20 µs IDLE > 300 µs PASSIVE (F) END OF FRAME (G) INTER-FRAME SEPARATION (H) IDLE Figure 21-7. J1850 VPW Symbols with Nominal Symbol Times MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.5.3.3 Normalization Bit (NB) The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message responses. 21.5.3.4 Break Signal (BREAK) Freescale Semiconductor, Inc... The BREAK signal is defined as a passive-to-active transition followed by an active period of at least 240 µs (see Figure 21-7 (c)). 21.5.3.5 Start-of-Frame Symbol (SOF) The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length (see Figure 21-7 (d)). This allows the data bytes which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. 21.5.3.6 End-of-Data Symbol (EOD) The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in length (see Figure 21-7 (e)). 21.5.3.7 End-of-Frame Symbol (EOF) The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 µs in length (see Figure 21-7 (f)). If no IFR byte is transmitted after an EOD symbol is transmitted, after another 80 µs the EOD becomes an EOF, indicating completion of the message. 21.5.3.8 Inter-Frame Separation Symbol (IFS) The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS symbol contains no transition, since when it is used it always appends to a 280-µs EOF symbol (see Figure 21-7 (g)). 21.5.3.9 Idle An idle is defined as a passive period greater than 300 µs in length. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface 21.5.4 J1850 VPW Valid/Invalid Bits and Symbols Freescale Semiconductor, Inc... The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow for variations in oscillator frequencies. In many cases, the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol. Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a single period of the MUX interface clock (tBDLC), an apparent separation in these maximum time/minimum time concurrences equals one cycle of tBDLC. This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols. This is done without reducing the valid window for receiving bits and symbols from transmitters onto the J1850 bus, which has varying oscillator frequencies. In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the tolerances for both the passive and active data bits received and the symbols received are defined with no gaps between definitions. For example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1, and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol. 21.5.4.1 Invalid Passive Bit See Figure 21-8 (1). If the passive-to-active received transition beginning the next data bit or symbol occurs between the active-to-passive transition beginning the current data bit (or symbol) and a, the current bit would be invalid. 21.5.4.2 Valid Passive Logic 0 See Figure 21-8 (2). If the passive-to-active received transition beginning the next data bit (or symbol) occurs between a and b, the current bit would be considered a logic 0. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 200 µs 128 µs 64 µ s ACTIVE (1) INVALID PASSIVE BIT PASSIVE a ACTIVE (2) VALID PASSIVE LOGIC 0 PASSIVE Freescale Semiconductor, Inc... a b ACTIVE (3) VALID PASSIVE LOGIC 1 PASSIVE b c ACTIVE (4) VALID EOD SYMBOL PASSIVE c d Figure 21-8. J1850 VPW Received Passive Symbol Times 21.5.4.3 Valid Passive Logic 1 See Figure 21-8 (3). If the passive-to-active received transition beginning the next data bit (or symbol) occurs between b and c, the current bit would be considered a logic 1. 21.5.4.4 Valid EOD Symbol See Figure 21-8 (4). If the passive-to-active received transition beginning the next data bit (or symbol) occurs between c and d, the current symbol would be considered a valid end-of-data symbol (EOD). 21.5.4.5 Valid EOF and IFS Symbols In Figure 21-9 (1), if the passive-to-active received transition beginning the SOF symbol of the next message occurs between a and b, the current symbol will be considered a valid end-of-frame (EOF) symbol. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface 300 µ s 280 µ s ACTIVE (1) VALID EOF SYMBOL PASSIVE a b Freescale Semiconductor, Inc... ACTIVE (2) VALID EOF+ IFS SYMBOL PASSIVE c d Figure 21-9. J1850 VPW Received Passive EOF and IFS Symbol Times See Figure 21-9 (2). If the passive-to-active received transition beginning the SOF symbol of the next message occurs between c and d, the current symbol will be considered a valid EOF symbol followed by a valid inter-frame separation symbol (IFS). All nodes must wait until a valid IFS symbol time has expired before beginning transmission. However, due to variations in clock frequencies and bus loading, some nodes may recognize a valid IFS symbol before others and immediately begin transmitting. Therefore, any time a node waiting to transmit detects a passive-to-active transition once a valid EOF has been detected, it should immediately begin transmission, initiating the arbitration process. 21.5.4.6 Idle Bus In Figure 21-9 (2), if the passive-to-active received transition beginning the start-of-frame (SOF) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 200 µs 128 µs 64 µ s ACTIVE (1) INVALID ACTIVE BIT PASSIVE a ACTIVE (2) VALID ACTIVE LOGIC 1 Freescale Semiconductor, Inc... PASSIVE a b ACTIVE (3) VALID ACTIVE LOGIC 0 PASSIVE b c ACTIVE (4) VALID SOF SYMBOL PASSIVE c d Figure 21-10. J1850 VPW Received Active Symbol Times 21.5.4.7 Invalid Active Bit In Figure 21-10 (1), if the active-to-passive received transition beginning the next data bit (or symbol) occurs between the passive-to-active transition beginning the current data bit (or symbol) and a, the current bit would be invalid. 21.5.4.8 Valid Active Logic 1 In Figure 21-10 (2), if the active-to-passive received transition beginning the next data bit (or symbol) occurs between a and b, the current bit would be considered a logic 1. 21.5.4.9 Valid Active Logic 0 In Figure 21-10 (3), if the active-to-passive received transition beginning the next data bit (or symbol) occurs between b and c, the current bit would be considered a logic 0. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC MUX Interface 21.5.4.10 Valid SOF Symbol In Figure 21-10 (4), if the active-to-passive received transition beginning the next data bit (or symbol) occurs between c and d, the current symbol would be considered a valid SOF symbol. Freescale Semiconductor, Inc... 21.5.4.11 Valid BREAK Symbol In Figure 21-11, if the next active-to-passive received transition does not occur until after e, the current symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See 21.5.2 J1850 Frame Format for BDLC response to BREAK symbols. 240 µ s ACTIVE (2) VALID BREAK SYMBOL PASSIVE e Figure 21-11. J1850 VPW Received BREAK Symbol Times 21.5.5 Message Arbitration Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the message with the highest priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the SOF symbol and continue with each bit thereafter. If a write to the BDR (for instance, to initiate transmission) occurred on or before MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Freescale Semiconductor, Inc... 104 • tBDLC from the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU write to the BDR occurred after 104 • tBDLC from the detection of the rising edge, then the BDLC will not transmit, but will wait for the next IFS period to expire before attempting to transmit the byte. The variable pulse-width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive type) simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to be recessive. Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, it loses arbitration and immediately stops transmitting. This is known as bitwise arbitration. Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitration. For instance, a message with priority 000 will win arbitration over a message with priority 011. This method of arbitration will work no matter how many bits of priority encoding are contained in the message. 0 1 1 0 1 1 TRANSMITTER A DETECTS AN ACTIVE STATE ON THE BUS AND STOPS TRANSMITTING 1 ACTIVE TRANSMITTER A PASSIVE 0 0 ACTIVE TRANSMITTER B TRANSMITTER B WINS ARBITRATION AND CONTINUES TRANSMITTING PASSIVE 0 1 1 0 0 DATA DATA DATA DATA DATA BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 ACTIVE J1850 BUS PASSIVE SOF Figure 21-12. J1850 VPW Bitwise Arbitrations Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Controller-Digital (BDLC-D) BDLC Protocol Handler During arbitration, or even throughout the transmitting message, when an opposite bit is detected, transmission is stopped immediately unless it occurs on the 8th bit of a byte. In this case, the BDLC automatically will append up to two extra logic 1 bits and then stop transmitting. These two extra bits will be arbitrated normally and thus will not interfere with another message. The second logic 1 bit will not be sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two extra logic 1s will not corrupt the current message. However, if the BDLC has lost arbitration due to noise on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored as a noise-corrupted message. 21.6 BDLC Protocol Handler The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error detection. The protocol handler conforms to SAE J1850 Class B Data Communications Network Interface. NOTE: Motorola assumes that the reader is familiar with the J1850 specification before reading this protocol handler description. TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 21-13. BDLC Block Diagram MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.6.1 Protocol Architecture The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift register, Tx shift register, and loopback multiplexer as shown in Figure 21-14. TO PHYSICAL INTERFACE ALOOP CONTROL LOOPBACK MULTIPLEXER RxD DLOOP FROM BCR2 LOOPBACK CONTROL BDTxD BDTxD Freescale Semiconductor, Inc... BDRxD STATE MACHINE Tx SHADOW REGISTER 8 Tx DATA Rx SHADOW REGISTER CONTROL Tx SHIFT REGISTER Rx DATA Rx SHIFT REGISTER 8 TO CPU INTERFACE AND Rx/Tx BUFFERS Figure 21-14. BDLC Protocol Handler Outline 21.6.2 Rx and Tx Shift Registers The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850 bus. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC Protocol Handler 21.6.3 Rx and Tx Shadow Registers Freescale Semiconductor, Inc... Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to the Rx shadow register and RDRF or RXIFR is set (see 21.7.4 BDLC State Vector Register). An interrupt is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new data byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to shift in the next byte of data. Data in the Rx shadow register must be retrieved by the CPU before it is overwritten by new data from the Rx shift register. Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register is ready to accept new data from the CPU when the TDRE flag in the BSVR is set. 21.6.4 Digital Loopback Multiplexer The digital loopback multiplexer connects RxD to either BDTxD or BDRxD, depending on the state of the DLOOP bit in the BCR2 (see 21.7.3 BDLC Control Register 2). 21.6.5 State Machine All functions associated with performing the protocol are executed or controlled by the state machine. The state machine is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The following sections describe the BDLC’s actions in a variety of situations. 21.6.5.1 4X Mode The BDLC can exist on the same J1850 bus as modules which use a special 4X (41.6 kbps) mode of J1850 variable pulse width modulation (VPW) operation. The BDLC cannot transmit in 4X mode, but it can receive messages in 4X mode, if the RX4XE bit is set in BCR2. If the MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) RX4XE bit is not set in the BCR2, any 4X message on the J1850 bus is treated as noise by the BDLC and is ignored. Freescale Semiconductor, Inc... 21.6.5.2 Receiving a Message in Block Mode Although not a part of the SAE J1850 protocol, the BDLC does allow for a special block mode of operation of the receiver. As far as the BDLC is concerned, a block mode message is simply a long J1850 frame that contains an indefinite number of data bytes. All other features of the frame remain the same, including the SOF, CRC, and EOD symbols. Another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. This is usually accomplished by sending a special predefined message. 21.6.5.3 Transmitting a Message in Block Mode A block mode message is transmitted inherently by simply loading the bytes one by one into the BDR until the message is complete. The programmer should wait until the TDRE flag (see 21.7.4 BDLC State Vector Register) is set prior to writing a new byte of data into the BDR. The BDLC does not contain any predefined maximum J1850 message length requirement. 21.6.5.4 J1850 Bus Errors The BDLC detects several types of transmit and receive errors which can occur during the transmission of a message onto the J1850 bus. Transmission Error If the message transmitted by the BDLC contains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmission error. When a transmission error is detected, the BDLC immediately will cease transmitting. The error condition is reflected in the BSVR (see Table 21-5). If the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is generated. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC Protocol Handler CRC Error A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of a received message are processed and the CRC calculation result is not equal. The CRC code will detect any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. The CRC error flag (in BSVR) is set when a CRC error is detected (see 21.7.4 BDLC State Vector Register). Freescale Semiconductor, Inc... Symbol Error A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the J1850 bus. The invalid symbol is set when a symbol error is detected (see 21.7.4 BDLC State Vector Register). Framing Error A framing error is detected if an EOD or EOF symbol is detected on a non-byte boundary from the J1850 bus. A framing error also is detected if the BDLC is transmitting the EOD and instead receives an active symbol. The symbol invalid, or the out-of-range flag, is set when a framing error is detected (see 21.7.4 BDLC State Vector Register). Bus Fault If a bus fault occurs, the response of the BDLC will depend upon the type of bus fault. If the bus is shorted to battery, the BDLC will wait for the bus to fall to a passive state before it will attempt to transmit a message. As long as the short remains, the BDLC will never attempt to transmit a message onto the J1850 bus. If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit the message, and then detect a transmission error (in BSVR), since the short to ground would not allow the bus to be driven to the active (dominant) SOF state. The BDLC will abort that transmission and wait for the next CPU command to transmit. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC will resume normal operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850 bus. (See 21.7.4 BDLC State Vector Register.) Freescale Semiconductor, Inc... BREAK — Break If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol (in BSVR) interrupt will be generated. Reading the BSVR (see 21.7.4 BDLC State Vector Register) will clear this interrupt condition. The BDLC will wait for the bus to idle, then wait for a start-of-frame (SOF) symbol. The BDLC cannot transmit a BREAK symbol. It only can receive a BREAK symbol from the J1850 bus. 21.6.5.5 Summary Table 21-1. BDLC J1850 Bus Error Summary Error Condition BDLC Function Transmission error For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. BDLC stops transmission. Cyclical redundancy check (CRC) error CRC error interrupt will be generated. The BDLC will wait for EOF. Invalid symbol: BDLC transmits, but receives invalid bits (noise) The BDLC will abort transmission immediately. Invalid symbol interrupt will be generated. Framing error Invalid symbol interrupt will be generated. The BDLC will wait for end of frame (EOF). Bus short to VDD The BDLC will not transmit until the bus is idle. Invalid symbol interrupt will be generated. EOF interrupt also must be seen before another transmission attempt. Depending on length of the short, LOA flag also may be set. Bus short to GND Thermal overload will shut down physical interface. Fault condition is seen as invalid symbol flag. EOF interrupt must also be seen before another transmission attempt. BDLC receives BREAK symbol Invalid symbol interrupt will be generated. The BDLC will wait for the next valid SOF. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface 21.7 BDLC CPU Interface The CPU interface provides the interface between the CPU and the BDLC and consists of these five user registers: 1. BDLC analog and roundtrip delay register (BARD) 2. BDLC control register 1 (BCR1) 3. BDLC control register 2 (BCR2) Freescale Semiconductor, Inc... 4. BDLC state vector register (BSVR) 5. BDLC data register (BDR) TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 21-15. BDLC Block Diagram MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.7.1 BDLC Analog and Roundtrip Delay This register programs the BDLC to compensate for various delays of different external transceivers. The default delay value is 16 µs. Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The BARD register can be written only once after each reset, after which they become read-only bits. The register may be read at any time. Freescale Semiconductor, Inc... Address: Read: $003B Bit 7 6 ATE RXPOL 1 1 5 4 0 0 0 0 3 2 1 Bit 0 BO3 BO2 BO1 BO0 0 1 1 1 Write: Reset: = Unimplemented Figure 21-16. BDLC Analog and Roundtrip Delay Register (BARD) ATE — Analog Transceiver Enable Bit The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog transceiver. 1 = Select on-board analog transceiver 0 = Select off-chip analog transceiver NOTE: This device does not contain an on-board transceiver. This bit should be programmed to a logic 0 for proper operation. RXPOL — Receive Pin Polarity Bit The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it back to the digital receive pin. 1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the external transceiver does not invert the receive signal 0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850 bus Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface BO3–BO0 — BARD Offset Bits Table 21-2 shows the expected transceiver delay with respect to BARD offset values. Freescale Semiconductor, Inc... Table 21-2. BDLC Transceiver Delay BARD Offset Bits BO[3:0] Corresponding Expected Transceiver’s Delays (µs) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 21.7.2 BDLC Control Register 1 This register is used to configure and control the BDLC. Address: $003C Bit 7 6 5 4 IMSG CLKS R1 R0 Read: Write: Reset: 1 1 R = Reserved 1 0 3 2 0 0 R R 0 0 1 Bit 0 IE WCM 0 0 Figure 21-17. BDLC Control Register 1 (BCR1) MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) IMSG — Ignore Message Bit Freescale Semiconductor, Inc... This bit is used to disable the receiver until a new start-of-frame (SOF) is detected. 1 = Disable receiver. When set, all BDLC interrupt requests will be masked (except $20 in BSVR) and the status bits will be held in their reset state. If this bit is set while the BDLC is receiving a message, the rest of the incoming message will be ignored. 0 = Enable receiver. This bit is cleared automatically by the reception of an SOF symbol or a BREAK symbol. It will then generate interrupt requests and will allow changes of the status register to occur. However, these interrupts may still be masked by the interrupt enable (IE) bit. CLKS — Clock Bit For J1850 bus communications to take place, the nominal BDLC operating frequency (fBDLC) must always be 1.048576 MHz or 1 MHz. The CLKS register bit allows the user to select the frequency (1.048576 MHz or 1 MHz) used to automatically adjust symbol timing. 1 = Binary frequency (1.048576 MHz) selected for fBDLC 0 = Integer frequency (1 MHz) selected for fBDLC R1 and R0 — Rate Select Bits These bits determine the amount by which the frequency of the MCU CGMXCLK signal is divided to form the MUX interface clock (fBDLC) which defines the basic timing resolution of the MUX interface. They may be written only once after reset, after which they become read-only bits. The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0 MHz for J1850 bus communications to take place. Hence, the value programmed into these bits is dependent on the chosen MCU system clock frequency per Table 21-3. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface Freescale Semiconductor, Inc... 1= Table 21-3. BDLC Rate Selection fXCLK Frequency R1 R0 Division fBDLC 1.049 MHz 0 0 1 1.049 MHz 2.097 MHz 0 1 2 1.049 MHz 4.194 MHz 1 0 4 1.049 MHz 8.389 MHz 1 1 8 1.049 MHz 1.000 MHz 0 0 1 1.00 MHz 2.000 MHz 0 1 2 1.00 MHz 4.000 MHz 1 0 4 1.00 MHz 8.000 MHz 1 1 8 1.00 MHz IE— Interrupt Enable Bit This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. Interrupt requests will be maintained until all of the interrupt request sources are cleared by performing the specified actions upon the BDLC’s registers. Interrupts that were pending at the time that this bit is cleared may be lost. 1 = Enable interrupt requests from BDLC 0 = Disable interrupt requests from BDLC If the programmer does not wish to use the interrupt capability of the BDLC, the BDLC state vector register (BSVR) can be polled periodically by the programmer to determine BDLC states. See 21.7.4 BDLC State Vector Register for a description of the BSVR. WCM — Wait Clock Mode Bit This bit determines the operation of the BDLC during CPU wait mode. See 21.8.2 Stop Mode and 21.8.1 Wait Mode for more details on its use. 1 = Stop BDLC internal clocks during CPU wait mode 0 = Run BDLC internal clocks during CPU wait mode MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.7.3 BDLC Control Register 2 This register controls transmitter operations of the BDLC. It is recommended that BSET and BCLR instructions be used to manipulate data in this register to ensure that the register’s content does not change inadvertently. Address: $003D Bit 7 6 5 4 3 2 1 Bit 0 ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 1 1 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read: Write: Reset: Figure 21-18. BDLC Control Register 2 (BCR2) ALOOP — Analog Loopback Mode Bit This bit determines whether the J1850 bus will be driven by the analog physical interface’s final drive stage. The programmer can use this bit to reset the BDLC state machine to a known state after the off-chip analog transceiver is placed in loopback mode. When the user clears ALOOP, to indicate that the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol before attempting to transmit. Most transceivers have the ALOOP feature available. 1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver. The J1850 bus is not driven. 0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the BDLC requires the bus to be idle for a minimum of end-of-frame symbol time (tTRV4) before message reception or a minimum of inter-frame symbol time (tTRV6) before message transmission. See 24.15 BDLC Receiver VPW Symbol Timings. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface Freescale Semiconductor, Inc... DLOOP — Digital Loopback Mode Bit This bit determines the source to which the digital receive input (BDRxD) is connected and can be used to isolate bus fault conditions (see Figure 21-14). If a fault condition has been detected on the bus, this control bit allows the programmer to connect the digital transmit output to the digital receive input. In this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. If no faults exist in the BDLC, the fault is in the physical interface block or elsewhere on the J1850 bus. 1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital loopback mode. 0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken out of digital loopback mode and can now drive or receive the J1850 bus normally (given ALOOP is not set). After writing DLOOP to 0, the BDLC requires the bus to be idle for a minimum of end-of-frame symbol (ttv4) time before allowing a reception of a message. The BDLC requires the bus to be idle for a minimum of inter-frame separator symbol (ttv6) time before allowing any message to be transmitted. RX4XE — Receive 4X Enable Bit This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature is useful for fast downloading of data into a J1850 node for diagnostic or factory programming of the node. 1 = When set, the BDLC is put in 4X receive-only operation. 0 = When cleared, the BDLC transmits and receives at 10.4 kbps. Reception of a BREAK symbol automatically clears this bit and sets BDLC state vector register (BSVR) to $001C. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) NBFS — Normalization Bit Format Select Bit Freescale Semiconductor, Inc... This bit controls the format of the normalization bit (NB) (see Figure 21-19). SAE J1850 strongly encourages using an active long (logic 0) for in-frame responses containing cyclical redundancy check (CRC) and an active short (logic 1) for in-frame responses without CRC. 1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR) ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR) does not end with a CRC byte. 0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR) ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR) does not end with a CRC byte. TEOD — Transmit End-of-Data Bit This bit is set by the programmer to indicate the end of a message is being sent by the BDLC. It will append an 8-bit CRC after completing transmission of the current byte. This bit also is used to end an in-frame response (IFR). If the transmit shadow register is full when TEOD is set, the CRC byte will be transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have been transmitted. (See 21.6.3 Rx and Tx Shadow Registers for a description of the transmit shadow register.) Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector register (BSVR) is cleared to allow lower priority interrupts to occur. (See 21.7.4 BDLC State Vector Register.) 1 = Transmit end-of-data (EOD) symbol 0 = The TEOD bit will be cleared automatically at the rising edge of the first CRC bit that is sent or if an error is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC receives back a valid EOD symbol or an error condition occurs. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits Freescale Semiconductor, Inc... These three bits control the type of in-frame response being sent. The programmer should not set more than one of these control bits to a 1 at any given time. However, if more than one of these three control bits are set to 1, the priority encoding logic will force these register bits to a known value as shown in Table 21-4. For example, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally they will be encoded as 010. However, when these bits are read back, they will read 011. Table 21-4. BDLC Transmit In-Frame Response Control Bit Priority Encoding Write/Read TSIFR Write/Read TMIFR1 Write/Read TMIFR0 Actual TSIFR Actual TMIFR1 Actual TMIFR0 0 0 0 0 0 0 1 X X 1 0 0 0 1 X 0 1 0 0 0 1 0 0 1 The BDLC supports the in-frame response (IFR) feature of J1850 by setting these bits correctly. The four types of J1850 IFR are shown in the following figure. The purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal ID or physical address in a concatenated manner after they have seen the EOD symbol. If transmission arbitration is lost by a node while sending its response, it continues to transmit its ID/address until observing its unique byte in the response stream. For VPW modulation, the first bit of the IFR is always passive; therefore, an active normalization bit must be generated by the responder and sent prior to its ID/address byte. When there are multiple responders on the J1850 bus, only one normalization bit is sent which assists all other transmitting nodes to sync their responses. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) CRC CRC EOD DATA FIELD EOF EOD SOF HEADER TYPE 0 — NO IFR DATA FIELD NB EOF EOD SOF HEADER ID TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER NB ID1 ID N TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS DATA FIELD CRC NB CRC (OPTIONAL) IFR DATA FIELD EOF EOD HEADER EOD SOF Freescale Semiconductor, Inc... CRC EOF EOD DATA FIELD EOD SOF HEADER TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER NB = Normalization bit ID = Identifier, usually the physical address of the responder(s) Figure 21-19. Types of In-Frame Response (IFR) TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the transmitting (responding) node. See Figure 21-19. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by the byte in the BDR. 0 = The TSIFR bit will be cleared automatically, once the BDLC has successfully transmitted the byte in the BDR onto the bus, or TEOD is set, or an error is detected on the bus. If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received from the bus, the TSIFR bit will remain in the reset state and no attempt will be made to transmit the IFR byte. If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR byte winning arbitration completes transmission, the BDLC Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface will again attempt to transmit the BDR (with no normalization bit). The BDLC will continue transmission attempts until an error is detected on the bus, or TEOD is set, or the BDLC transmission is successful. If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will not be sent out because the BDLC will attempt to retransmit the byte in the transmit shift register after the IRF byte winning arbitration completes transmission. TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit Freescale Semiconductor, Inc... The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. Response IFR bytes are still subject to J1850 message length maximums (see 21.5.2 J1850 Frame Format). See Figure 21-19. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received, the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into the BDR. After TEOD has been set and the last IFR byte has been transmitted, the CRC byte is transmitted. 0 = The TMIFR1 bit will be cleared automatically, once the BDLC has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR after the TDRE interrupt. If the TMIFR1 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt (see 21.7.4 BDLC State Vector Register) will occur similar to the main message transmit sequence. The programmer should then load the next byte of the IFR into the BDR for transmission. When the last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the BDLC control register 2 (BCR2). This will instruct the BDLC to transmit a CRC byte once the byte in the BDR is transmitted, and then transmit an EOD symbol, indicating the end of the IFR portion of the message frame. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) However, if the programmer wishes to transmit a single byte followed by a CRC byte, the programmer should load the byte into the BDR before the EOD symbol has been received, and then set the TMIFR1 bit. Once the TDRE interrupt occurs, the programmer should then set the TEOD bit in the BCR2. This will result in the byte in the BDR being the only byte transmitted before the IFR CRC byte, and no TDRE interrupt will be generated. Freescale Semiconductor, Inc... If the programmer attempts to set the TMIFR1 bit immediately after the EOD symbol has been received from the bus, the TMIFR1 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte. If a loss of arbitration occurs when the BDLC is transmitting any byte of a multiple byte IFR, the BDLC will go to the loss of arbitration state, set the appropriate flag, and cease transmission. If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be cleared and no attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will be sent out. NOTE: The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition fault. This is helpful in preventing noise on the J1850 bus from corrupting a message. TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR without CRC. Response IFR bytes are still subject to J1850 message length maximums (see 21.5.2 J1850 Frame Format). See Figure 21-19. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received, the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into the BDR. After TEOD has been set, the last IFR byte to be transmitted will be the last byte which was written into the BDR. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface Freescale Semiconductor, Inc... 0 = The TMIFR0 bit will be cleared automatically, once the BDLC has successfully transmitted the EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the BDR after the TDRE interrupt. If the TMIFR0 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt (see 21.7.4 BDLC State Vector Register) will occur similar to the main message transmit sequence. The programmer should then load the next byte of the IFR into the BDR for transmission. When the last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the BCR2. This will instruct the BDLC to transmit an EOD symbol once the byte in the BDR is transmitted, indicating the end of the IFR portion of the message frame. The BDLC will not append a CRC when the TMIFR0 is set. If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the bus, the TMIFR0 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte. If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will be cleared, and no attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits (active short bits) will be sent out. NOTE: The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition fault. This is helpful in preventing noise onto the J1850 bus from a corrupted message. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.7.4 BDLC State Vector Register This register is provided to substantially decrease the CPU overhead associated with servicing interrupts while under operation of a multiplex protocol. It provides an index offset that is directly related to the BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state machine in software. Freescale Semiconductor, Inc... Address: Read: $003E Bit 7 6 5 4 3 2 1 Bit 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 21-20. BDLC State Vector Register (BSVR) I0, I1, I2, and I3 — Interrupt Source Bits These bits indicate the source of the interrupt request that currently is pending. The encoding of these bits are listed in Table 21-5. Table 21-5. BDLC Interrupt Sources BSVR I3 I2 I1 I0 Interrupt Source Priority $00 0 0 0 0 No interrupts pending 0 (lowest) $04 0 0 0 1 Received EOF 1 $08 0 0 1 0 Received IFR byte (RXIFR) 2 $0C 0 0 1 1 BDLC Rx data register full (RDRF) 3 $10 0 1 0 0 BDLC Tx data register empty (TDRE) 4 $14 0 1 0 1 Loss of arbitration 5 $18 0 1 1 0 Cyclical redundancy check (CRC) error 6 $1C 0 1 1 1 Symbol invalid or out of range 7 $20 1 0 0 0 Wakeup 8 (highest) Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) BDLC CPU Interface Freescale Semiconductor, Inc... Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2. Upon receiving a BDLC interrupt, the user can read the value within the BSVR, transferring it to the CPU’s index register. The value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine. For example: Service * * JMPTAB LDX JMP BSVR JMPTAB,X Fetch State Vector Number Enter service routine, (must end in RTI) JMP NOP JMP NOP JMP NOP SERVE0 Service condition #0 SERVE1 Service condition #1 SERVE2 Service condition #2 SERVE8 Service condition #8 * JMP END NOTE: The NOPs are used only to align the JMPs onto 4-byte boundaries so that the value in the BSVR can be used intact. Each of the service routines must end with a return-from-interrupt (RTI) instruction to guarantee correct continued operation of the device. Note also that the first entry can be omitted since it corresponds to no interrupt occurring. The service routines should clear all of the sources that are causing the pending interrupts. Note that the clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0, I1, and I2 of the BSVR will then reflect the source of the remaining interrupt request. If fewer states are used or if a different software approach is taken, the jump table can be made smaller or omitted altogether. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) 21.7.5 BDLC Data Register Address: $003F Bit 7 6 5 4 3 2 1 Bit 0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 Read: Write: Reset: Indeterminate after reset Freescale Semiconductor, Inc... Figure 21-21. BDLC Data Register (BDR) This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass data received from the J1850 bus to the CPU. Each data byte (after the first one) should be written only after a Tx data register empty (TDRE) state is indicated in the BSVR. Data read from this register will be the last data byte received from the J1850 bus. This received data should only be read after an Rx data register full (RDRF) interrupt has occurred. See 21.7.4 BDLC State Vector Register. The BDR is double buffered via a transmit shadow register and a receive shadow register. After the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the TDRE flag is set, and the shadow register is ready to accept the next data byte. The receive shadow register works similarly. Once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. The RDRF flag is set to indicate that a new byte of data has been received. The programmer has one BDLC byte reception time to read the shadow register and clear the RDRF flag before the shadow register is overwritten by the newly received byte. To abort an in-progress transmission, the programmer should stop loading data into the BDR. This will cause a transmitter underrun error and the BDLC automatically will disable the transmitter on the next non-byte boundary. This means that the earliest a transmission can be Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Low-Power Modes halted is after at least one byte plus two extra logic 1s have been transmitted. The receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error. NOTE: The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition fault. This is helpful in preventing noise on the J1850 bus from corrupting a message. Freescale Semiconductor, Inc... 21.8 Low-Power Modes This subsection describes wait mode and stop mode. 21.8.1 Wait Mode This power-conserving mode is entered automatically from run mode whenever the CPU executes a WAIT instruction and the WCM bit in BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode, the BDLC cannot drive any data. A subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the BDLC to wake up and generate a CPU interrupt request if the interrupt enable (IE) bit in the BDLC control register 1 (BCR1) is previously set (see 21.7.2 BDLC Control Register 1 for a better understanding of IE). This results in less of a power saving, but the BDLC is guaranteed to receive correctly the message which woke it up, since the BDLC internal operating clocks are kept running. NOTE: Ensuring that all transmissions are complete or aborted before putting the BDLC into wait mode is important. 21.8.2 Stop Mode This power-conserving mode is entered automatically from run mode whenever the CPU executes a STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BDLC control register 1 (BCR1) is previously set. This is the lowest power mode that the BDLC can enter. MC68HC908AS60 — Rev. 1.0 Technical Data Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Byte Data Link Controller-Digital (BDLC-D) Freescale Semiconductor, Inc... A subsequent passive-to-active transition on the J1850 bus will cause the BDLC to wake up and generate a non-maskable CPU interrupt request. When a STOP instruction is used to put the BDLC in stop mode, the BDLC is not guaranteed to correctly receive the message which woke it up, since it may take some time for the BDLC internal operating clocks to restart and stabilize. If a WAIT instruction is used to put the BDLC in stop mode, the BDLC is guaranteed to correctly receive the byte which woke it up, if and only if an end-of-frame (EOF) has been detected prior to issuing the WAIT instruction by the CPU. Otherwise, the BDLC will not correctly receive the byte that woke it up. If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC internal operating clocks to restart and stabilize before normal communications can resume. Therefore, the BDLC is not guaranteed to receive that message correctly. NOTE: It is important to ensure that all transmissions are complete or aborted prior to putting the BDLC into stop mode. Technical Data MC68HC908AS60 — Rev. 1.0 Byte Data Link Controller-Digital (BDLC-D) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 22. Timer Interface Module A (TIMA-6) Freescale Semiconductor, Inc... 22.1 Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 22.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 380 22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 22.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 22.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 382 22.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .383 22.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 385 22.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 386 22.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 387 22.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 22.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 22.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 391 22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 22.8.1 TIMA Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . 392 22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0). . . . . . . . . . . . . . . . . 392 22.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 22.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . 393 22.9.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 395 22.9.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 396 22.9.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 397 22.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 402 MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) 22.2 Introduction This section describes the timer interface module (TIMA). The TIMA is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 22-1 is a block diagram of the TIMA. 22.3 Features Freescale Semiconductor, Inc... Features of the TIMA include: • Six input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse-width-modulation (PWM) signal generation • Programmable TIMA clock input: – 7-frequency internal bus clock prescaler selection – External TIMA clock input (4-MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMA counter stop and reset bits Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Features TCLK PTD6/TACLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR Freescale Semiconductor, Inc... TMODH:TMODL CHANNEL 0 ELS0B ELS0A TOV0 CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L CH0F 16-BIT LATCH MS0A CHANNEL 1 ELS1B MS0B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L CH0IE CH1F 16-BIT LATCH CH1IE MS1A CHANNEL 2 ELS2B ELS2A TOV2 CH2MAX 16-BIT COMPARATOR TCH2H:TCH2L CH2F 16-BIT LATCH MS2A CHANNEL 3 ELS3B MS2B ELS3A TOV3 CH3MAX 16-BIT COMPARATOR TCH3H:TCH3L CH2IE CH3F 16-BIT LATCH CH3IE MS3A CHANNEL 4 ELS4B ELS4A TOV4 CH5MAX 16-BIT COMPARATOR TCH4H:TCH4L CH4F 16-BIT LATCH MS4A CHANNEL 5 ELS5B MS4B ELS5A TOV5 CH5MAX 16-BIT COMPARATOR TCH5H:TCH5L CH4IE CH5F 16-BIT LATCH MS5A CH5IE PTE2 LOGIC PTE2/TACH0 INTERRUPT LOGIC PTE3 LOGIC PTE3/TACH1 INTERRUPT LOGIC PTF0 LOGIC PTF0/TACH2 INTERRUPT LOGIC PTF1 LOGIC PTF1/TACH3 INTERRUPT LOGIC PTF2 LOGIC PTF2 INTERRUPT LOGIC PTF3 LOGIC PTF3 INTERRUPT LOGIC Figure 22-1. TIMA Block Diagram MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Addr. $0020 Register Name Read: Timer A Status and Control Register (TASC) Write: See page 393. Reset: Freescale Semiconductor, Inc... $0023 $0024 $0025 $0026 $0027 $0028 $0029 TOF 6 5 TOIE TSTOP 0 4 3 0 0 TRST R 2 1 Bit 0 PS2 PS1 PS0 0 0 1 0 0 0 0 0 Read: Timer A Counter Register High (TACNTH) Write: See page 395. Reset: Bit 15 14 13 12 11 10 9 Bit 8 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Timer A Counter Register Low (TACNTL) Write: See page 395. Reset: Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 $0021 $0022 Bit 7 Unimplemented Read: Timer A Modulo Register High (TAMODH) Write: See page 396. Reset: Read: Timer A Modulo Register Low (TAMODL) Write: See page 396. Reset: Read: Timer A Channel 0 Status and Control Register (TASC0) Write: See page 397. Reset: Read: Timer A Channel 0 Register High (TACH0H) Write: See page 403. Reset: Read: Timer A Channel 0 Register Low (TACH0L) Write: See page 403. Reset: Read: Timer A Channel 1 Status and Control Register (TASC1) Write: See page 397. Reset: CH0F 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH1F CH1IE 0 0 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 R 0 0 = Unimplemented R = Reserved Figure 22-2. TIMA I/O Register Summary (Sheet 1 of 3) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Features Addr. $002A Freescale Semiconductor, Inc... $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 Register Name Read: Timer A Channel 1 Register High (TACH1H) Write: See page 403. Reset: Read: Timer A Channel 1 Register Low (TACH1L) Write: See page 403. Reset: Read: Timer A Channel 2 Status and Control Register (TASC2) Write: See page 397. Reset: Read: Timer A Channel 2 Register High (TACH2H) Write: See page 403. Reset: Read: Timer A Channel 2 Register Low (TACH2L) Write: See page 403. Reset: Read: Timer A Channel 3 Status and Control Register (TASC3) Write: See page 397. Reset: Read: Timer A Channel 3 Register High (TACH3H) Write: See page 403. Reset: Read: Timer A Channel 3 Register Low (TACH3L) Write: See page 403. Reset: Read: Timer A Channel 4 Status and Control Register (TASC4) Write: See page 397. Reset: Read: Timer A Channel 4 Register High (TACH4H) Write: See page 403. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH3F CH3IE 0 0 MS3A ELS3B ELS3A TOV3 CH3MAX R 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset CH4F CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 0 Indeterminate after reset = Unimplemented R = Reserved Figure 22-2. TIMA I/O Register Summary (Sheet 2 of 3) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Addr. $0034 Freescale Semiconductor, Inc... $0035 $0036 $0037 Register Name Read: Timer A Channel 4 Register Low (TACH4L) Write: See page 403. Reset: Read: Timer A Channel 5 Status and Control Register (TASC5) Write: See page 397. Reset: Read: Timer A Channel 5 Register High (TACH5H) Write: See page 403. Reset: Read: Timer A Channel 5 Register Low (TACH5L) Write: See page 403. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Indeterminate after reset CH5F CH5IE 0 0 MS5A ELS5B ELS5A TOV5 CH5MAX R 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset = Unimplemented R = Reserved Figure 22-2. TIMA I/O Register Summary (Sheet 3 of 3) 22.4 Functional Description Figure 22-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing reference for the input capture and output compare functions. The TIMA counter modulo registers, TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The six TIMA channels are programmable independently as input capture or output compare channels. 22.4.1 TIMA Counter Prescaler The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Functional Description Freescale Semiconductor, Inc... 22.4.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC5 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. The result obtained by an input capture will be two more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. The free-running counter contents are transferred to the TIMA channel status and control register (TACHxH–TACHxL) (see 22.9.5 TIMA Channel Registers) on each proper signal transition regardless of whether the TIMA channel flag (CH0F–CH5F in TASC0–TASC5 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this value is stored in the input capture register two bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range. MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Timer Interface Module A (TIMA-6) Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 22.9.5 TIMA Channel Registers). Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Reset does not affect the contents of the input capture channel register (TACHxH–TACHxL). 22.4.3 Output Compare With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests. 22.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 22.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Functional Description Freescale Semiconductor, Inc... Use these methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable channel x TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 22.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors the buffered output compare function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the output. MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Freescale Semiconductor, Inc... Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The output compare value in the TIMA channel 2 registers initially controls the output on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the PTF2 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS4B bit in TIMA channel 4 status and control register (TSC4) links channel 4 and channel 5. The output compare value in the TIMA channel 4 registers initially controls the output on the PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors the buffered output compare function, and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Functional Description 22.4.4 Pulse-Width Modulation (PWM) Freescale Semiconductor, Inc... By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 22-3 shows, the output compare value in the TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to set the pin if the state of the PWM pulse is logic 0. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 22-3. PWM Period and Pulse Width The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 22.9.1 TIMA Status and Control Register. The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50 percent. MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) 22.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 22.4.4 Pulse-Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMA channel registers. Freescale Semiconductor, Inc... An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMA may pass the new value before it is written to the TIMA channel registers. Use these methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable channel x TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Functional Description 22.4.4.2 Buffered PWM Signal Generation Freescale Semiconductor, Inc... Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the PTF2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The TIMA channel 4 registers MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) initially control the pulse width on the PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the pulse width are the ones written to last. TASC4 controls and monitors the buffered PWM function, and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3, is available as a general-purpose I/O pin. Freescale Semiconductor, Inc... NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. 22.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization procedure: 1. In the TIMA status and control register (TASC): a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width. 4. In TIMA channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 22-2.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB–ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 22-2.) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Functional Description NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Freescale Semiconductor, Inc... 5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H–TACH2L) initially control the PWM output. TIMA status control register 2 (TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA channel 4 registers (TACH4H–TACH4L) initially control the PWM output. TIMA status control register 4 (TASC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority over MS4A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0 percent duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100 percent duty cycle output. (See 22.9.4 TIMA Channel Status and Control Registers.) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) 22.5 Interrupts Freescale Semiconductor, Inc... These TIMA sources can generate interrupt requests: • TIMA overflow flag (TOF) — The TOF bit is set when the TIMA counter value rolls over to $0000 after matching the value in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE, enables TIMA overflow CPU interrupt requests. TOF and TOIE are in the TIMA status and control register. • TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. 22.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 22.6.1 Wait Mode The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction. 22.6.2 Stop Mode The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop mode. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) TIMA During Break Interrupts 22.7 TIMA During Break Interrupts A break interrupt stops the TIMA counter and inhibits input captures. Freescale Semiconductor, Inc... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 9.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 22.8 I/O Signals Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares four of its pins with the TIMA. PTD6/TACLK is an external clock input to the TIMA prescaler. The six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, PTF1/TACH3, PTF2, and PTF3. MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) 22.8.1 TIMA Clock Pin (PTD6/ATD14/TCLK) PTD6/TACLK is an external clock input that can be the clock source for the TIMA counter instead of the prescaled internal bus clock. Select the PTD6/TACLK input by writing logic 1s to the three prescaler select bits, PS[2:0]. (See 22.9.1 TIMA Status and Control Register.) The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: Freescale Semiconductor, Inc... 1 ------------------------------------- + t SU bus frequency The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2. PTD6/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the TIMA clock input. When the PTD6/TACLK pin is the TIMA clock input, it is an input regardless of the state of the DDRD6 bit in data direction register D. 22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE2/TACH0, PTE6/TACH2, and PTF2 can be configured as buffered output compare or buffered PWM pins. 22.9 I/O Registers These I/O registers control and monitor TIMA operation: • TIMA status and control register (TASC) • TIMA control registers (TACNTH–TACNTL) • TIMA counter modulo registers (TAMODH–TAMODL) • TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4, and TSAC5) • TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L, and TACH5H–TACH5L) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers 22.9.1 TIMA Status and Control Register Freescale Semiconductor, Inc... The TIMA status and control register: • Enables TIMA overflow interrupts • Flags TIMA overflows • Stops the TIMA counter • Resets the TIMA counter • Prescales the TIMA counter clock Address: $0020 Bit 7 Read: 6 5 TOIE TSTOP TOF Write: 0 Reset: 0 R 0 1 4 3 0 0 TRST R 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Reserved Figure 22-4. Timer A Status and Control Register (TASC) TOF — TIMA Overflow Flag Bit This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMA counter has reached modulo value. 0 = TIMA counter has not reached modulo value. TOIE — TIMA Overflow Interrupt Enable Bit This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) TSTOP — TIMA Stop Bit This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit. 1 = TIMA counter stopped 0 = TIMA counter active Freescale Semiconductor, Inc... NOTE: Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit wait mode. Also, when the TSTOP bit is set and input capture mode is enabled, input captures are inhibited until TSTOP is cleared. TRST — TIMA Reset Bit Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIMA counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select either the PTD6/TACLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 22-1 shows. Reset clears the PS[2:0] bits. Table 22-1. Prescaler Selection PS[2:0] TIMA Clock Source 000 Internal bus clock ÷1 001 Internal bus clock ÷ 2 010 Internal bus clock ÷ 4 011 Internal bus clock ÷ 8 100 Internal bus clock ÷ 16 101 Internal bus clock ÷ 32 110 Internal bus clock ÷ 64 111 PTD6/TACLK Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers 22.9.2 TIMA Counter Registers The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter. Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers. Freescale Semiconductor, Inc... NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value latched during the break. Register Name and Address: TCNTH — $0022 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 Register Name and Address: TCNTL — $0023 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 22-5. TIMA Counter Registers (TCNTH and TCNTL) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) 22.9.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes counting from $0000 at the next clock. Writing to the high byte (TAMODH) inhibits the TOF bit and overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo registers. Freescale Semiconductor, Inc... Register Name and Address: TAMODH — $0024 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Read: Write: Reset: Register Name and Address: TAMODL — $0025 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 22-6. TIMA Counter Modulo Registers (TAMODH and TAMODL) NOTE: Reset the TIMA counter before writing to the TIMA counter modulo registers. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers 22.9.4 TIMA Channel Status and Control Registers Freescale Semiconductor, Inc... Each of the TIMA channel status and control registers: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIMA overflow • Selects 100 percent PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Register Name and Address: TASC0 — $0026 Bit 7 Read: CH0F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Register Name and Address: TASC1 — $0029 Bit 7 Read: 6 CH1F 5 0 CH1IE Write: 0 Reset: 0 R R 0 0 = Reserved Figure 22-7. TIMA Channel Status and Control Registers (TACC0–TASC5) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Register Name and Address: TASC2 — $002C Bit 7 Read: CH2F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 0 4 3 2 1 Bit 0 MS3A ELS3B ELS3A TOV3 CH3MAX 0 0 0 0 0 Register Name and Address: TASC3 — $002F Freescale Semiconductor, Inc... Bit 7 Read: 6 CH3F 5 0 CH3IE Write: 0 Reset: 0 R 0 0 Register Name and Address: TASC4 — $0032 Bit 7 Read: CH4F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX 0 0 0 0 0 0 0 4 3 2 1 Bit 0 MS5A ELS5B ELS5A TOV5 CH5MAX 0 0 0 0 0 Register Name and Address: TASC5 — $0035 Bit 7 Read: 6 CH5F 5 0 CH5IE Write: 0 Reset: 0 R R 0 0 = Reserved Figure 22-7. TIMA Channel Status and Control Registers (TACC0–TASC5) (Continued) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers CHxF — Channel x Flag Bit Freescale Semiconductor, Inc... When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMA counter registers matches the value in the TIMA channel x registers. When CHxIE = 0, clear CHxF by reading TIMA channel x status and control register with CHxF set, and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0, TIMA channel 2, and TIMA channel 4 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to general-purpose I/O. Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 22-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation Freescale Semiconductor, Inc... When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, output compare mode, or input capture mode is enabled. See Table 22-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F, and pin PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture mode, or output compare operation mode is enabled. Table 22-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers Table 22-2. Mode, Edge, and Level Selection MSxB:MSxA ELSxB:ELSxA X0 00 Mode Freescale Semiconductor, Inc... Output preset NOTE: X1 00 00 01 00 10 00 11 01 01 01 10 01 11 1X 01 1X 10 1X 11 Configuration Pin under port control; initialize timer output level high Pin under port control; initialize timer output level low Capture on rising edge only Input capture Capture on falling edge only Capture on rising or falling edge Output compare or PWM Buffered output compare or buffered PWM Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Before enabling a TIMA channel register for input capture operation, make sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two bus clocks. TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMA counter overflow. 0 = Channel x pin does not toggle on TIMA counter overflow. NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a channel x output compare if both occur at the same time. MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 percent. As Figure 22-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100 percent duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW Freescale Semiconductor, Inc... OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 22-8. CHxMAX Latency 22.9.5 TIMA Channel Registers These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown. In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMA channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMA channel x registers (TCHxH) inhibits output compares and the CHxF bit until the low byte (TCHxL) is written. Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers Register Name and Address: TACH0H — $0027 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Freescale Semiconductor, Inc... Register Name and Address: TACH0L — $0028 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH1H — $002A Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH1L — $002B Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH2H — $002D Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Sheet 1 of 3) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) Register Name and Address: TACH2L — $002E Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Freescale Semiconductor, Inc... Register Name and Address: TACH3H — $0030 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH3L — $0031 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH4H — $0033 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Register Name and Address: TACH4L — $0034 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Sheet 2 of 3) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Interface Module A (TIMA-6) I/O Registers Register Name and Address: TACH5H — $0036 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Freescale Semiconductor, Inc... Register Name and Address: TACH5L — $0037 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Sheet 3 of 3) MC68HC908AS60 — Rev. 1.0 Technical Data Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Timer Interface Module A (TIMA-6) Technical Data MC68HC908AS60 — Rev. 1.0 Timer Interface Module A (TIMA-6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 23. Analog-to-Digital Converter (ADC-15) Freescale Semiconductor, Inc... 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 23.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 23.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 23.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 23.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 23.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412 23.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 23.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH). . . . . . . . . . . . . . . . . . .412 23.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . 412 23.7.3 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 412 23.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 23.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 413 23.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 23.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 416 MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) 23.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC-15). 23.3 Features Freescale Semiconductor, Inc... Features of the ADC module include: • 15 channels with multiplexed input • Linear successive approximation • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock 23.4 Functional Description Fifteen ADC channels are available for sampling external sources at pins PTD6/TACLK–PTD0 and PTB7/ATD7–PTB0/ATD0. An analog multiplexer allows the single ADC converter to select one of 15 ADC channels as ADC voltage in (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 23-1. Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) Functional Description INTERNAL DATA BUS READ DDRB/DDRB WRITE DDRB/DDRD RESET WRITE PTB/PTD DISABLE DDRBx/DDRDx PTBx/PTDx PTBx/PTDx ADC CHANNEL x Freescale Semiconductor, Inc... READ PTB/PTD DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC VOLTAGE IN ADCVIN ADC CHANNEL SELECT ADCH[4:0] COCO ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 23-1. ADC Block Diagram 23.4.1 ADC Port I/O Pins PTD6/TACLK–PTD0 and PTB7/ATD7–PTB0/ATD0 are general-purpose input/output (I/O) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any effect on the port pin MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read. NOTE: Do not use ADC channels ATD14 or ATD12 when using the PTD6/TACLK or PTD4/TBLCK pins as the clock inputs for the 16-bit timers. Freescale Semiconductor, Inc... 23.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH (see 24.7 ADC Characteristics), the ADC converts the signal to $FF (full scale). If the input voltage equals VSSA, the ADC converts it to $00. Input voltages between VREFH and VSSA are a straight-line linear conversion. All other input voltages will result in $FF if greater than VREFH and $00 if less than VSSA. NOTE: Input voltage should not exceed the analog supply voltages. 23.4.3 Conversion Time Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between 16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example, with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz, one conversion will take between 16 and 17 µs and there will be between 128 bus cycles between each conversion. Sample rate is approximately 60 kHz. Refer to 24.7 ADC Characteristics. 16 to 17 ADC clock cycles Conversion time = ADC clock frequency Number of bus cycles = Conversion time x bus frequency Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) Interrupts 23.4.4 Continuous Conversion Freescale Semiconductor, Inc... In the continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO bit is set after the first conversion and will stay set for the next several conversions until the next write of the ADC status and control register or the next read of the ADC data register. 23.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. See 24.7 ADC Characteristics for accuracy information. 23.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 23.6 Low-Power Modes The following subsections describe the low-power modes. 23.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the WAIT instruction. MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) 23.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. Freescale Semiconductor, Inc... 23.7 I/O Signals The ADC module has 15 channels that are shared with I/O ports B and D and one channel with an input-only port bit on port D. Refer to 24.7 ADC Characteristics for voltages referenced in this section. 23.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH) The ADC analog portion uses VDDAREF as its power pin. Connect the VDDA/VDDAREF pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results. VREFH is the high reference voltage for all analog-to-digital conversions. Connect the VREFH pin to a voltage potential between 1.5 volts and VDDAREF/VDDA depending on the desired upper conversion boundary. NOTE: Route VDDAREF carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 23.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. VREFL is the lower reference supply for the ADC. 23.7.3 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 15 ADC channels to the ADC module. Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) I/O Registers 23.8 I/O Registers Freescale Semiconductor, Inc... These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADICLK) 23.8.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register. Address: $0038 Bit 7 Read: COCO Write: R Reset: 0 R 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 1 1 1 1 1 = Reserved Figure 23-2. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read. If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC interrupt request. Reset clears this bit. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit Freescale Semiconductor, Inc... When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] — ADC Channel Select Bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 15 ADC channels. The six channels are detailed in Table 23-1. Be careful when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets these bits. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) I/O Registers Freescale Semiconductor, Inc... Table 23-1. Mux Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select 0 0 0 0 0 PTB0/ATD0 0 0 0 0 1 PTB1/ATD1 0 0 0 1 0 PTB2/ATD2 0 0 0 1 1 PTB3/ATD3 0 0 1 0 0 PTB4/ATD4 0 0 1 0 1 PTB5/ATD5 0 0 1 1 0 PTB6/ATD6 0 0 1 1 1 PTB7/ATD7 0 1 0 0 0 PTD0 0 1 0 0 1 PTD1 0 1 0 1 0 PTD2 0 1 0 1 1 PTD3 0 1 1 0 0 PTD4/TBLCK 0 1 1 0 1 PTD5 0 1 1 1 0 PTD6/TACLK Unused (Note 1) Range 01111 ($0F) to 11010 ($1A) Unused (Note 1) 1 1 0 1 1 Reserved 1 1 1 0 0 Unused (Note 1) 1 1 1 0 1 VREFH (Note 2) 1 1 1 1 0 VSSA/VREFL (Note 2) 1 1 1 1 1 ADC power off Notes: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC both in production test and for user applications. MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) 23.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Freescale Semiconductor, Inc... Address: $0039 Bit 7 6 5 4 3 2 1 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: R R R R R R R R Reset: Indeterminate after reset R = Reserved Figure 23-3. ADC Data Register (ADR) 23.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: $003A Bit 7 6 5 4 ADIV2 ADIV1 ADIV0 ADICLK Read: Write: Reset: 0 R 0 0 0 3 2 1 Bit 0 0 0 0 0 R R R R 0 0 0 0 = Reserved Figure 23-4. ADC Input Clock Register (ADICLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 23-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC-15) I/O Registers Freescale Semiconductor, Inc... Table 23-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8 1 X X ADC input clock ÷ 16 X = Don’t care ADICLK — ADC Input Clock Register Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. See 24.7 ADC Characteristics. 1 = Internal bus clock 0 = External clock (CGMXCLK) fXCLK or bus frequency 1 MHz = ADIV[2:0] NOTE: During the conversion process, changing the ADC clock will result in an incorrect conversion. MC68HC908AS60 — Rev. 1.0 Technical Data Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Analog-to-Digital Converter (ADC-15) Technical Data MC68HC908AS60 — Rev. 1.0 Analog-to-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 24. Electrical Specifications Freescale Semiconductor, Inc... 24.1 Contents 24.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 24.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 421 24.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 24.5 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .422 24.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 24.7 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 24.8 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . 425 24.9 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 428 24.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . 428 24.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 429 24.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 429 24.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 24.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 431 24.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . 431 MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications 24.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 24.5 5.0 Volt DC Electrical Characteristics for guaranteed operating conditions. Freescale Semiconductor, Inc... Rating Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIn VSS –0.3 to VDD +0.3 V I ± 25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA RST and IRQ input voltage VIn VDD + 4 V Maximum current per pin excluding VDD and VSS Note: Voltages are referenced to V SS. NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications Functional Operating Range 24.3 Functional Operating Range Rating Symbol Value Unit TA –40 to 125 °C VDD 5.0 ± 10% V Symbol Value Unit Thermal resistance QFP (64 pins) θJA 70 °C/W Thermal resistance PLCC (52 pins) θJA 50 °C/W I/O pin power dissipation PI/O User determined W Power dissipation (Note 1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant (Note 2) K Average junction temperature TJ Operating temperature range Operating voltage range Freescale Semiconductor, Inc... 24.4 Thermal Characteristics Characteristic PD x (TA + 273°C) + (PD2 x θJA) TA = PD x θJA W/°C °C Notes: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With this value of K, P D, and TJ can be determined for any value of TA. MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications 24.5 5.0 Volt DC Electrical Characteristics Freescale Semiconductor, Inc... Characteristic Symbol Min Max Unit Output high voltage (ILoad = –2.0 mA) all ports (ILoad = –5.0 mA) all ports VOH VDD –0.8 VDD –1.5 — — V Output low voltage (ILoad = 1.6 mA) all ports (ILoad = 10.0 mA) all ports VOL — — 0.4 1.5 V Input high voltage All ports, IRQ, RESET, OSC1 VIH 0.7 x VDD VDD V Input low voltage All ports, IRQ, RESET, OSC1 VIL VSS 0.3 x VDD V dc injection current, all ports (Note 3) IINJ — ±0.5 mA — — 35 20 mA mA — — — — 50 100 400 500 µA µA µA µA VDD supply current Run (Note 4) Wait (Note 5) Stop (Note 6) 25°C with LVI disabled –40°C to +125°C with LVI disabled 25°C with LVI enabled –40°C to +125°C with LVI enabled IDD I/O ports Hi-Z leakage current IL — ±1 µA Input current IIn — ±1 µA Capacitance Ports (as input or output) COut CIn — — 12 8 pF Low-voltage reset inhibit VLVII 4.0 4.3 V — Continued — Notes: 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3. Functionality of the MCU is guaranteed during injection of dc. current up to the maximum specified level. The maximum specified level is the total current for each port and is allowed on a single pin or a combination of pins. Some disturbance of the ADC accuracy is possible during any injection event and is dependant on board layout and power supply decoupling. 4. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. C L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 5. Wait IDD measured using external square wave clock source (fOP = 8.0 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled. 6. Stop IDD measured with OSC1 = VSS. Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications Control Timing Characteristic Symbol Min Max Unit Low-voltage reset inhibit/recover hysteresis HLVI 100 300 mV POR rearm voltage (Note 7) VPOR 0 200 mV POR reset voltage (Note 8) VPORRST 0 800 mV R POR 0.02 — V/ms High COP disable voltage (Note 10) VHI VDD + 2 VDD + 4 V High FLASH block protect override (Note 11) VHI VDD + 2 VDD + 4 V Freescale Semiconductor, Inc... POR rise time ramp rate (Note 9) Notes: 7. Maximum is highest voltage that POR is guaranteed. 8. Maximum is highest voltage that POR is possible. 9. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 10. See 14.9 COP Module During Break Interrupts. VHI on RST pin. 11. See Section 4. FLASH-1 Memory and Section 5. FLASH-2 Memory for further information. VHI on IRQ pin. 24.6 Control Timing Characteristic Symbol Min Max Unit Bus operating frequency fBus 32 k 8.4 M Hz RESET pulse width low tRL 1.5 — tcyc IRQ interrupt pulse width low (edge-triggered) tILHI 1.5 — tcyc IRQ interrupt pulse period tILIL Note 4 — tcyc tTH, tTL tTLTL 2 Note 4 — — tcyc 16-bit timer (Note 2) Input capture pulse width (Note 3) Input capture period Notes: 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted. 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. Refer to Table 22-2. Mode, Edge, and Level Selection and supporting note. 4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 2 tcyc. MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications 24.7 ADC Characteristics Characteristic Min Max Unit Resolution 8 8 Bits Absolute accuracy (VREFL = 0 V, VDDA/VDDAREF = VREFH = 5 V ± 10%) –1 +1 LSB Includes quantization VREFL VREFH V VREFL = VSSA Power-up time 16 17 µs Conversion time period Input leakage (Note 3) Ports B and D — ±1 µA Conversion time 16 17 ADC clock cycles Freescale Semiconductor, Inc... Conversion range (Note 1) Monotonicity Comments Includes sampling time Inherent within total error Zero input reading 00 01 Hex VIn = VREFL Full-scale reading FE FF Hex VIn = VREFH Sample time (Note 2) 5 — ADC clock cycles Input capacitance — 8 pF Not tested ADC internal clock 500 k 1.048 M Hz Tested only at 1 MHz Analog input voltage VREFL VREFH V Notes: 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 10% 2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications Serial Peripheral Interface (SPI) Timing 24.8 Serial Peripheral Interface (SPI) Timing Freescale Semiconductor, Inc... Num Symbol Min Max Unit Operating frequency (Note 3) Master Slave fBUS(M) fBus(S) fBUS/128 dc fBUS/2 fBUS MHz 1 Cycle time Master Slave tcyc(M ) tcyc(S) 2 1 128 — tcyc 2 Enable lead time tLead 15 — ns 3 Enable lag time tLag 15 — ns 4 Clock (SCK) high time Master Slave tW(SCKH)M tW(SCKH)S 100 50 — — ns 5 Clock (SCK) low time Master Slave tW(SCKL)M tW(SCKL)S 100 50 — — ns 6 Data setup time (inputs) Master Slave tSU(M) tSU(S) 45 5 — — ns 7 Data hold time (inputs) Master Slave tH(M) tH(S) 0 15 — — ns tA(CP0) tA(CP1) 0 0 40 20 ns tDIS — 25 ns 8 Characteristic Access time, slave (Note 4) CPHA = 0 CPHA = 1 9 Slave disable time (hold time to high-impedance state) 10 Enable edge lead time to data valid (Note 6) Master Slave tEV(M) tEV(S) — — 10 40 ns 11 Data hold time (outputs, after enable edge) Master Slave tHO(M) tHO(S) 0 5 — — ns 12 Data valid Master (before capture edge) tV(M) 90 — ns 13 Data hold time (outputs) Master (before capture edge) tHO(M) 100 — ns Notes: 1. 2. 3. 4. 5. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins. Item numbers refer to dimensions in Figure 24-1 and Figure 24-2. fBus = the currently active bus frequency for the microcontroller. Time to data active from high-impedance state With 100 pF on all SPI pins MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications SS INPUT SS pin of master held high 1 SCK, CPOL = 0 OUTPUT NOTE SCK, CPOL = 1 OUTPUT NOTE 5 4 5 4 6 Freescale Semiconductor, Inc... MISO INPUT MSB IN BITS 6–1 10 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT 13 12 Note: This first clock edge is generated internally, but is not seen at the SCK pin. a) SPI Master Timing, CPHA = 0 SS INPUT SS pin of master held high 1 SCK, CPOL = 0 OUTPUT SCK, CPOL = 1 OUTPUT 5 NOTE 4 5 NOTE 4 6 MISO INPUT MSB IN 10 MOSI OUTPUT BITS 6–1 11 MASTER MSB OUT 12 7 LSB IN 10 BITS 6–1 11 MASTER LSB OUT 13 Note: This last clock edge is generated internally, but is not seen at the SCK pin. b) SPI Master Timing, CPHA = 1 Figure 24-1. SPI Master Timing Diagram Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications Serial Peripheral Interface (SPI) Timing SS INPUT 3 1 SCK, CPOL = 0 INPUT 11 5 4 2 SCK, CPOL = 1 INPUT 5 4 9 8 Freescale Semiconductor, Inc... MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined, but normally MSB of character just received a) SPI Slave Timing, CPHA = 0 SS INPUT 1 SCK, CPOL = 0 INPUT 5 4 2 3 SCK, CPOL = 1 INPUT 8 MISO OUTPUT 5 4 10 NOTE MOSI INPUT 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined, but normally LSB of character previously transmitted b) SPI Slave Timing, CPHA = 1 Figure 24-2. SPI Slave Timing Diagram MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications 24.9 CGM Operating Conditions Freescale Semiconductor, Inc... Characteristic Symbol Min Typ Max Comments Operating voltage VDD 4.5 V — 5.5 V Crystal reference frequency fRCLK 1 4.9152 MHz 16 Module crystal reference frequency fXCLK — 4.9152 MHz — Same frequency as fRCLK Range nominal multiplier (MHz) fNOM — 4.9152 — 4.5–5.5 V, VDD only VCO center-of-range frequency (MHz) fVRS 4.9152 — (1) 4.5–5.5 V, VDD only VCO operating frequency (MHz) fVCLK 4.9152 — 32.0 1. fVRS is a nominal value described and mandated as an example in the CGM module section for the desired VCO operating frequency, fVCLK. 24.10 CGM Component Information Description Symbol Min Typ Max Crystal load capacitance CL — — — Consult crystal manufacturer’s data Crystal fixed capacitance C1 — 2 x CL — Consult crystal manufacturer’s data Crystal tuning capacitance C2 — 2 x CL — Consult crystal manufacturer’s data CFACT — 0.0154 — F/s V CF — CFACT x (VDDA/ fXCLK) — See 10.5.3 External Filter Capacitor Pin (CGMXFC). — CBYP must provide low AC impedance from f = fXCLK/100 to 100 x fVCLK, so series resistance must be considered. Filter capacitor multiply factor Filter capacitor Bypass capacitor CBYP — 0.1 µF Technical Data Comments MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications CGM Acquisition/Lock Time Information 24.11 CGM Acquisition/Lock Time Information Description Symbol Min Typ Max Notes Manual mode time to stable tACQ — (8 x VDDA)/(fXCLK x KACQ) — If CF chosen correctly tAL — (4 x VDDA)/(fXCLK x KTRK) — If CF chosen correctly Manual acquisition time tLock — tACQ + tAL — Tracking mode entry frequency tolerance DTRK 0 — ± 3.6% Acquisition mode entry frequency tolerance DUNT ± 6.3% — ± 7.2% Lock entry frequency tolerance DLock 0 — ± 0.9% Lock exit frequency tolerance DUNL ± 0.9% — ± 1.8% Reference cycles per acquisition mode measurement nACQ — 32 — Reference cycles per tracking mode measurement nTRK — 128 — Automatic mode time to stable tACQ nACQ/fXCLK (8 x VDDA)/(fXCLK x KACQ) — If CF chosen correctly Automatic stable to lock time tAL nTRK/fXCLK (4 x VDDA)/(fXCLK x KTRK) — If CF chosen correctly tLock — tACQ + tAL — — ± (fCRYS) x (.025%) x (N/4) Freescale Semiconductor, Inc... Manual stable to lock time Automatic lock time PLL jitter, deviation of average bus frequency over 2 ms — 0 N = VCO frequency multiplier (GBNT) Notes: 1. GBNT guaranteed but not tested 2. V DD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = –40°C to TA(MAX), unless otherwise noted. 24.12 Timer Module Characteristics Characteristic Input capture pulse width Input clock pulse width Symbol Min Max Unit tTIH, tTIL 125 — ns tTCH, tTCL (1/fOP) + 5 — ns MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications 24.13 Memory Characteristics Characteristic Symbol Min Max Unit VRDR 0.7 — V EEPROM programming time per byte tEEPGM 10 — ms EEPROM erasing time per byte tEEBYTE 10 — ms EEPROM erasing time per block tEEBLOCK 10 — ms EEPROM erasing time per bulk tEEBULK 10 — ms EEPROM programming voltage discharge period tEEFPV 100 — µs EEPROM write/erase cycles — 10,000 — Cycles EEPROM data retention after 10,000 write/erase cycles — 10 — Years FLASH pages per row — 8 8 Pages FLASH bytes per page — 8 8 Bytes FLASH read bus clock frequency fRead (Note 1) 32 K 8.4 M Hz FLASH charge pump clock frequency (4.5 FLASH Charge Pump Frequency Control) fPump (Note 2) 1.8 2.5 MHz FLASH block/bulk erase time tErase 100 110 ms FLASH high voltage kill time tKill 200 — µs tHVD 50 — µs flsPulses (Note 3) — 100 Pulses FLASH page program step size tStep (Note 4) 1.0 1.2 ms FLASH cumulative program operations per row between erase cycles tRow (Note 5) — 8 Page program cycles FLASH HVEN low to MARGIN high time tHVTV 50 — µs FLASH MARGIN high to PGM low time tVTP 150 — µs FLASH row erase endurance — 100 — Cycles FLASH row program endurance — 100 — Cycles FLASH data retention time after 100 program/erase cycles — 10 — Years Freescale Semiconductor, Inc... RAM data retention voltage FLASH return to read time FLASH page program pulses Notes: 1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. fPump is defined as the charge pump clock frequency required for program, erase, and margin read operations. 3. flsPulses is defined as the maximum number of tStep pulses required by a page of FLASH memory using the smart programming algorithm. 4. tStep is defined as the amount of time during one page program pulse that HVEN is held high. 5. tRow is defined as the maximum numer of pages programmed on a row before the row using the smart programming algorithm. Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Specifications BDLC Transmitter VPW Symbol Timings 24.14 BDLC Transmitter VPW Symbol Timings Freescale Semiconductor, Inc... Characteristic Number Symbol Min Typ Max Unit Passive logic 0 10 tTVP1 62 64 66 µs Passive logic 1 11 tTVP2 126 128 130 µs Active logic 0 12 tTVA1 126 128 130 µs Active logic 1 13 tTVA2 62 64 66 µs Start of frame (SOF) 14 tTVA3 198 200 202 µs End of data (EOD) 15 tTVP3 198 200 202 µs End of frame (EOF) 16 tTV4 278 280 282 µs Inter-frame separator (IFS) 17 tTV6 298 300 302 µs Notes: 1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V 2. The receiver symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations. 24.15 BDLC Receiver VPW Symbol Timings Characteristic Number Symbol Min Typ Max Unit Passive logic 0 10 tTRVP1 34 64 96 µs Passive logic 1 11 tTRVP2 96 128 163 µs Active logic 0 12 tTRVA1 96 128 163 µs Active logic 1 13 tTRVA2 34 64 96 µs Start of frame (SOF) 14 tTRVA3 163 200 239 µs End of data (EOD) 15 tTRVP3 163 200 239 µs End of frame (EOF) 16 tTRV4 239 280 320 µs Break 18 tTRV6 240 — — µs Notes: 1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V 2. The receiver symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations. MC68HC908AS60 — Rev. 1.0 Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Electrical Specifications 13 11 1 1 14 10 12 SOF 0 0 15 0 EOD 16 EOF 18 BRK Figure 24-3. BDLC Variable Pulse-Width Modulation (VPW) Symbol Timing Technical Data MC68HC908AS60 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 25. Mechanical Specifications Freescale Semiconductor, Inc... 25.1 Contents 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 25.3 52-Pin Plastic Leaded Chip Carrier Package . . . . . . . . . . . . . 434 25.4 64-Pin Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 25.2 Introduction The MC68HC908AS60 is available in two types of packages: • 56-pin plastic leaded chip carrier (PLCC) • 64-pin quad flat pack (QFP). This section shows the latest package specifications available at the time of this publication. To make sure that you have the latest information, contact one of the following: • Local Motorola Sales Office • World Wide Web at http://www.motorola.com/semiconductors/ Follow the World Wide Web on-line instructions to retrieve the current mechanical specifications. MC68HC908AS60 — Rev. 1.0 Technical Data Mechanical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Mechanical Specifications 25.3 52-Pin Plastic Leaded Chip Carrier Package 0.007 (0.18) B Y BRK –N– T L–M M 0.007 (0.18) U M S N S T L–M S N S D Z –M– Freescale Semiconductor, Inc... –L– W D 52 1 V A 0.007 (0.18) M T L–M S N S R 0.007 (0.18) M T L–M S N S E C 0.004 (0.100) –T– SEATING J VIEW S G PLANE G1 S T L–M S H N S 0.007 (0.18) M T L–M S N S K1 K F VIEW S S T L–M S N S VIEW D–D Z 0.010 (0.25) G1 0.010 (0.25) X 0.007 (0.18) M T L–M S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 Technical Data INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.710 0.730 0.040 ––– MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 18.04 18.54 1.02 ––– MC68HC908AS60 — Rev. 1.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Mechanical Specifications 64-Pin Quad Flat Pack 25.4 64-Pin Quad Flat Pack L 48 33 49 DETAIL A S D S H A-B D V P B M B B 0.20 (0.008) Freescale Semiconductor, Inc... L 0.20 (0.008) M C A-B 0.05 (0.002) A-B -B- -A- S S 32 -A-, -B-, DDETAIL A 17 64 1 F 16 -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B 0.20 (0.008) M S H A-B S S D S D S J N BASE METAL M E DETAIL C D 0.20 (0.008) C -H- -CH SEATING PLANE M G U T R DATUM PLANE -HQ K W X DETAIL C DATUM PLANE M C A-B S D S SECTION B-B 0.01 (0.004) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A-B AND ĆDĆ TO BE DETERMINED AT DATUM PLANE ĆHĆ. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE ĆCĆ. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE ĆHĆ. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MC68HC908AS60 — Rev. 1.0 DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.45 2.15 0.45 0.30 2.40 2.00 0.40 0.30 0.80 BSC 0.25 Ċ 0.23 0.13 0.95 0.65 12.00 REF 10° 5° 0.17 0.13 0.40 BSC 7° 0° 0.30 0.13 16.95 17.45 Ċ 0.13 Ċ 0° 16.95 17.45 0.45 0.35 1.6 REF INCHES MIN MAX 0.547 0.555 0.547 0.555 0.085 0.096 0.012 0.018 0.079 0.094 0.012 0.016 0.031 BSC Ċ 0.010 0.005 0.009 0.026 0.037 0.472 REF 5° 10° 0.005 0.007 0.016 BSC 0° 7° 0.005 0.012 0.667 0.687 0.005 Ċ 0° Ċ 0.667 0.687 0.014 0.018 0.063 REF Technical Data Mechanical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Mechanical Specifications Technical Data MC68HC908AS60 — Rev. 1.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 26. Ordering Information Freescale Semiconductor, Inc... 26.1 Contents 26.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 26.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 26.2 Introduction This section contains instructions for ordering the MC68HC908AS60 (see Table 26-1). Packages available are: • 52-pin plastic leaded chip carrier (PLCC) • 64-pin quad flat pack (QFP) 26.3 MC Order Numbers Table 26-1. MC Order Numbers MC Order Number(1) Operating Temperature Range MC68HC908AS60CFN – 40°C to + 85°C MC68HC908AS60VFN – 40°C to + 105°C MC68HC908AS60MFN – 40°C to + 125°C MC68HC908AS60CFU – 40°C to + 85°C MC68HC908AS60VFU – 40°C to + 105°C MC68HC908AS60MFU – 40°C to + 125°C 1. FN = Plastic leaded chip carrier (PLCC) FU = 4 x 14 mm quad flat pack (QFP) MC68HC908AS60 — Rev. 1.0 Technical Data Ordering Information For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Ordering Information Technical Data MC68HC908AS60 — Rev. 1.0 Ordering Information For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Index Freescale Semiconductor, Inc... A accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ACK1 bit (IRQ1 interrupt request acknowledge bit). 216, 219, 220, 221 ACQ bit (acquisition mode bit). . . . . . . . . . . . . 161, 162, 171, 172, 177 arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 A-to-D converter pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AUTO bit (automatic bandwidth control bit). . . . . . . 162, 169, 171, 174 B BCFE bit (break clear flag enable bit) . . . . . . . . . . . 154, 220, 295, 391 SCI status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 BCS bit (base clock select bit). . . . . . . . . 162, 165, 170, 172, 174, 175 BDLC receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 transmit pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 BIH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 BIL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 BKF bit (SCI break flag bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 block protection EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 break interrupt causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 effects on COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188, 208 effects on CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122, 187 effects on SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 effects on TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187, 295, 391 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index BRK module break address registers (BRKH/L) . . . . . . . 186, 187, 188, 189, 190 break status and control register (BSCR) . . . . . . . . . . . . . 186, 189 BRKA bit (break active bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 186, 189 BRKE bit (break enable bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 bus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114, 163, 168 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 C Freescale Semiconductor, Inc... C bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CAN receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 transmit pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CCR C bit (carry/borrow flag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 H bit (half-carry flag). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I bit (interrupt mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 N bit (negative flag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 V bit (overflow flag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Z bit (zero flag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 CGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 PLL bandwidth control register (PBWC) . . 161, 169, 171, 174, 177 PLL control register (PCTL) . . . . . . . . . . . . . . . . 165, 169, 174, 175 PLL programming register (PPG). . . . . . . . . . . . . . . . 164, 169, 173 CGMINT signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168, 175 CGMOUT signal 156, 157, 161, 165, 168, 170, 172, 174, 175, 199, 288 CGMRCLK signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160 CGMRDV signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 CGMVCLK signal . . . . . . . . . . 156, 157, 161, 165, 168, 170, 171, 174 CGMVDV signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 CGMXCLK signal 138, 156, 157, 165, 168, 170, 175, 204, 205, 206, 208 duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CGMXFC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 CHxF bits (TIM channel interrupt flag bits) . . . . . . . . . . . . . . . 390, 399 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Index CHxIE bits (TIM channel interrupt enable bits) . . . . . . . . . . . . 390, 399 CHxMAX bits (TIM maximum duty cycle bits) . . . . . . . . . . . . . 389, 402 CLI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 clock generator module see CGM clock generator module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 PLL programming register (PPG). . . . . . . . . . . . . . . . . . . . . . . . 199 CON1 bit in EENVR1 or EEACR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CON1 bit in EENVR2 or EEACR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 111 CON2 bit in EENVR1 or EEACR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CON2 bit in EENVR2 or EEACR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 111 condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 119, 217 configuration register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . 206, 208 configuration register (CONFIG-1) . . . . . . . . . . . . . . . . . . . . . . . . . 182 CONx bits in EENVR1 or EEACR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CONx bits in EENVR2 or EEACR2 . . . . . . . . . . . . . . . . . . . . . . . . . 111 COP bit (COP reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 COP control register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . 206, 207 COP counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203, 204, 206, 207 COP module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 during break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 COP timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204, 208 COPD bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 COPL bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 CPHA bit (SPI clock phase bit) . . . . . . . . . . . . . . . . . . . . . . . . 281, 284 CPOL bit (SPI clock polarity bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 CPU interrupt software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122, 186, 194 CPU interrupts external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161, 162, 168, 169, 174 SCI receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275, 278, 286 TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 TIM output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 TIM overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294, 390 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 crystal . . . . . . . . . . . . . . . . . . . . . . . 156, 157, 168, 178, 199, 204, 205 CSIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 E Freescale Semiconductor, Inc... EEBCLK bit in EECR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 EEBCLK bit in EECR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 EEBP3–EEBP0 bit in EENVR2 or EEACR2 . . . . . . . . . . . . . . . . . . 111 EEBP3–EEBP0 bits in EENVR1 or EEACR1 . . . . . . . . . . . . . . . . . . 99 EELAT bit in EECR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 EELAT bit in EECR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 EEOFF bit in EECR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 EEOFF bit in EECR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 EEPGM bit in EECR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 EEPGM bit in EECR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EEPROM array control register (EEACR2) . . . . . . . . . . . . . . . . . . . 110 EEPROM control register (EECR1). . . . . . . . . . . . . . . . . . . . . . . . . . 96 EEPROM control register (EECR2). . . . . . . . . . . . . . . . . . . . . . . . . 108 EEPROM nonvolatile register (EENVR1) . . . . . . . . . . . . . . . . . . . . . 98 EEPROM nonvolatile register (EENVR2) . . . . . . . . . . . . . . . . . . . . 110 EERA bit in EENVR1 or EEACR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 EERA bit in EENVR2 or EEACR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EERAS1 and EERAS0 bits in EECR1. . . . . . . . . . . . . . . . . . . . . . . . 97 EERAS1 and EERAS0 bits in EECR2. . . . . . . . . . . . . . . . . . . . . . . 109 ELAT bit (EPROM/OTPROM latch control bit) . . . . . . . . . . . 66, 79, 80 electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 ELSxA/B bits (TIM edge/level select bits) . . . . . . . . . . . . . . . . 388, 400 ENSCI bit (enable SCI bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 EPGM bit (EPROM/OTPROM program control bit). . . . . . . . . . . 66, 80 EPROM control register (EPMCR) . . . . . . . . . . . . . . . . . . . . . . . 65, 79 EPROM/OTPROM programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 79 EPROM/OTPROM security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 79 erase EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index external filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167, 178 external interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Freescale Semiconductor, Inc... F fbus (bus frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 FE bit (SCI receiver framing error bit) . . . . . . . . . . . . . . . . . . . . . . . 253 FEIE bit (SCI receiver framing error interrupt enable bit) . . . . . . . . 249 fnom (nominal center-of-range frequency) . . . . . . . . . . . . . . . . . . . . 160 frclk (PLL reference clock frequency) . . . . . . . . . . . . . . . . . . . . . . . . 160 frdv (PLL final reference frequency) . . . . . . . . . . . . . . . . . . . . . 160, 177 fvclk (VCO output frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 fvrs (VCO programmed center-of-range frequency) . . . . . 160, 164, 174 H H bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 host computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191, 192, 194 I I bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I bit (interrupt mask). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217, 221 I/O port pin termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 I/O registers locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 IDLE bit (SCI receiver idle bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 ILAD bit (illegal address reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ILIE bit (SCI idle line interrupt enable bit) . . . . . . . . . . . . . . . . . . . . 246 ILOP bit (illegal opcode reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ILTY bit (SCI idle line type bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 IMASK1 bit (IRQ1 interrupt mask bit) . . . . . . . . . . . . . . . . . . . 217, 221 index register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 input capture . . . . . . . . . . 315, 318, 376, 380, 381, 390, 392, 397, 402 internal address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 interrupt status and control register (ISCR) . . . . . . . . . . . . . . . . . . . 216 IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . . . 220 IRQ1 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 IRQ1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index IRQ1/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 215, 219 triggering sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 IRST signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138, 139 L Freescale Semiconductor, Inc... L (VCO linear range multiplier) . . . . . . . . . . . . . . . . . . . . . . . . 164, 165 LOCK bit (lock indicator bit). . . . . . . . . . . . . . . 161, 169, 171, 174, 177 LOOPS bit (SCI loop mode select bit) . . . . . . . . . . . . . . . . . . . . . . . 243 LVI module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LVITRIPF and LVITRIPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 LVI status register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211, 212 LVI trip voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LVIOUT bit (LVI output bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211, 212 LVIPWR bit (LVI power enable bit) . . . . . . . . . . . . . . . . . . . . . . . . . 213 LVIPWR bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LVIRST bit ( LVI reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LVIRST bit (LVI reset enable bit). . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LVIRST bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LVISTOP bit in CONFIG-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 M M bit (SCI character length bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 M68HC08 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 mask option register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 210, 211 MODE1 bit (IRQ1 edge/level select bit). . . . . . . . . . . . . . 217, 219, 221 MODF bit (mode fault error bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 MODF bit (SPI mode fault bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 monitor commands IREAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 READSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 monitor mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186, 187, 199, 207 alternate vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192, 195, 199 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 echoing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MSxA/B bits (TIM mode select bits) . . . . . . . . . . . . 383, 384, 387, 388, 389, 399, 400, 402 MSxB bits (TIM mode select bits) . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Freescale Semiconductor, Inc... N N (VCO frequency multiplier). . . . . . . . . . . . . . . . . . . . . . 163, 164, 165 N bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 NEIE bit (SCI receiver noise error interrupt enable bit) . . . . . . . . . . 249 NF bit (SCI noise flag bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 noise . . . . . . . . . . . . . . . . . 39, 160, 161, 166, 168, 176, 178, 386, 389 O OR bit (SCI receiver overrun bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 ORIE bit (SCI receiver overrun interrupt enable bit) . . . . . . . . . . . . 249 OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 167, 168 OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 167, 168 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 150, 157, 166, 167, 168, 205 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 output compare . . . . . . . . . . . . . . . . 315, 318, 376, 380, 382, 383, 384, 385, 389, 390, 392, 397, 402 OVRF bit (overflow bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 OVRF bit (SPI overflow bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 P page zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PE bit (SCI receiver parity error bit). . . . . . . . . . . . . . . . . . . . . . . . . 253 PEIE bit (SCI receiver parity error interrupt enable bit) . . . . . . . . . . 249 PEN bit (SCI parity enable bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 phase-locked loop (PLL) . . . . . . . . . . . . . 156, 157, 159, 163, 166, 168, 174, 175, 176, 177, 178, 199 acquisition mode . . . . . . . . . . . . 159, 161, 171, 172, 176, 177, 179 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176, 177, 179 automatic bandwidth mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 lock detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159, 161, 168 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176, 177 loop filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159, 161, 167 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index Freescale Semiconductor, Inc... manual bandwidth mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159, 177 tracking mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 159, 161, 171, 177 voltage-controlled oscillator (VCO) . . . . . . 157, 159, 161, 165, 171, 173, 174, 178 PIN bit (external reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139, 153 pins assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ATD7-ATD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ATD8–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BDRxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BDTxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 42 CGMXFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 OSC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PTA7-PTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PTB7-PTB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PTC5-PTC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PTD7-PTD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PTE7-PTC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PTF5-PTF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SPSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TACH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TACH0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TACH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VDDS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PLLF bit (PLL flag bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 PLLF bit (PLL interrupt flag bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PLLIE bit (PLL interrupt enable bit) . . . . . . . . . . . . . . . . . . . . . 162, 169 PLLON bit (PLL on bit) . . . . . . . . . . . . . . . . . . . . . . 162, 170, 173, 175 port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 304–305 data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . 304 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Index port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 306–308 data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . 307 port B data register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 308–310 data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . 309 port C data register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 311–313 data direction register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . 312 port D data register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 314–317 data direction register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . 316 port E data register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 port F . . . . . . . . . . . . . . . . . . . . . . . . . 42, 318–320, 320–322, 323–325 data direction register F (DDRF) . . . . . . . . . . . . . . . . . . . . . . . . . 319 port F data register (PTF). . . . . . . . . . . . . . . . . . . . . . 318, 320, 323 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 program EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 187, 219 PS[2:0] bits (TIM prescaler select bits) . . . . . . . . . . . . . . 297, 380, 394 PSHH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PTY bit (SCI parity bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 PULH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 pulse-width modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 pulse-width modulation (PWM) . . . . . . . . . 385, 386, 387, 388, 392, 397 duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385, 389, 402 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294, 385 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 R R8 bit (SCI received bit 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61–62, 192 size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RE bit (SCI receiver enable bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 redundant mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 106 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index Freescale Semiconductor, Inc... reset COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203, 207 external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 external reset pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 illegal opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139, 206 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140, 206 reset status register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 RPF bit (SCI reception in progress flag bit) . . . . . . . . . . . . . . . . . . . 254 RST pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 RTI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 122, 186 RWU bit (SCI receiver wakeup bit) . . . . . . . . . . . . . . . . . . . . . . . . . 247 S SBK bit (SCI send break bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 SBSW bit (SIM break stop/wait bit) . . . . . . . . . . . . . . . . . . . . . . . . . 151 SCI baud rate misalignment tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SCI baud rate register (SCBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SCI character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SCI control register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SCI control register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SCI control register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SCI data register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 SCI framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236, 253 SCI status register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 SCI status register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 SCP1–SCP0 bits (SCI baud rate prescaler bits) . . . . . . . . . . . . . . . 255 SCR2–SCR0 bits (SCI baud rate select bits) . . . . . . . . . . . . . . . . . 256 SCRF bit (SCI receiver full bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 SCRIE bit (SCI receiver interrupt enable bit). . . . . . . . . . . . . . . . . . 246 SCTE bit (SCI transmitter empty bit) . . . . . . . . . . . . . . . . . . . . . . . . 250 SCTIE bit (SCI transmitter interrupt enable bit) . . . . . . . . . . . . . . . . 246 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Index serial peripheral interface module (SPI) . . . . . . . . . . . . . . . . . . . . . 288 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285, 288 control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 279, 283, 286 data register (SPDR) . . . . . . . . . . . . . . . . . 264, 265, 269, 286, 288 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 287 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 286 slave select pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 285 status and control register (SPSCR) . . . . . . . . . 264, 269, 275, 285 SIM bus frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SIMOSCEN signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 168 SPE bit (SPI enable bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SPMSTR bit (SPI master mode bit). . . . . . . . . . . . . 263, 265, 280, 283 SPR[0:1] bits (SPI baud rate select bits) . . . . . . . . . . . . . . . . . . . . . 264 SPR1[1:0] bits (SPI baud rate select bits) . . . . . . . . . . . . . . . . . . . . 288 SPRF bit (SPI receiver full bit). . . . . 264, 265, 275, 276, 283, 285, 286 SPRIE bit (SPI receiver interrupt enable bit) . . . . . . . . . . 275, 283, 286 SPTE bit (SPI transmitter empty bit) . . . . . . . . 264, 275, 276, 285, 287 SPTE bit (SPI transmitter enable bit). . . . . . . . . . . . . . . . . . . . . . . . 287 SPTIE bit (SPI transmitter interrupt enable bit) . . . . . . . . 275, 285, 287 SPWOM bit (SPI wired-OR mode bit) . . . . . . . . . . . . . . . . . . . 279, 284 SSREC bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61, 117 start bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SCI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 stop bit SCI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 STOP bit (STOP enable bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 STOP bit in CONFIG-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 STOP instruction . . . . . . . . . . . 170, 175, 188, 205, 207, 278, 294, 390 stop mode . . . . . . . . . . . . . . . . . . . . . . . . 188, 208, 213, 278, 294, 390 stop mode recovery time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SWI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122, 186, 187, 194 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index system integration module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . 134 reset status register (SRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SIM counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138, 142 T Freescale Semiconductor, Inc... T8 bit (SCI transmitted bit 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 TC bit (SCI transmission complete bit) . . . . . . . . . . . . . . . . . . . . . . 250 TCIE bit (SCI transmission complete interrupt enable bit). . . . . . . . .246 TE bit (SCI transmitter enable bit) . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TIM counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292, 295, 380, 391 timer interface module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 channel registers (TCH0H/L–TCH3H/L) . . 299, 382, 383, 384, 385, 386, 387, 391, 392, 401, 402 channel registers (TCHxH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 channel status and control registers (TSC0–TSC3). . 383, 387, 397 clock input pin (PTE3/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 380, 392 counter modulo registers (TMODH/L) . . . . . . . . 294, 299, 390, 396 counter modulo registers (TMODH:TMODL) . . . . . . . . . . . . . . . 388 counter registers (TCNTH/L) . . . . . . . . . . . . . . . . . . . 298, 395, 399 counter registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . . . 298, 395 DMA select register (TDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 modulo registers (TMODH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 modulo registers (TMODH:TMODL) . . . . . . . . . . . . . . . . . 292, 380 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 status and control register (TSC) 294, 296, 380, 388, 390, 393, 400 TOF bit (TIM overflow bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294, 390 TOF bit (TIM overflow flag bit) . . . . . . . . . . . . . . . . . 296, 299, 393, 396 TOIE bit (TIM overflow interrupt enable bit). . . . . . . 294, 296, 390, 393 TOVx (TIM toggle on overflow bits) . . . . . . . . . . . . . . . . . . . . . . . . . 389 TOVx bits (TIM overflow bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 TOVx bits (TIM toggle on overflow bits) . . . . . . . . . . . . . . . . . 389, 401 TRST bit (TIM reset bit) . . . . . . . . . . . . . . 297, 298, 388, 394, 395, 400 TSTOP bit (TIM stop bit) . . . . . . . . . . . . . . . . . . . . . . 297, 388, 394, 400 TXINV bit (SCI transmit inversion bit) . . . . . . . . . . . . . . . . . . . . . . . 243 Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Index U user vectors addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Freescale Semiconductor, Inc... V bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168, 178, 179 voltage-controlled oscillator (VCO) . . . . . . . . . . . . . . . . . 163, 168, 170 VRS[7:4] bits (VCO range select bits) . . . . . . . . . . . . . . . . . . . . . . . 174 W WAIT instruction . . . . . . . . . . . . . . . . . . . 188, 207, 213, 278, 294, 390 wait mode . . . . . . . . . . . . . . . . 188, 207, 213, 278, 294, 297, 390, 394 WAKE bit (SCI wakeup condition bit) . . . . . . . . . . . . . . . . . . . . . . . 244 X XLD bit (crystal loss detect bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Z Z bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MC68HC908AS60 — Rev. 1.0 Technical Data Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Index Technical Data MC68HC908AS60 — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC908AS60/D REV 1 MC68HC08AS60 Technical Data Home Page: RoHS-compliant and/or Pb- free versions of Freescale products have the functionality www.freescale.com and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free email: counterparts. For further information, see http://www.freescale.com or contact your [email protected] Freescale sales representative. USA/Europe or Locations Not Listed: Freescale Semiconductor For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Technical Information Center, CH370 1300 N. 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