FREESCALE MCZ33298EG

Freescale Semiconductor
Technical Data
Document Number: MC33298
Rev. 6.0, 4/2008
Eight Output Switch with Serial
Peripheral Interface I/O
33298
The 33298 is a smart eight output low side power switch. It is a
versatile device incorporating an 8-bit serial-in shift register to control
an 8-bit parallel output latch providing control of eight independent
"ON/OFF" output switches. Applications include the control of
solenoids, relays, lamps, small DC motors, and other moderate current
loads (1.0 – 3.0A).
The 33298 interfaces directly with a microcontroller to control
various inductive or incandescent loads. Input control is fast. Data
rates are guaranteed to 2.0 MHz but the device is capable of rates to
8.5 MHz @ 25°C.
Each output uses high efficiency MOSFET power transistors
configured with open drains. Each low "ON" resistance output (0.4Ω
RDS(ON) @ 25°C) is capable of sinking up to 3.0A of transient current.
On a continuous basis, each output can simultaneously (with all
outputs "ON") handle 0.5A of current when the device is soldered onto
a typical PC board. Higher output currents are dependent on the
number of outputs simultaneously "ON". The circuit's innovative
monitoring and protection features include very low standby current.
Features
LOW SIDE SWITCH
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42344B
24 SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
-40°C to 125°C
24 SOIC
MC33298DW/R2
• Designed to operate over wide supply voltages of 5.5 to 26.5V
MCZ33298EG/R2
• Interfaces to microprocessor using 8-bit SPI I/O protocol up to
3.0MHz
• 1.0A peak current outputs with maximum RDS(ON) of 1.8Ω at TJ - 150°C
• Outputs current limited to accommodate in-rush currents associated with switching incandescent loads
• Output voltages clamped to 65V during inductive switching
• Maximum sleep current (IPWR) of 25µA
• Maximum of 4.0mA IDD during operation
• Pb-free packaging designated by suffix code EG
VDD
V PWR
33298
MCU
VPWR
OP 0
SFPD
OP 1
VDD
OP 2
CS
OP 3
SCLK
OP 4
SI
OP 5
SO
OP 6
OP 7
RESET
GND
Figure 1. 33298 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
21
OUTPUT 0
+
VDD
16
OVD
VDD
RB
SFPD
SFL
CS
SCLK
SI
SO
CSI
CSBI
SFPD
15
RST
10µA
25µA
22
CS
+
10µA
10
Fault Timers
SCLK
SI
Bias
53V
GE
OT
SF
OF
Gate
Control
OUTPUT
1 to 7
To Gates
1 to 7
23
Open
Load
Detect
SPI
Interface
Logic
lLimit
+
–
Short-circuit
Detect
10µA
Serial D/O
Line Driver
RS
GND 5-8
17-20
Over-temperature
Detect
4
SO
2
11 - 14
10µA +
3
24
Voltage
Regulator
Over -voltage
9
From Detectors 1 to 7
Figure 2. 33298 Simplified Block Diagram
Table 1. Fault Operation
SERIAL OUTPUT (SO) PIN REPORTS
Over-voltage
Over-temperature
Over-current
Output ON, Open Load Fault
Over-voltage condition reported
Fault reported by Serial Output (SO) pin
SO pin reports short to battery/supply or over-current condition
Not reported
Output OFF, Open Load Fault SO pin reports output OFF open load condition
DEVICE SHUTDOWNS
Over-voltage
Over-temperature
Over-current
Total device shutdown at VPWR = 28 to 36V. All outputs are latched off while the SPI register is reset (cleared).
Outputs can be turned back on with a new SPI command after VPWR has decayed below the over-voltage
shutdown voltage including hysteresis.
Only the output experiencing an over-temperature condition turns off.
Only the output experiencing an over-current condition shuts down at 3.0A to 6.0A after a 25ms to 100ms delay,
with SFPD pin grounded. All outputs will continue to operate in a current limit mode, with no shutdown, if the
SFPD pin is at 5.0V.
33298
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OP7
1
24
OP0
OP8
2
23
OP1
SCLK
3
22
RST
SI
4
21
VPWR
GND
5
20
GND
GND
6
19
GND
GND
7
18
GND
GND
8
17
GND
SO
9
16
VDD
CS
10
15
SFPD
OP5
11
14
OP2
OP4
12
13
OP3
Figure 3. 33298 Pin Connections
Table 2. 33298 Pin Function Description
Pin Number
Pin Name
Formal Name
Definition
1
OP7
Output 7
This pin provides connection to drain of output MOSFET number seven.
2
OP6
Output 6
This pin provides connection to drain of output MOSFET number six.
3
SCLK
System Clock
4
SI
Serial Input
This pin is for the input of serial instruction data. SI information is read on the falling edge of
SCLK.
5
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
6
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
7
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
8
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
9
SO
Serial Output
10
CS
Chip Select
11
OP5
Output 5
This pin provides connection to drain of output MOSFET number five.
12
OP4
Output 4
This pin provides connection to drain of output MOSFET number four.
13
OP3
Output 3
This pin provides connection to drain of output MOSFET number three.
14
OP2
Output 2
This pin provides connection to drain of output MOSFET number two.
15
SFPD
Short Fault
Protect Disable
16
VDD
Logic Supply
17
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
18
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
19
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
20
GND
Ground
This pin provides connection to IC Power Ground and functions as part of heat sinking path.
21
VPWR
Power
Output MOSFET gate drive supply.
22
RST
RESET
This pin is active low. It is used to clear the SPI Shift register, thereby setting all output
switches OFF.
This pin clocks the internal Shift registers of the 33298.
This pin is the tri-stateable output from the Shift register.
Whenever this pin is in a logic low state, data can be transferred from the MCU to the 33298
through the SI pin and from the 33298 to the MCU through the SO pin.
This pin is used to prevent the outputs from latching-OFF because of an over current
condition.
Logic Supply.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 2. 33298 Pin Function Description (continued)
Pin Number
Pin Name
Formal Name
Definition
23
OP1
Output 1
This pin provides connection to drain of output MOSFET number one.
24
OP0
Output 0
This pin provides connection to drain of output MOSFET number zero.
33298
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Value
Power Supply Voltage
Unit
V
Normal Operation (Steady-state)
VPWR(SS)
- 1.5 to 26.5
Transient Conditions(1)
VPWR(PK)
- 13 to 60
Logic Supply Voltage(2)
VDD
- 0.3 to 7.0
V
Input pin Voltage(3)
VIN
- 0.3 to 7.0
V
Output Clamp Voltage(4)
VOUT(OFF)
2.0mA ≤ IOUT ≤ 0.5A
Output Self-Limit Current
V
50 to 75
IOUT(LIM)
3.0 to 6.0
A
IOUT(CONT)
1.0
A
Human Body Model(7)
VESD1
2000
Machine Model(7)
VESD2
200
Output Clamp Energy(8)
ECLAMP
Continuous Per Output Current(5)
ESD
Voltage(6)
V
Repetitive:
TJ = 25°C
100
mJ
TJ = 124°C
30
mJ
TJ = 25°C
2.0
J
TJ = 124°C
0.5
J
Non-Repetitive:
Recommended Frequency of SPI Operation(9)
fSPI
2.0
MHz
Storage Temperature
TSTG
- 55 to 150
°C
Peak Package Reflow Temperature During Reflow(10),(11)
TPPRT
Note 11.
°C
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Transient capability with external 100Ω resistor in series with VP pin and supply.
Exceeding these limits may cause a malfunction or permanent damage to the device.
Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device.
With output OFF.
Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature
will require maximum output current computation using package RθJA.
ESD data available upon request.
ESD1 testing is performed in accordance with the Human Body Model (CZap = 200pF, RZap = 1500Ω), ESD2 testing is performed in
accordance with the Machine Model (CZap = 200pF, RZap = 0Ω).
Maximum output clamp energy capability at 150°C junction temperature using a single non-repetitive pulse method.
Guaranteed and production tested for 2.0MHz SPI operation, but demonstrated to operate to 8.5MHz at 25°C.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 4. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Operating Case Temperature
Operating Junction Temperature
(12)
Power Dissipation (TA = 25°C)
(13)
Thermal Resistance (Junction-to-Ambient)
Symbol
Value
Unit
TC
- 40 to 125
°C
TJ
- 40 to 150
°C
PD
3.0
W
°C/W
RθJA
Case 738 Package
All Outputs ON(15)
31
Single Output ON(15)
37
Case 751E Package
All Outputs ON(14)
34
Single Output ON(15)
40
Notes
12. See Figure 22 for Thermal model.
13. Soldering temperature limit is for 10 seconds maximum duration; not designed for immersion soldering; exceeding these limits may
cause malfunction or permanent damage to the device. Contact Freescale Semiconductor Sales Office for device immersion soldering
time/temperature limits.
14. Thermal resistance from Junction-to-Ambient with all outputs ON and dissipating equal power.
15. Thermal resistance from Junction -to-Ambient with a single output ON.
33298
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 4.5V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 16V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate value with VBAT = 13V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
VPWR(QF)
5.5
—
9.0
VPWR(FO)
9.0
—
26.5
Supply Current (All Outputs ON, IOUT = 0.5A)
VPWR(ON)
—
1.0
2.0
V
Sleep State Supply Current (VDD = 0.5V)
IPWR(SS)
—
1.0
50
µA
Sleep State Output Leakage Current (per Output, VDD = 0.5V)
IOUT(SS)
—
—
50
µA
VOV
28
—
36
V
VOV(HYS)
0.2
—
1.5
V
VDD
4.5
—
5.5
V
IDD
—
—
4.0
mA
VDD(UVLO)
2.0
—
4.5
V
POWER INPUT
Supply Voltage Range
V
Quasi-Functional(16)
Fully Operational
(17)
Over-voltage Shutdown
Over-voltage Shutdown Hysteresis
Logic Supply Voltage
Logic Supply Current (with any combination of Outputs ON)
Logic Supply Under-voltage Lockout Threshold
(18)
POWER OUTPUT
Drain-to-Source ON Resistance (IOUT = 0.5A, TJ = 25°C)
Ω
RDS(ON)
VPWR = 5.5V
—
—
VPWR = 9.0V
—
0.4
0.5
VPWR = 13V
—
0.35
0.45
Drain-to-Source ON Resistance (IOUT = 0.5A, TJ = 150°C)
Ω
RDS(ON)
VPWR = 5.5V
—
VPWR = 9.0V
VPWR = 13V
Output Self-limiting Current
—
1.8
—
7.5
0.9
—
0.65
0.8
3.0
4.0
6.0
IOUT(LIM)
Outputs Programmed ON, VOUT = 0.6VDD
Output Fault Detect Threshold(19)
A
VDD
VOUTTH(F)
Output Programmed OFF
0.6
Output OFF Open Load Detect Current
(20)
Output Clamp Voltage
0.7
0.8
µA
IOCO
Output Programmed OFF, VOUT = 0.6VDD
30
50
100
V
VOK
2.0mA < IOUT < 200mA
Output Leakage Current (VDD < 2.0V)
1.0
(21)
IOUT(LKG)
50
60
75
-50
0
50
µA
Notes
16. SPI inputs and outputs operational; Fault status reporting may not be fully operational within this voltage range.
17. Value reflects normal operation (no faults) with all outputs ON. Each ON output contributes approximately 20µA to IPWR. Each output
experiencing a soft short condition contributes approximately 0.5mA to IPWR. A soft short is defined as any load current causing the
output source current to self-limit. A hard output short is a very low-impedance short to supply.
18. For VDD less than the Under-voltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled.
19.
20.
21.
Output Fault Detect Threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts.
Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded to be OFF.
Output leakage current measured with the output OFF and at 16V.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 16V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate value with VPWR = 13V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
TLIM
155
170
185
°C
TLIM(HYS)
—
10
20
°C
Input Logic High Voltage(23)
VIH
0.7
—
1.0
VDD
Input Logic Low Voltage(24)
VIL
0
—
0.2
VDD
VI(HYS)
50
100
500
mV
Over-temperature Shutdown (Outputs
OFF)(22)
Over-temperature Shutdown Hysteresis
(22)
DIGITAL INTERFACE
Input Logic Voltage Hysteresis(25)
Input Logic Current(26)
IIN
-10
0
10
µA
RST Pull-up Current (RST = 0.7VDD)
IRST
10
22
50
µA
SFPD Pull-down Current (SFPD = 0.2VDD)
ISFPD
10
22
50
µA
SO High State Output Voltage (IOH = 1.0mA)
VSOH
VDD -1.0V
VDD -0.6V
—
V
SO Low State Output Voltage (IOL = -1.6mA)
VSOL
—
0.2
0.4
V
SO Tri-state Leakage Current (CS = 0.7VDD, 0V < VSO < VDD)
ISOT
-10
0
10
µA
Input Capacitance (0V < VDD < 5.5V)(27)
CIN
—
—
12
pF
CSOT
—
—
20
pF
SO Tri-state Capacitance (0V < VDD < 5.5V)(28)
Notes
22.
23.
24.
25.
26.
27.
28.
This parameter is guaranteed by design, but it is not production tested.
Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs.
Lower logic threshold voltage range applies to SI, CS, SCLK, Reset, and SFPD input signals.
Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design, but it is not production tested.
Input current of SCLK, SI and CS logic control inputs.
Input capacitance of SI, CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not
production tested.
Tri-state capacitance of SO for 0V < VDD < 5.5V. This parameter is guaranteed by design, but it is not production tested.
33298
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
.
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 16V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tR
0.4
1.5
20
µs
POWER OUTPUT TIMING
Output Rise Time (VPWR = 13V, RL = 26Ω)(29)
Output Fall Time (VPWR = 13V, RL = 26Ω)(29)
Output Turn ON Delay Time (VPWR = 13V, RL = 26Ω)(30)
Output Turn-OFF Delay Time (VPWR = 13V, RL =
Output Short Fault Disable Report
26Ω)(31)
Delay(32)
tF
0.4
2.5
20
µs
tDLY(ON)
1.0
5.0
15
µs
tDLY(OFF)
1.0
5.0
15
µs
25
50
100
25
50
100
tDLY(SF)
SFPD = 0.2 x VDD
Output OFF Fault Report Delay(33)
µs
tDLY(OFF)
SFPD = 0.2 x VDD
µs
DIGITAL INTERFACE TIMING
SCLK Clock Period(34)
tPSCLK
500
—
—
ns
SCLK Clock High Time
tWSCLKH
175
—
—
ns
tWSCLKL
175
—
—
ns
tW(RST)
250
50
—
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
250
50
—
ns
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
tLAG
250
50
—
ns
SI to Falling Edge of SCLK (Required for Setup Time)
tSISU
125
25
—
ns
Falling Edge of SCLK to SI (Required for Hold Time)
SCLK Clock Low Time
)(35)
Required Low State Duration for Reset (VIL < 0.2VDD
tSI(HOLD)
125
25
—
ns
SO Rise Time (CL = 200pF)
tRSO
—
25
75
ns
SO Fall Time (CL = 200pF)
tFSO
—
25
75
ns
SI, CS, SCLK, Incoming Signal Rise Time(36)
tRSI
—
—
200
ns
SI, CS, SCLK, Incoming Signal Fall
Time(36)
tFSI
—
—
200
ns
Time from Falling Edge of CS to SO
Low-impedance(37)
tSO(EN)
—
—
200
ns
Time from Rising Edge of CS to SO
High-impedance(38)
tSO(DIS)
—
—
200
ns
—
50
125
Time from Rising Edge of SCLK to SO Data Valid
0.2VDD < SO > 0.8VDD, CL = 200pF
(39)
tVALID
ns
Notes
29. Output Rise and Fall time respectively measured across a 26Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.
30. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
31. Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
32. Output Short Fault Delay time measured from rising edge of CS to IOUT -= 2.0A point with output ON, VOUT = 5.0V, and SFPD = 0.2
VDD. See Figures 8 and 10.
33.
34.
35.
36.
37.
38.
39.
Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9.
Clock period include 75ns rise plus 75ns fall transition in addition to clock high and low time.
RST Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VIH
RST
0.2VDD
VIL
tW(RST)
VIH
CS
0.2VDD
VIL
tW(SCLKH)
tLEAD
tLAG
tR
VIH
0.7VDD
SCLK
0.2VDD
VIL
tW(SCLKL)
tSI(su)
0.7VDD
SI
tF
tSI(HOLD)
VIH
Don't Care
Valid
Don't Care
Valid
Don't Care
VIL
0.2VDD
Figure 4. Input Timing Switch Characteristics
ELECTRICAL PERFORMANCE CURVES
VDD = 5.0V
VDD = 5.0V
VPull-Up = 2.5V
RL = 2.0 kΩ
33298
33298
SCLK
CS
Under
Test
SO
Under
Test
SO
CL = 20pF
CL = 200 pF
CL represents the total capacitance of the test fixture and probe.
CL represents the total capacitance of the test fixture and probe.
Figure 5. Valid Data Delay Time and
Valid Time Test Circuit
Figure 6. Enable and Disable Time Test Circuit
33298
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
tR (SI)
tF (SI)
< 10 ns
< 10ns
5.0V
0.7VDD
SCLK
0.2VDD
tDLY(LH)
(Low-to-High)
SO
(High-to-Low)
VPWR = 14V
V0L
CS
Under
Test
Output
CL
tF (SO)
V0H
0.7VDD
0.2 VDD
tDLY(HL)
RL = 26Ω
33298
tR (SO)
tVALID
0
V0H
0.7VDD
0.2VDD
SO
VDD = 5.0V
50%
V0L
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of CS causes the SO output to switch from
high to low.
CL represents the total capacitance of the test fixture and probe.
Figure 9. Switching Time Test Circuit
Figure 7. Valid Data Delay Time and
Valid Time Waveforms
VDD = 5.0V
tR(SI)
CS
0.2VDD
90%
10%
(High-to-Low)
5.0 V
0.7 VDD
0
tSO(EN)
SO
tSO(DIS)
33298
CS
VTri-State
90%
Under
Test
IL = 2.0A
(Output ΟΝ)
Output
CL = 20 pF
10%
tSO(EN)
tSO(dis)
tSO(DIS)
V0H
90%
SO
VPWR = 11V
tF(SI)
< 10 ns
< 10 ns
10%
(Low-to-High)
VTri-State
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of detecting a circuit fault with CS in a High Logic state, e.g. open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of detecting a circuit fault with CS in a High Logic state, e.g. shortened load.
CL represents the total capacitance of the test fixture and probe.
Figure 10. Output Fault Unlatch Disable
Delay Test Circuit
Figure 8. Enable and Disable Time Waveforms
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
tR(SI)
tF(SI)
< 10ns
tR(SI)
< 10ns
50%
CS
tDLY(OFF)
0
14V
Output Voltage
50%
50%
Waveform 2
< 10ns
0
VOFF = 11V
50%
tDLY(OFF)
Output Current
Waveform
5.0V
90%
10%
VON = 5.0V
IO(CL)
50%
0
VOL
tDLY(ON)
1. tDLY(ON)
Output Voltage
Waveform
VOL
14V
Output Voltage
50%
CS
10%
Waveform 1
< 10 ns
5.0V
90%
tF(SI)
tDLY(OFF)
and
are turn-on and turn-off propagation delay
times.
2. Turn-off is an output programmed from an ON to an OFF state.
3. Turn-on is an output programmed from and OFF to an ON state.
Figure 11. Turn-On/Off Waveforms
1. tPDLY(OFF) is the output fault unlatch disable propagation delay time required to correctly report an output fault after CS rises. It represents an
output commanded ON while having an existing output short (over-current) to supply.
2. The SFPD pin < 0.2V
Figure 12. Output Fault Unlatch Disable
Delay Waveforms
33298
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33298 was conceived, specified, designed, and
developed for automotive applications. It is an eight output
low side power switch having 8-bit serial control. The 33298
incorporates SMARTMOS™ technology having effective 1.5µ
CMOS logic, bipolar/MOS analog circuitry, and independent
state of the art double diffused MOS (DMOS) power output
transistors. Many benefits are realized as a direct result of
using this mixed technology. A simplified block diagram
delineates 33298 in Figure 1.
Where bipolar devices require considerable control
current for their operation, structured MOS devices, since
they are voltage controlled, require only transient gate
charging current affording a significant decrease in power
consumption. The CMOS capability of the SMARTMOS
process allows significant amounts of logic to be
economically incorporated into the monolithic design.
Additionally, the bipolar/MOS analog circuits embedded
within the updrain power DMOS output transistors monitor
and provide fast, independent protection control functions for
each individual output. All outputs have internal 65V at 0.5A
independent output voltage clamps to provide fast inductive
turn-off and transient protection.
The 33298 uses high efficiency updrain power DMOS
output transistors exhibiting very low room temperature
drain-to-source ON resistance values (RDS(on) ≤ 1.0Ω at 13V
VPWR) and dense CMOS control logic. Operational bias
currents of less than 2.0mA (1.0mA typical) with any
combination of outputs ON are the result of using this mixed
technology and would not be possible with bipolar structures.
To accomplish a comparable functional feature set using a
bipolar structure approach, would result in a device requiring
hundreds of milliamperes of internal bias and control current.
This would represent a very large amount of power to be
consumed by the device itself and not available for load use.
During operation, the 33298 functions as an eight output
serial switch serving as a microcontroller (MCU) bus
expander and buffer, with fault management and fault
reporting features.
In doing so, the device directly relieves the MCU of the
fault management functions.
The 33298 directly relieves the MCU of the fault
management functions. The 33298 directly interfaces to an
MCU, operating at system clock serial frequencies in excess
of 3.0MHz. It uses a Synchronous Peripheral Interface (SPI)
for control and diagnostic readout. Figure 13 illustrates the
basic SPI configuration between an MCU and one 33298.
MC68HCXX
Microcontroller
Shift Register
Receive
Buffer
Parallel
Ports
33298
MOSI
SI
MISO
SO
SCLK
Shift Register
To
Logic
RST
CS
Figure 13. SPI Interface with Microcontroller
The circuit can also be used in a variety of other
applications in the computer, telecommunications, and
industrial fields. It is parametrically specified over an input
battery /supply range of 9.0 to 16V but is designed to operate
over a considerably wider range of 5.5 to 26.5V. The design
incorporates the use of Logic Level MOSFETs as output
devices. These MOSFETs are sufficiently turned ON with a
gate voltage of less than 5.0V thus eliminating the need for
an internal charge pump. Each output is identically sized and
independent in operation. The efficiency of each output
transistor, at room temperature provides as little as 9.0V
supply (VPWR), the maximum RDS(on) of an output
All inputs are compatible with 5.0V CMOS logic levels,
incorporating negative or inverted logic. Whenever an input is
programmed to a logic low state (<1.0V) the corresponding
low side switched output being controlled will be active low
and turned ON. Conversely, whenever an input is
programmed to a logic high state (>3.0V), the output being
controlled will be high and turned OFF.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
INTRODUCTION
SCLK
Parallel Port
MC68XX
Microcontroller
SPI
CS
SCLK
CS
SCLK
CS
SCLK
CS
SCLK
SO
SI
SO
SI
SO
SI
SO
SI
MISO
IRQ
33298
8 Outputs
33298
33298
8 Outputs
8 Outputs
33298
8 Outputs
MOSI
Figure 14. 33298 SPI System Daisy Chain
One main advantage of the 33298 is the serial port. When
supplies the system clock signal (top MCU designated the
coupled to an MCU, it receives ON/OFF commands from the
master); the lower MCU being the slave. It is possible to have
MCU and in return transmits the drain status of the device’s
a system with more than one master; however, not at the
output switches. Many devices can be daisy-chained
same time. Only when the master is not communicating can
together, forming a larger system, illustrated in Figure 14.
a slave assume the mastership and communicate. MCU
master control is switched through the use of the slave select
Note In this example, only one dedicated MCU parallel
(SS) pin of the MCUs. A master will become a slave when it
port (aside from the required SPI) is required for chip select
detects a logic low state on its SS pin.
to control 32 possible loads.
These basic examples make the 33298 very attractive for
Multiple 33298 devices can also be controlled in a parallel
applications where a large number of loads require efficient
input fashion using the SPI, illustrated in Figure 15. This
control. To this end, the popular Synchronous Serial
figure shows a possible 24 loads being controlled by only
Peripheral Interface (SPI) protocol is incorporated to
three dedicated parallel MCU ports used for chip select.
communicate efficiently with the MCU.
SPI SYSTEM ATTRIBUTES
33298
MOSI
SCLK
MC68XX
Microcontroller
SPI
SI
8 Outputs
SCLK
CS
33298
8 Outputs
SI
Parallel
Ports
A
B
C
SCLK
CS
33298
SI
8 Outputs
SCLK
CS
Figure 15. Parallel Input SPI Control
Figure 16 illustrates a basic method of controlling multiple
33298 devices using two MCUs. A system can have only one
master MCU at any given instant of time and one or more
slave MCUs. Master control of the system must pass from
one MCU to the other in an orderly manner. The master MCU
The SPI system is flexible enough to communicate directly
with numerous standard peripherals and MCUs available
from Freescale Semiconductor and other semiconductor
manufacturers. SPI reduces the number of pins necessary
for input/output (I/O) on the 33298. It also offers an easy
means of expanding the I/O function using few MCU pins.
The SPI system of communication consists of the MCU
transmitting, in return it receives one data-bit of information
per system clock cycle.
Data-bits of information are simultaneously transmitted by
one pin, Microcontroller Out Serial In (MOSI), and received
by another pin, Microcontroller In Serial Out (MISO), of
the MCU.
Some features of the SPI are:
• Full duplex, three-wire synchronous data transfer
• Each microcontroller can be a master or a slave
• Provides write collision flag protection
• Provides end of message interrupt flag
• Four I/Os associated with SPI (MOSI, MISO, SCLK, SS)
Drawbacks to SPI are:
• An MCU is required for efficient operational control
• In contrast to parallel input control it Is slower at
performing pulse width modulating (PWM) functions.
33298
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL PIN DESCRIPTION
MC68XX
Microcontroller
SPI
(Master)
A0
B0
A1
B1 Parallel
Ports
A2
33298
CS
SCLK
8 Outputs
8-Bit
SO
8-Bit
SCLK
MISO
SI
MOSI
VDD
33298
SS
CS
SCLK
MC68XX
Microcontroller
SPI
(Alternate Master)
B0 Parallel A0
B1 Ports A1
A2
SCLK
8-Bit
VDD
8 Outputs
8-Bit
SO
SI
33298
CS
SCLK
8 Outputs
8-Bit
MISO
SO
MOSI
SI
SS
Figure 16. Multiple MCU SPI Control
CHIP SELECT (CS)
The 33298 receives its MCU communication through the
CS pin. Whenever this pin is in a logic low state, data can be
transferred from the MCU to the 33298 by way of the SI pin
and from the 33298 to the MCU through the SO pin. Clockedin data from the MCU is transferred from the 33298 Shift
register and latched into the power outputs on the rising edge
of the CS signal. On the falling edge of the CS signal, drain
status information is transferred from the power outputs then
loaded into the Shift register of the device. The CS pin also
controls the output driver of the serial output (SO) pin.
Whenever the CS pin goes to a logic low state, the SO pin
output driver is enabled allowing information to be transferred
from the 33298 to the MCU. To avoid data corruption or the
generation of spurious data, it is essential the high-to-low
transition of the CS signal occur only when SCLK is in a logic
low state.
SYSTEM CLOCK (SCLK)
The system clock (SCLK) pin clocks the internal shift
registers of the 33298. The serial input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal while the serial output (SO) pin shifts data information
out of the SO line driver on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided to
guarantee validity of data. It is essential the SCLK pin be in a
logic low state whenever the chip select bar (CS) pin makes
any transition. For this reason, it is recommended, though not
absolutely necessary, the SCLK pin be kept in a low logic
state as long as the device is not accessed (CS in logic high
state). When CS is in a logic high state, signals at the SCLK
and SI pins are ignored and SO is tri-stated (highimpedance). See the Data Transfer Timing diagram in
Figure 18.
SERIAL INPUT (SI)
This pin is for the input of serial instruction (SI) data. SI is
read on the falling edge of SCLK. A logic high state present
on this pin when the SCLK signal rises will program a specific
output OFF. In turn, the pin turns OFF the specific output on
the rising edge of the CS signal. Conversely, a logic low state
present on the SI pin will program the output ON, In turn, the
pin turns ON the specific output on the rising edge of the CS
signal.
To program the eight outputs of the 33298 ON or OFF, an
8-bit serial stream of data is required to be synchronously
entered into the SI pin starting with Output 7, followed by
Output 6, Output 5, and so on, to Output 0. Referring to
Figure 18, the DO bit is the most significant bit (MSB)
corresponding to Output 7. For each rise of the SCLK signal,
with CS held in a logic low state, a data-bit instruction (ON or
OFF) is synchronously loaded into the Shift register per the
data-bit SI state. The Shift register is full after eight bits of
information have been entered. To preserve data integrity,
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
INTRODUCTION
care should be taken to not transition SI as SCLK transitions
from a low-to-high logic state.
VDD
SERIAL OUTPUT (SO)
The serial output (SO) pin is the tri-stateable output from
the Shift register. The SO pin remains in a high-impedance
state until the CS pin goes to a logic low state. The SO data
reports the drain status, either high or low relative to the
previous command word. The SO pin changes state on the
rising edge of SCLK and reads out on the falling edge of
SCLK. When an output is OFF and not faulted, the
corresponding SO data-bit is a high state. When an output is
ON, and there is no fault, the corresponding data-bit on the
SO pin will be a low logic state. The SI/SO shifting of data
follows a first-in-first-out (FIFO) protocol with both input and
output words transferring the MSB first. Referring to
Figure 18, the DO bit is the MSB corresponding to Output 7
relative to the previous command word. The SO pin is not
affected by the status of the Reset pin.
RESET (RST)
The 33298 reset (RST) pin is active low. It is used to clear
the SPI Shift register. In doing so, all output switches are set
at OFF. The device situated in the same system with an
MCU, the MCU retains the Reset pin of the device in a logic
low state. Retention ensures all outputs to be OFF until both
the VDD and VPWR pin voltages are adequate for
predictable operation. Retention of the device RST pin takes
place only upon initial system power up. After the 33298 is
reset, the MCU is ready to assert system control with all
output switches initially OFF.
If the VPWR pin of the 33298 experiences a low voltage,
following normal operation, the MCU should pull the RST pin
low to shutdown the outputs and clear the input data register.
The RST pin is active low and has an internal pull-down
incorporated, insuring operational predictability should the
external pull-down of the MCU open circuit. The internal pulldown is only 25µA, affording safe and easy interfacing to the
MCU. The Reset pin of the 33298 should be pulled to a logic
low state for a duration of at least 250ns, ensuring reliable a
reset.
A simple power ON reset delay of the system can be
programmed through the use of an RC network comprised of
a shunt capacitor from the RST pin to Ground and a resistor
to VDD, illustrated in Figure 17. Care should be exercised
ensuring proper discharge of the capacitor. Careful attention
eliminates adverse delay of the Reset and damage of the
MCU if it pulls the Reset line low, thereby accomplishing
initialization for turn ON delay. It may be easier to incorporate
delay into the software program and use a parallel port pin of
the MCU to control the 33298 RST pin.
+
RDLY
20µA
Reset
MCU
Reset
CDLY
33298
Figure 17. Power ON Reset
SHORT FAULT PROTECT DISABLE (SFPD)
The Short Fault Protect Disable (SFPD) pin is used to
prevent the outputs from latching-off due to an over-current
condition. This feature provides control of incandescent lamp
loads where in-rush currents exceed the device’s analog
current limits. Essentially the SFPD pin determines whether
the 33298 output(s) will instantly shutdown upon sensing an
output short or remain ON in a current limiting mode of
operation until the output short is removed or thermal
shutdown is reached. If the SFPD pin is tied to VDD = 5.0V
the 33298 output(s) will remain ON in a current limited mode
of operation upon encountering a load short to supply or overcurrent condition. When the SFPD pin is grounded, a shortcircuit will immediately shut down only the output affected.
Other outputs not having a fault condition will operate
normally. The short-circuit operation is addressed in more
detail later.
POWER CONSUMPTION
The 33298 has extremely low power consumption in both
the operating and standby modes. In the standby, or Sleep
mode, with VDD ≤ 2.0V, the current consumed by the VPWR
pin is less than 25µA. In the operating mode, the current
drawn by the VDD pin is less than 4.0mA (1.0mA typical)
while the current drawn at the VPWR pin is 2.0mA maximum
(1.0mA typical). During normal operation, turning outputs ON
increases IPWR by only 20µA per output. Each output
experiencing a soft short (over-current conditions just under
the current limit), adds 0.5mA to the IPWR current.
PARALLELING OF OUTPUTS
Using MOSFETs as output switches permits connecting
any combination of outputs together. RDS(ON) of MOSFETs
have an inherent positive temperature coefficient providing
balanced current sharing between outputs without
destructive operation (bipolar outputs could not be paralleled
in this fashion as thermal run-away would likely occur). The
device can even be operated with all outputs tied together.
This mode of operation may be desirable in the event the
application requires lower power dissipation, or the added
capability of switching higher currents.
Performance of parallel operation results in a
corresponding decrease in RDS(ON) while the Output OFF
Open Load Detect Currents and the Output Current Limits
increase correspondingly (by a factor of eight if all outputs are
paralleled). Less than 125mΩ RDS(ON) at 25°C with current
limiting of eight to 24A will result if all outputs are paralleled
33298
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
together. There will be no change in the over-voltage detect
or the OFF output threshold voltage range. The advantage of
paralleling outputs within the same 33298 affords the
existence of minimal RDS(ON) and output clamp voltage
variation between outputs.
Typically, the variation of RDS(ON) between outputs of the
same device is less than 0.5 percent. The variation in clamp
voltages, potentially affecting dynamic current sharing, is less
than five percent. Paralleling outputs from two or more
different devices is possible, but it is not recommended.
There is no guarantee the RDS(ON) and clamp voltage of the
two devices will match. System level thermal design analysis
and verification should be conducted whenever paralleling
outputs; particularly where different devices are involved.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
18
OD*
D0
OD*
D1
OD*
D2
OD*
D4
Old Data
Old Data
OD*
D3
OD*
D5
OD*
D6
OD*
D7
D0*
D8
D1*
D9
D3*
D11
New Data DO0
New Data DO7
D2*
D10
D4*
D12
D5*
D13
D6*
D14
D7*
D15
SO pin is enabled. Output Status information transferred to Output Shift Register.
Data from the Shift Register is transferred to the Output Power Switches.
Will change state on the rising edge of the SCLK pin signal.
Will accept data on the falling edge of the SCLK pin signal.
CS High-to-Low
CS Low-to-High
SO
SI
Data Transfer Timing (General)
NOTES: 1.Reset pin is in a logic high-state during the above operation.
2.D0, D1, D2,..., and D15 relate to the ordered entry of program data into the MC33298 with D0/D8 bits (MSB) corresponding to Output 7 and D7/D15 corresponding to Output 0.
3.D0*, D1*, D2*,..., and D7* relate to the ordered data out of the 33298 with D0* bit (MSB) corresponding to Output 7.
4.OD* corresponds to Old Databits.
5.For brevity, only DO7 and DO0 are shown which respectively correspond to Output 7 and Output 0.
Output 0
Output 7
SO
SI
SCLK
CS
FUNCTIONAL DESCRIPTION
INTRODUCTION
Figure 18. Data Transfer Timing
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
FAULT LOGIC OPERATION
INTRODUCTION
The MCU can perform a parity check of the fault logic
operation by comparing the command 8-bit word to the status
8-bit word. Assume after system reset, the MCU first sends
an 8-bit command word to the 33298. This word is called
Command Word 1. Each output to be turned ON will have its
corresponding data bit low. Refer to the data transfer timing
illustration in Figure 18.
As Command Word 1 is being written into the Shift register
of the 33298, a status word is being simultaneously written
and received by the MCU. However, the word being received
by the MCU is the status of the previous write word to the
33298, Status Word 0. If the command word of the MCU is
written a second time (Command Word 2 = Command Word
1), the word received by the MCU, Status Word 2, is the
status of Command Word 1. The timing diagram illustrated in
Figure 18 depicts this operation. Status Word 2 is then
compared with Command Word 1. The MCU will Exclusive
OR Status Word 2 with Command Word 1 to determine if the
two words are identical. If the two words are identical, faults
do not exist. The timing between the two write words must be
greater than 100µs to receive proper drain status. The
system data bus integrity may be tested by writing two like
words to the 33298 within a few microseconds of each other.
INITIAL SYSTEM SETUP TIMING
The MCU can monitor two kinds of faults:
1. Communication errors on the data bus
2. Actual faults of the output loads
After initial system start up or reset, the MCU will write one
word to the 33298. If the word is repeated within
approximately five microseconds of the first word, the word
received by the MCU, at the end of the repeated word, serves
as a confirmation of data bus integrity (1). At start up, the
33298 will take 25 to 100µs before a repeat of the first word
should be repeated at least 100µs later to verify the status of
the outputs.
The SO of the 33298 will indicate any one of four faults.
The four possible faults are:
1. Over-temperature
2. Output OFF Open Fault
3. Short Fault (over-current)
4. VPWR Over-voltage Fault.
All of these faults, with the exception of the Over-voltage
Fault, are output specific. Over-temperature Detect, Output
OFF Open Detect, and Output Short Detect are dedicated to
each output separately such that the outputs are independent
in operation. A VPWR Over-voltage Detect is a global nature
causing all outputs to be turned OFF.
OVER-TEMPERATURE FAULT
Patent pending Over-temperature Detect and shutdown
circuits are specifically incorporated for each individual
output. The shutdown following an Over-temperature
condition is independent of the system clock and other logic
signal. Each independent output shuts down at 155°C to
185°C. When an output shuts down due to an Overtemperature Fault, no other outputs are affected. The MCU
recognizes the fault since the output was commanded to be
ON and the status word indicates it is OFF. A maximum
hysteresis of 20°C ensures an adequate time delay between
output turn OFF and recovery. This avoids a very rapid turn
ON and turn OFF of the device around the Over-temperature
threshold. When the temperature falls below the recovery
level for the Over-temperature Fault, the device will turn on
only if the Command Word during the next write cycle
indicates the output should be turned ON.
OVER-VOLTAGE FAULT
An Over-voltage condition on the VPWR pin causes the
33298 to shut-down all outputs until the over-voltage
condition is removed and the device is re-programmed by the
SPI. The over-voltage threshold on the VPWR pin is specified
as 28V to 36V with 1.0V typical hysteresis. Following the over
voltage condition, the next write cycle sends the SO pin the
hexadecimal word $FF (all ones) indicating all outputs are
turned off. In this way, potentially dangerous timing problems
are avoided and the MCU reset routine ensures an orderly
startup of the loads. The 33298 does not detect an overvoltage on the VDD pin. Other external circuitry, such as a
universal voltage monitor, is necessary to accomplish this
function.
OUTPUT OFF OPEN LOAD FAULT
An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input in a logic high state). To understand the
operation of the Open Load Fault detect circuit; see
Figure 19. The Output OFF Open Load Fault is detected by
comparing the drain voltage of the specific MOSFET output
to an internally generated reference. Each output has one
dedicated comparator for this purpose.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
operation once the condition causing the Open Load Fault is
removed.
33298
VPWR
Low = Fault
RL
MOSFET OFF
+
–
Output
50µA
VTHRES
2.5 to 3.5V
Figure 19. Output OFF Open Load Fault
An Output OFF Open Load Fault is indicates when the
output voltage is less than the Output Threshold Voltage
(VTHRES) of 0.6 to 0.8 x VDD. Since the 33298 outputs function
as switches, during normal operation, each MOSFET output
should either be completely turned ON or OFF. By design,
the threshold voltage was selected to be between the ON and
OFF voltage of the MOSFET. During normal operation, the
ON state VDS voltage of the MOSFET is less than the
threshold voltage and the OFF state VDS voltage is greater
than the threshold voltage. This design approach provides
using the same threshold comparator for Output Open Load
Detect in the OFF state and Short-circuit Detect in the ON
state. See Figure 20 for an understanding of the Short-circuit
Detect circuit. With VDD = 5.0V, an OFF state output voltage
of less than 3.0V will be detected as an Output OFF Open
Load Fault while voltages greater than 4.0V will not be
detected as a fault.
The 33298 has an internal pull-down current source of
50µA, illustrated in Figure 19 between the MOSFET drain
and ground. This current source prevents the output from
floating up to VPWR if there is an open load or internal wire
bond failure. The internal comparator compares the drain
voltage with a reference voltage, VTHRES (0.6 to 0.8 x VDD). If
the output voltage is less than this reference voltage, the
33298 will declare the condition to be an open load fault.
During steady-state operation, the minimum load
resistance (RL) required to prevent false fault reporting during
normal operation can be located using the following equation.
Therefore, the load resistance necessary to prevent false
open load fault reporting is (using Ohm’s Law) equal to 92kΩ
or less.
During output switching, especially with capacitive loads,
a false output OFF Open Load Fault may be triggered. To
prevent this false fault from being reported an internal fault
filter in the range of 25 to 100µs is incorporated. The duration
in which a false fault may be reported is a function of the load
impedance (RL,CL,LL), RDS(ON), and COUT of the MOSFET as
well as the supply voltage (VPWR). The rising edge of CS
triggers a built-in fault delay timer which must time-out (25 or
100µs) before the fault comparator is enabled to detect at
faulted threshold. The circuit automatically returns to normal
SHORTED LOAD FAULT
A short load, or over-current fault can be caused by any
output being shorted directly to supply, or an output
experiencing a current greater than the current limit.
There are three safety circuits progressively in operation
during load short conditions providing system protection.
They are:
1. The output current of the device is monitored in an
analog fashion using a SENSEFET™ approach and
current limited.
2. The output current of the device is sensed by
monitoring the MOSFET drain voltage.
3. The output thermal limit of the device is sensed, and
when attained, causes only the specific faulted output
to be latched OFF, allowing all remaining outputs to
operate normally.
Each of the three protection mechanisms are incorporated
in their output providing robust independent output operation.
The analog current limit circuit is always active, monitoring
the output drain current. An over-current condition causes the
gate control circuitry to reduce the gate-to-source voltage
imposed on the output MOSFET, re-establishing the load
current in compliance with current limit (3.0 to 6.0A) range.
Time required for the current limit circuitry to act is less than
20µs. Therefore, currents higher than 3.0 to 6.0A will never
be seen for more than 20µs (a typical duration is 10µs). If the
current of an output attempts to exceed the predetermined
limit of 3.0 to 6.0A (4.0A nominal), the VDS voltage will
exceed the VTHRES voltage and the over-current comparator
will be tripped, illustrated in Figure 20.
33298
VPWR
High = Fault
MOSFET ON
Digital
+
–
RL
Output
–
Analog +
VREF
VTHRES
2.5 to 3.5V
Figure 20. Short Circuit Detect and
Analog Current Limiting Circuit
The status of SFPD determines whether the 33298 will
shut down immediately, or continue to operate in an analog
current limited mode until either the short-circuit (over-
33298
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
current) condition is removed or thermal shutdown is
reached.
Grounding the SFPD pin enables the short fault protection
shutdown circuitry. Consider a load short (output short to
supply) occurring on an output before, during, and after
output turn ON. When the CS signal rises to the high logic
state, the corresponding output is turned ON, activating a
delay timer. The duration of the delay timer is 70 to 250µs. If
the short circuit takes place before the output is turned ON,
the delay experienced is the entire 70 µs to 250µs followed
by shutdown. If the short occurs during the delay time, the
shutdown still occurs after the delay time has elapsed.
However, if the short circuit occurs after the delay time,
shutdown is immediate (within 20µs after sensing). The
purpose of the delay timer is to prevent false faults from being
reported when switching capacitive loads.
If the SFPD pin is at 5.0V, or VDD, an output will not be
disabled when an over-current is detected. The specific
output will, within 5.0 to 10µs of encountering the shortcircuit, go into an analog current limited mode. This feature is
especially useful when switching incandescent lamp loads,
where high in-rush currents experienced during startup last
for 10 to 20 milliseconds.
Each output of the 33298 has its own over-current
shutdown circuitry. Over-temperature, and the over-voltage
faults are not affected by the SFPD pin’s state.
Both load current sensing and output voltage sensing are
incorporated for short fault detection with actual detection
occurring slightly after the onset of current limit. The current
limit circuitry incorporates a SENSEFET™ approach to
measure the total drain current. This calls for the current
through a small number of cells in the power MOSFET to be
measured and the result multiplied by a constant, giving the
total current. Wherein output shutdown circuitry measures
the drain-to-source voltage, shutting down the output if its
threshold (VThres) is exceeded.
Short fault detection is accomplished by sensing the
output voltage and comparing it to VThres. The lowest VThres
requires a voltage of 0.6 times 4.5V (the minimum VDD
voltage) or 2.7V to be sensed. For an enabled output, with
VDD = 5.0 ± 0.5V, an output voltage in excess of 4.4V will be
detected as a “short”, while voltages less than 2.7V will not be
detected as “shorts”.
OVER-CURRENT RECOVERY
If the SFPD pin is in a high logic state, the circuit returns to
normal operation automatically after the short-circuit is
removed (unless thermal shutdown has occurred).
If the SFPD pin is grounded and over-current shutdown
occurs, removing the short circuit will result in the output
remaining OFF until the next write cycle. If the short circuit is
not removed, the output will turn ON for the delay time (70 to
250µs) and then turn OFF for every write cycle commanding
a turn ON.
SFPD PIN VOLTAGE SELECTION
Since the voltage condition of the SFPD pin controls the
activation of the short fault protection (i.e., shutdown) mode
equally for all eight outputs, the load having the longest
duration of in-rush current determines what voltage (state)
the SFPD pin should be. Usually if at least one load is, an
incandescent lamp for example, the in-rush current on that
input will be milliseconds in duration. Therefore, setting SFPD
at 5.0V will prevent shutdown of the output due to the in-rush
current. The system relies only on the over-temperature
shutdown to protect the outputs and the loads. The 33298
was designed to switch GE194 incandescent lamps, or
equivalents, with the SFPD pin in a grounded state.
Considerably larger lamps can be switched with the SFPD
pin held in a high logic state.
Sometimes both a delay period greater than 70 to 250µs
(current limiting of the output) followed by an immediate overcurrent shutdown is necessary. This can be accomplished by
programming the SFPD pin to 5.0V for the extended delay
period, allowing the outputs to remain ON in a current limited
mode, then grounding it to accomplish the immediate
shutdown after a period of time. Additional external circuitry
is required to implement this type of function. An MCU
parallel output port can be devoted to controlling the SFPD
voltage during and after the delay period, is often a much
better method. In either case, care should be taken to
execute the SFPD start-up routine every time start-up or
reset occurs.
UNDER-VOLTAGE SHUTDOWN
An under-voltage VDD condition will result in the global
shutdown of all outputs. The under-voltage threshold is
between 2.5V and 3.5V. When VDD goes below the
threshold, all outputs are turned OFF, thereby resetting the
Serial Output Data register to indicate the same.
An under-voltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5V and
9.0V, the outputs will operate per the command word.
However, the status as reported by the SO pin may not be
accurate below 9.0V VPWR. Proper operation at VPWR
voltages below 5.5V are not be guaranteed.
DECIPHERING FAULT TYPE
The 33298 SO pin can be used to determine what kind of
system fault has occurred. With eight outputs having open
load, over-current, over-temperature, and over-voltage faults;
a total of 25 different faults are possible. The SO status word
received by the MCU will be compared with the word sent to
the 33298 during the previous write cycle. For a specific
output, if the SO bit compares with the corresponding SI bit
of the previous word; the output is operating normal with no
fault. Only when the SO bit and previous word SI bit differ is
there a fault indicated. If the two words are not the same, the
MCU should be programmed to determine which output or
outputs are faulted.
If, for a specific output, the initial SI command bit were
logic high, the output would be programmed to be OFF; if,
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
upon the next command word being entered, a logic low
came back on SO, for that specific output’s corresponding bit,
an Output-OFF Open-Load fault would be indicated. The
resulting SO bit, for that specific output, would be different
from that entered during the previous word for that SI bit,
indicating the fault. The eight output-off open-load faults are
therefore most easily detected.
If for a specific output, the initial SI command bit were a
logic low, calling for the output to be programmed on; upon
the next word command being entered, the corresponding bit
came back with a logic high on SO, an output over-current
fault would be indicated. An over-current fault is always
reported by the SO output and is independent of the logic
state existing on the SFPD pin. When the SFPD pin is in a
logic high state, an over-current condition will be reported on
the SO pin. However, limiting output current is in effect and
the output is permitted to operate if the over-current condition
does not drive output into an over-temperature fault. An overtemperature fault will shutdown the specific output effected
for the duration of the over-temperature condition.
Over-current and over-temperature faults are often
related. Turning the effected output switches OFF and
waiting for some time to allow the output to cool down should
make these types of faults go away. Soft over-current faults
can sometimes be determined over hard short faults and over
temperature faults by observing the time required for the
device to recover. However, in general over-current and overtemperature faults can not be differentiated in normal
application usage.
An advantage of the synchronous serial output is multiple
faults can be detected with only one (SO) pin being used for
fault status reporting.
If VPWR experiences an over-voltage condition, all outputs
will immediately be turned OFF and remain latched off. A new
command word is required to turn the outputs back on
following an over-voltage condition.
OUTPUT VOLTAGE CLAMPING
Each output of the 33298 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of the
output. Each clamp independently limits the drain to source
voltage to 65V at drain currents of 0.5A and keeps the output
transistors from avalanching by causing the transient energy
to be dissipated in the linear mode. See Figure 21. The total
energy clamped (EJ) can be calculated by multiplying the
current area under the current curve (IA) times the clamp
voltage (VCL) times the duration the clamp is active (t).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.5A, indicate the maximum energy
to be 50mJ at 150°C junction temperature per output.
Drain-to-Source Clamp
Voltage (VCL = 65V)
Drain Voltage
Drain Current
(ID = 0.5A)
Clamp Energy
(EJ = IA x VCL x t)
VPWR
Drain-to-Source ON
Voltage(VDS(ON))
Current
Area (IA)
GND
Time
Figure 21. Output Voltage Clamping
THERMAL CHARACTERIZATION
THERMAL MODEL
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors
of power generation. The thermal model illustrated in
Figure 22 was developed for the 33298 mounted on a typical
PC board. The model is accurate for both steady state and
transient thermal conditions. The components RD0 through
RD7 represent the steady state thermal resistance of the
silicon die for transistor outputs 0 through 7, while CD0
through CD7 represent the corresponding thermal
capacitance of the silicone die translator outputs and plastic.
The device area and die thickness determine the values of
these specific components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by
the terms RPKG and CPKG. The steady state thermal
resistance of leads and the PC board make up the steady
state package thermal resistance, RPKG. The thermal
capacitance of the package is made up of the combined
capacitance of the flag and the PC board. The mode
compound was not modeled as a specific component but it is
factored into the other overall component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to.The IPWR current source represents the total power
dissipation and is calculated by totalling the power dissipation
of each individual output transistor. This is easily
accomplished by knowing RDS(ON) and load current of the
individual outputs.
Very satisfactory steady state and transient results are
experienced with this thermal model. Tests indicate the
model accuracy to have less than 10 percent error. Output
interaction with an adjacent output is believed to be the main
contributor to the thermal inaccuracy. Tests indicate little or
no detectable thermal affects caused by distant output
transistors isolated by one or more other outputs. Tests were
conducted with the device mounted on a typical PC board
placed horizontally in a 33 cubic inch still air enclosure. The
PC board was made of FR4 material measuring 2.5 by 2.5
33298
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
inches, having double sided circuit traces of 1.0 ounce
copper soldered to each device pin. The board temperature
was measured with thermal couple soldered to the board
surface one inch away from the center of the device. The
ambient temperature of the enclosure was measured with a
second thermal couple located over the center of one inch
distance from device.
additional PC board metal around the heatsinking pins
improved RPKG from 30° to 28°C/W.
The SOP-24 package has pins 5, 6, 7, 8, 17, 18, 19, and
20 of the package connected directly to the lead frame flag.
Characterization was conducted in the same manner as with
the DIP package. The junction-to-ambient temperature
resistance was found to be 40°C/W with a single output active
(34°C/W with all outputs dissipating equal power0 and the
thermal resistance from junction-to-PC board
(RJUNCTION-BOARD) to be 30°C/W (board temperature,
measure one inch from device center). The junction-toheatsink lead resistance was found again to approximate
10°C/W. Devoting additional PC board metal around the
heatsinking pins for this package improved the Rpkg from 33°
to 31°C/W.
The total power dissipation available is dependent on the
number of outputs enabled at any one time. At 25°C the
RDS(ON) in 450mΩ with a coefficient of 6500 ppm/°C. For the
junction temperature to remain below 150°C, the maximum
available power dissipation must decrease as the ambient
temperature increases. Figure 23 and 24 depict the per
output limit of current at ambient temperatures necessary
when one, four, or eight outputs are enable ON. 25 illustrates
how the RDS(ON) output value is affected by junction
temperature.
THERMAL PERFORMANCE
Figure 22 illustrates the worst case thermal component
parameters values for the 33298 in the 20-pin plastic power
DIP and the SOP-24 wide body surface mount package. Pins
5, 6, 15, and 16 of the power DIP package are connected
directly to the lead frame flag. The parameter values
indicated take into account adjacent output combinations.
The characterization was conducted over power dissipation
levels of 0.7 to 17W. The junction-to-ambient temperature
thermal resistance was found to be 37°C/W with a single
output active (31°C/W with all outputs dissipating equal
power) and in conjunction with this, the thermal resistance
from junction to PC board (RJUNCTION-BOARD) was found to be
27°C/W (board temperature, measure one inch from device
center). Additionally, the thermal resistance from junction-toheatsink lead was found to approximate 10°C/W. Devoting
Junction Temperature Node
VD - TD (C°)
(Volts represent Die Surface Temperature)
Output 0
Rd0
Output 1
Cd0
Output 2
Cd1
Rd1
Rd2
Output 6
Cd2
Rd6
Output 7
Cd6
Rd7
Cd7
Flag Temperature Node
IPWR (Steady State or Transient)
(1.0A = 1.0W of Device Power Dissipation)
RPKG = RLEADS +RPC Board
Package
RDX
(Ω)*
CDX
(F)*
RPKG
(Ω)*
CPKG
(F)*
20 pin Dip
7.0
0.002
30
0.2
SOP-24L
7.0
0.002
33
0.15
CPKG = CFLAG + CPC Board
Ambient Temperature Node
VA = TA (C°)
(1.0V = 1°C Ambient Temperature)
* Ω = °C/W, F = W s/°C, IPWR = W, and VA = °C
Figure 22. Thermal Model (Electrical Equivalent)
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
IL(MAX),Maximum Current Per Output (A)
3.0
1 Output ON (37°C/W)
2.5
RDS(ON)@150°C=0.8Ω
TJ =150°C
2.0
4 Outputs ON (32°C/W)
1.5
1.0
8 Outputs ON (31°C/W)
0.5
0
-50 -25
0
25
50
75
100 125 150
TA, Ambient Temperature (C°)
IL(MAX),Maximum Current Per Output (A)
1.5
1.4
VPWR = 13V
VDD = 5.0 V
IOUT = 0.5A
1.3
1.2
1.1
1.0
0.9
-50 -25
0
25
50
75
100 125 150
Figure 25. Maximum Output ON Resistance vs. Junction
Temperature
1 Output ON (40°C/W)
RDS(ON)@150°C=0.8Ω
2.0
1.5
1.6
TJ Junction Temperature (°C)
Figure 23. Maximum DIP Package Steady State
Output Current vs. Ambient Temperature
2.5
RDS(ON), Output ON Resistance (Ω)
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
TJ =150°C
4 Outputs ON (35°C/W)
1.0
0.5
8 Outputs ON (34°C/W)
0
-50 -25
0
25
50
75
100 125 150
TA Ambient Temperature (C°)
Figure 24. Maximum SOP Package Steady State Output
Current vs. Ambient Temperature
33298
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EG SUFFIX
24-PIN
98ASB42344B
REVISION G
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
EG SUFFIX
24-PIN
98ASB42344B
REVISION G
33298
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
4.0
8/2006
•
•
•
•
•
5.0
11/2006
•
6.0
3/2008
•
•
•
Implemented Revision History page
Converted to Freescale format
Update to the prevailing form and style
Added EG suffix device
Removed MC33298EG/R2 and replaced with MCZ33298EG in the Ordering Information
block
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum ratings on page 5. Added note with instructions to obtain this information
from www.freescale.com.
Updated Freescale form and style.
Corrections from original document.
Upgraded the package drawing to Rev. G
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
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MC33298
Rev. 6.0
4/2008
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