Freescale Semiconductor Advance Information Document Number: MC33879 Rev 7, 8/2008 Configurable Octal Serial Switch with Open Load Detect Current Disable 33879 33879A The 33879 device is an 8-output hardware-configurable, high side / low side switch with 16-bit serial input control. Two of the outputs may be controlled directly via microprocessor for PWM applications. The 33879 incorporates SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33879 controls various inductive, incandescent, or LED loads by directly interfacing with a microcontroller. The circuit’s innovative monitoring and protection features include very low standby currents, cascade fault reporting, internal + 45 V clamp voltage for low-side configuration, - 20 V high side configuration, output specific diagnostics, and independent over-temperature protection. HIGH SIDE/ LOW SIDE SWITCH Features • Designed to operate 5.5V < VPWR < 26.5V • 16-Bit SPI for control and fault reporting, 3.3V / 5.0V compatible • Outputs are current limited (0.6A to 1.2A) to drive incandescent lamps • Output voltage clamp, + 45V (Low Side) and - 20V (High Side) during inductive switching • On/Off control of open load detect current (LED application) • Internal reverse battery protection on VPWR • Loss of ground or supply will not energize loads or damage IC • Maximum 5.0μA IPWR standby current at 13V VPWR • RDS(ON) of 0.75Ω at 25°C typical • Short-circuit detect and current limit with automatic retry • Independent over-temperature protection • Pb-free packaging designated by suffix code EK DWB SUFFIX EXPOSED PAD EK SUFFIX (PB-FREE) 98ARL10543D 32-PIN SOICW ORDERING INFORMATION Device MCU 33879 VDD VPWR A0 MOSI SCLK CS EN DI SCLK CS MISO DO PWM1 IN5 MCZ33879EK/R2 MCZ33879AEK/R2 PWM2 IN6 GND VBAT D1 D2 D3 D4 S1 S2 S3 S4 High-Side Drive M D5 D6 D7 D8 S5 S6 S7 S8 H-Bridge Configuration VBAT VBAT Low-Side Drive Figure 1. 33879 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. Package -40°C to 125°C 32 SOICW-EP MC33879EK/R2 VPWR +5.0 V Temperature Range (TA) DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations (Optional Table) Freescale Part No. VPWR Supply Voltage 33879 -16 to 40V 33879A -16 to 45V Reference Location 6, 7, 13 33879 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VDD __ CS VPWR ~50 μA Internal Bias Power Supply SCLK Charge Pump Over-voltage Shutdown/POR Sleep State DI GND DO EN ~110 kΩ OV, POR, SLEEP SPI and Interface Logic Typical of all 8 output drivers TLIM SPI Bit 0 IN5 Enable ~50 μA SPI Bit 4 IN5 IN6 Open Load Detect Current ~80 μA Gate Drive Control Current Limit + – ~50 μA + – Open/Short Comparator + – ~4.0 V Open/Short Threshold Open Load Detect Current ~80 μA TLIM EP Gate Drive Control Exposed Pad Current Limit + – + – Open/Short Comparator D1 D2 D3 D4 D7 D8 Drain Outputs S1 S2 S3 S4 S7 S8 Source Outputs D5 D6 Drain Outputs S5 Source Outputs S6 + – ~4.0 V Open/Short Threshold Figure 2. 33879 Simplified Internal Block Diagram 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS GND VDD S8 NC D8 S2 D2 NC NC S1 D1 D6 S6 IN6 EN SCLK 9 24 10 23 11 22 12 21 13 20 14 19 DO VPWR NC S7 D7 S4 D4 NC NC S3 D3 D5 S5 IN5 15 18 CS 16 17 DI 1 32 2 31 3 30 4 29 5 28 6 27 7 8 26 GND 25 Figure 3. 33879 Pin Connections Table 2. 33879 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15. Pin Number Pin Name Pin Function Formal Name 1 GND Ground Ground 2 VDD Input Logic Supply Voltage 3 S8 Output Source Output 8 4, 8, 9, 24, 25, 30 NC No Connection Not Connected No internal connection to this pin. 5 D8 Output Drain Output 8 Output 8 MOSFET drain pin. 6 S2 Output Source Output 2 7 D2 Output Drain Output 2 10 S1 Output Source Output 1 11 D1 Output Drain Output 1 Output 1 MOSFET drain pin. 12 D6 Output Drain Output 6 Output 6 MOSFET drain pin. 13 S6 Output Source Output 6 14 IN6 Input Command Input 6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. 15 EN Input Enable Input IC Enable. Active high. With EN low, the device is in Sleep mode. 16 SCLK Clock SPI Clock 17 DI Input Serial Data Input SPI control data input pin from MCU to the 33879. Logic  activates output. 18 CS Input SPI Chip Select SPI control chip select input pin from MCU to the 33879. Logic  allows data to be transferred in. 19 IN5 Input Command Input 5 20 S5 Output Source Output 5 21 D5 Output Drain Output 5 Output 5 MOSFET drain pin. 22 D3 Output Drain Output 3 Output 3 MOSFET drain pin. Definition Digital ground. Logic supply for SPI interface. With VDD low the device will be in Sleep mode. Output 8 MOSFET source pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 6 MOSFET source pin. SPI control clock input pin. PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. Output 5 MOSFET source pin. 33879 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33879 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 15. Pin Number Pin Name Pin Function Formal Name 23 S3 Output Source Output 3 26 D4 Output Drain Output 4 27 S4 Output Source Output 4 28 D7 Output Drain Output 7 29 S7 Output Source Output 7 31 VPWR Input Battery Input 32 DO Output Serial Data Output 33 EP Ground Exposed Pad Definition Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pin. Power supply pin to the 33879. VPWR has internal reverse battery protection. SPI control data output pin from the 33879 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Device will perform as specified with the Exposed Pad un-terminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 1 (GND) and system ground. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. 33879 Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit VDD - 0.3 to 7.0 VDC – - 0.3 to 7.0 VDC ELECTRICAL RATINGS VDD Supply Voltage(1) CS, DI, DO, SCLK, IN5, IN6, and EN(1) VPWR (1) VPWR Supply Voltage VDC 33879 -16 to 40 33879A -16 to 45 Output Clamp Energy(2) ECLAMP 50 ± 450 mJ V ESD Voltage(3) Human Body Model 33879 VESD1 Machine Model 33879 VESD2 ±100 VESD1 ±2000 Human Body Model 33879A Machine Model 33879A VESD2 ±200 THERMAL RATINGS °C Operating Temperature Ambient TA - 40 to 125 Junction TJ - 40 to 150 Case TC - 40 to 125 Storage Temperature TSTG - 55 to 150 °C Power Dissipation(4) PD 1.7 W RθJA 71 RθJC 1.2 TPPRT Note 6 °C/W Thermal Resistance Junction to Ambient Between the Die and the Exposed Die Pad Peak Package Reflow Temperature During Reflow (5), (6) °C Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200pF, RZAP = 0Ω). 4. Maximum power dissipation at TA = 25°C with no heatsink used. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 6. 33879 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 3.1V ≤ VDD ≤ 5.5V, 5.5V ≤ VPWR ≤ 18V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max 5.5 – 26.5 5.5 – 27.5 – 14 24 – 2.0 5.0 – 2.0 5.0 33879 27 28.5 32 33879A 28 30 33 Unit POWER INPUT Supply Voltage Range VPWR (FO) Fully Operational 33879 33879A Supply Current IPWR (ON) Sleep State Supply Current IPWR (SS) VDD or EN ≤ 0.8V, VPWR = 13V Sleep State Supply Current V μA μA IVDD (SS) EN ≤ 0.8V, VDD = 5.5V VPWR Over-voltage Shutdown Threshold Voltage mA VPWR(OV) V VPWR Over-voltage Shutdown Hysteresis Voltage VPWR(OV-HYS) 0.2 1.5 2.5 V VPWR Under-voltage Shutdown Threshold Voltage VPWR(UV) 3.0 4.0 5.0 V VPWR Under-voltage Shutdown Hysteresis Voltage VPWR(UV-HYS) 300 500 700 mV Logic Supply Voltage VDD 3.1 – 5.5 V Logic Supply Current IDD 250 400 700 μA VDD(SS) 0.8 2.5 3.0 V Logic Supply Sleep State Threshold Voltage 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1V ≤ VDD ≤ 5.5V, 5.5V ≤ VPWR ≤ 18V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max – – 1.4 – 0.75 – – – – 0.6 – 1.2 2.5 4.0 4.5 35 55 90 20 30 60 65 100 160 40 75 135 40 45 55 -15 - 20 - 25 – – 5.0 Unit POWER OUTPUT Drain-to-Source ON Resistance (IOUT = 0.350A, VPWR = 13V) TJ = 125°C TJ = 25°C TJ = -40°C Output Self Limiting Current High Side and Low Side Configurations Output Fault Detection Voltage Threshold(7) IOUT (LIM) VOUT(FLT-TH) Outputs Programmed OFF Output Fault Detection Current @ Threshold, High Side Configuration Output OFF Open Load Detection Current, High Side Configuration Over-temperature Shutdown Hysteresis(8) μA – – 5.0 μA IOUT (LKG) VDD = 5.0V, VDRAIN = 16V, VSOURCE = 0V, Open Load Detection Current Disabled Over-temperature Shutdown(8) μA IOUT (LKG) VDD = 5.0V, VDRAIN = 16V, VSOURCE = 0V, Open Load Detection Current Disabled Output Leakage Current High Side Configuration V IOUT (LKG) VDD = 0V, VDRAIN = 16V, VSOURCE = 0V Output Leakage Current Low Side Configuration V VOC (HSD) IS = -10mA Output Leakage Current High Side and Low Side Configurations μA VOC (LSD) ID = 10mA Output Clamp Voltage High Side Drive μA IOCO VDRAIN = 16V, VSOURCE = 0V, Outputs Programmed OFF, VPWR=16V Output Clamp Voltage Low Side Drive μA IOCO VDRAIN = 16V, VSOURCE = 0V, Outputs Programmed OFF, VPWR=16V Output OFF Open Load Detection Current, Low Side Configuration μA IOUT(FLT-TH) Outputs Programmed OFF A V IOUT(FLT-TH) Outputs Programmed OFF Output Fault Detection Current @ Threshold, Low Side Configuration Ω RDS (ON) – – 20 TLIM 155 – 185 °C TLIM (HYS) 5.0 10 15 °C Notes 7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 8. This parameter is guaranteed by design; however, it is not production tested. 33879 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1V ≤ VDD ≤ 5.5V, 5.5V ≤ VPWR ≤ 18V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit Input Logic High-voltage Thresholds(9) VIH 0.7 VDD – VDD + 0.3 V Input Logic Low-voltage Thresholds(9) VIL GND - 0.3 – 0.2 VDD V -10 – 10 DIGITAL INTERFACE IN5, IN6, EN Input Logic Current μA I IN5, I IN6, I EN IN5, IN6, EN = 0V IN5, IN6 Pull-down Current μA I IN5, I IN6, 0.8 to 5.0V EN Pull-down Current 0 to 5.0 V CS Input Current -10 – 10 μA -10 – 10 μA ICS -30 – -100 – – 10 μA ICS(LKG) VDOHIGH V VDD - 0.4 – VDD – – 0.4 – – 20 VDOLOW IDO-LOW = 1.6mA Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN(10) 100 ICS IDO-HIGH = -1.6mA DO Low-state Output Voltage 45 μA DO CS = 5.0V, VDD = 0V DO High-state Output Voltage 20 I SCK, I DI, I TRI- CS = 0V CS Leakage Current to VDD 100 μA CS = VDD CS Pull-up Current 45 I EN EN = 5.0V SCLK, DI Input, Tri-state DO Output 30 CIN V pF Notes 9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 10. This parameter is guaranteed by design; however, it is not production tested. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1V ≤ VDD ≤ 5.5V, 5.5V ≤ VPWR ≤ 18V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max 0.1 0.5 1.0 0.1 0.5 1.0 Unit POWER OUTPUT TIMING Output Slew Rate Low Side Configuration(11) t SR(RISE) RLOAD = 620Ω, CL = 200pF Output Slew Rate Low Side Configuration(11) t SR(FALL) RLOAD = 620 Ω, CL = 200 pF Output Rise Time High Side Configuration(11) Output Turn OFF Delay Time, High Side and Low Side Configuration(12) Output Fault Delay Time(13) Power-ON Reset Delay VDD or EN ≤ 0.2 V 0.1 0.3 1.0 0.1 0.3 1.0 1.0 15 50 1.0 30 100 100 – 300 100 – – V/μs μs t DLY(ON) μs t DLY(OFF) t FAULT μs μs tPOR Delay Time Required from Rising Edge of EN and VDD to SPI Active Low-State Duration on VDD or EN for Reset V/μs t SR(FALL) RLOAD = 620Ω, CL = 200pF Output Turn ON Delay Time, High Side and Low Side Configuration(12) V/μs t SR(RISE) RLOAD = 620Ω, CL = 200pF Output Fall Time High Side Configuration(11) V/μs t RESET µs 100 – – Notes 11. Output slew rate respectively measured across a 620Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points. CL capacitor is connected from Drain or Source output to Ground. 12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points. 13. Duration of fault before fault bit is set. Duration between access times must be greater than 300μs to read faults. 33879 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1V ≤ VDD ≤ 5.5V, 5.5V ≤ VPWR ≤ 18V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit f SPI – 4.0 – MHz Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) t LEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) t LAG 50 – – ns DI to Falling Edge of SCLK (Required Setup Time) t DI (SU) 16 – – ns Falling Edge of SCLK to DI (Required Hold Time) t DI (HOLD) 20 – – ns DI, CS, SCLK Signal Rise Time(15) t R (DI) – 5.0 – ns DI, CS, SCLK Signal Fall Time(15) t F (DI) – 5.0 – ns Time from Falling Edge of CS to DO Low Impedance(16) t DO (EN) – – 55 ns Time from Rising Edge of CS to DO High Impedance(17) t DO (DIS) – – 55 ns t VALID – 25 55 ns DIGITAL INTERFACE TIMING(14) Recommended Frequency of SPI Operation(14) Time from Rising Edge of SCLK to DO Data Valid(18) Notes 14. 15. 16. 17. 18. This parameter is guaranteed by design. Production test equipment uses 4.16MHz, 5.5V/3.1V SPI interface. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at DO pin. Time required for output status data to be terminated at DO pin. Time required to obtain valid data out from DO following the rise of SCLK. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS 0.2 VDD tLEAD tLAG 0.7 VDD SCLK 0.2 VDD tDI(SU) tDI(HOLD) 0.7 VDD 0.2 VDD DI MSB in tDO(EN) 0.7 VDD 0.2 VDD DO tDO(DIS) tVALID MSB out LSB out Figure 4. SPI Timing Diagram < 50 ns tR(DI) VDD = 5.0 V 0.7 VDD 33879 Under Test < 50 ns 3.3/5.0 V 50% SCLK SCLK tF(DI 0.2 VDD 0V DO 0.7 VDD CL = 200 pF DO 0.2 VDD VOL tR(DO (Low-to-High) tVALID DO (High-to-Low) 0.7 VDD NOTE: CL represents the total capacitance of the test fixture and probe. 0.2 Figure 5. Valid Data Delay Time and Valid Time Test Circuit VOH VOH VOL Figure 6. Valid Data Delay Time and Valid Time Waveforms tF(CS) tR(CS) < 50 ns < 50 ns 3.3/5.0 V 90% CS 0.2 VDD 0.7 VDD 10% 0V tDO(EN) DO (Tri-State to Low) tDO(DIS) VTri-State 90% 10% tDO(EN) tDO(DIS) 90% DO 10% VOL VOH VTri-State (Tri-State to High) Figure 7. Enable and Disable Time Waveforms 33879 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TYPICAL ELECTRICAL CHARACTERISTICS TYPICAL ELECTRICAL CHARACTERISTICS 7 VPWR @ 18 V 19 33879 18 17 16 33879A 15 14 -40 -25 0 25 50 75 100 VPWR @ 13 V IPWR Current into VPWR Pin (µA) IPWR Current into VPWR Pin (mA) 20 125 6 5 4 3 2 1 -40 -25 25 50 75 100 125 TA, Ambient Temperature (°C) Figure 9. Sleep State IPWR vs. Temperature TA, Ambient Temperature (°C) Figure 8. IPWR vs. Temperature 1.4 140 TA = 25°C 1.2 120 VPWR @ 13 V High Side Drive 1.0 100 RDS(ON) (Ω) IPWR Current into VPWR Pin (µA) 0 33879 80 60 40 20 0.8 0.6 0.4 33879A 0 5 10 15 VPWR 20 -40 -25 25 125 Figure 11. RDS(ON) vs. Temperature at 350mA Figure 10. Sleep State IPWR vs. VPWR 1.4 0 25 50 75 100 TA, Ambient Temperature (°C) TA = 25°C High Side Drive 1.2 RDS(ON) (Ω) 1.0 0.8 0.6 0.4 0.2 0 5 10 15 20 25 VPWR (V) Figure 12. RDS(ON) vs. VPWR at 350mA 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 13 140 IOCO, Open Load (µA) VPWR @ 13 V 120 100 80 60 High Side 40 Low Side 20 -40 -25 0 25 50 75 100 125 TA, Ambient Temperature (°C) Figure 13. Open Load Detection Current at Threshold VOUT(flt-th), Open Load Threshold (V) ELECTRICAL CHARACTERISTICS TYPICAL ELECTRICAL CHARACTERISTICS 5.5 5.0 VPWR @ 13 V High Side and Low Side 4.5 4.0 3.5 3.0 2.5 -40 -25 0 25 50 75 100 125 TA, Ambient Temperature (°C) Figure 14. Open Load Detection Threshold vs. Temperature 33879 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CS PIN The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SPI clock (SCLK) is in a logic low state. SCLK PIN The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to ensure validity of data. It is essential that the SCLK pin be in a logic low state when the CS pin makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is tri-state. Load Detection Current disabled will report logic  in the off state. The first eight positive transitions of SCLK will report logic  followed by the status of the eight output drivers. The DI / DO shifting of data follows a first-in, first-out protocol with both input and output words transferring the most significant bit (MSB) first. EN PIN The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open / short fault detection performed and reported. With the EN pin low, all outputs become inactive, Open Load Detection Current is disabled, and the device enters Sleep mode. The 33879 will perform Power-ON Reset on rising edge of the enable signal. IN5 AND IN6 PINS The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the Serial Peripheral Interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic . Maximum PWM frequency for each output is 2.0 kHz. DI PIN VDD PIN The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs and Open Load Detection Current on or off, send the DI data beginning with the Open Load Detection Current bits, followed by output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register. The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive DO output and the pullup current for CS. VDD must be applied for normal mode operation. The 33879 device will perform Power-ON Reset with the application of VDD. DO PIN The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879 device are reported as logic  through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are reported as logic . Conversely, normal operating outputs with non-faulted loads are reported as logic . Outputs programmed with Open VPWR PIN The VPWR pin is battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal logic current is provided from the VPWR pin. The 33879 will perform Power-ON Reset with the application of VPWR. D1– D8 PINS The D1 to D8 pins are the open-drain outputs of the 33879. For high-side drive configurations, the drain pins are connected to battery supply. In low side drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When configured as low side drive, the 33879 limits the positive inductive transient to 45V. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION MCU INTERFACE DESCRIPTION S1– S8 PINS EXPOSED PAD PIN The S1 to S8 pins are the source outputs of the 33879. For high side drive configurations, the source pins are connected directly to the load. In low side drive configurations, the source is connected to ground. All outputs may be configured individually as desired. When high side drive is used, the 33879 will limit the negative inductive transient to negative 20 V. Device will perform as specified with the Exposed Pad unterminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 1 (GND) and system ground. MCU INTERFACE DESCRIPTION INTRODUCTION The 33879 is an 8-output hardware-configurable power switch with 16-bit serial control. A simplified internal block diagram of the 33879 is shown in Figure 2 on page 3. The 33879 device uses high-efficiency up-drain power DMOS output transistors exhibiting low drain-to-source ON resistance (RDS(ON) = 0.75 Ω at 25°C typical) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast inductive turn-off and transient protection. In operation, the 33879 functions as an 8-output serial switch serving as a MCU bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly interfaces to an MCU using a SPI for control and diagnostic readout. Figure 15 illustrates the basic SPI configuration between an MCU and one 33879. All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. When a SPI bit is programmed to a logic , the corresponding output will be OFF. Conversely, when a SPI bit is programmed to logic  the output being controlled will be ON. Diagnostics are treated in a similar manner. Outputs with a fault will feed back (via DO) a logic  to the microcontroller, while normal operating outputs will provide a logic . Figure 16 illustrates the daisy chain configuration using the 33879. Data from the MCU is clocked daisy chain through each device while the CS bit is commanded low by the MCU. During each clock cycle, output status from the daisy chain is transferred to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS, command data stored in the input register is then transferred to the output driver. SCLK Parallel Port MC68HCxx Microcontroller 33879 33879 CS MC68HCxx MISO Microcontroller DO with SPI Interface MOSI DI MISO DO Shift Register Shift Register 16 Bits DI 8 Outputs 33879 33879 CS SCLK CS SCLK DO DI DO DI 8 Outputs 8 Outputs 16 Bits MOSI SCLK Receive Buffer Parallel Ports To Logic CS Figure 15. SPI Interface with Microcontroller Figure 16. 33879 SPI System Daisy Chain Multiple 33879 devices can be controlled in a parallel input fashion using the SPI. Figure 17 illustrates the control of 24 loads using three dedicated parallel MCU ports for chip select. 33879 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION SPI DEFINITION 33879 MOSI DI SCLK SCLK MISO 8 Outputs DO CS MC68HCxx Microcontroller with SPI Interface 33879 DI SCLK DO CS 8 Outputs 33879 Parallel Ports A DI B SCLK C DO 8 Outputs CS Figure 17. Parallel Input SPI Control SPI DEFINITION Fault Register, shown in Table 7, defines the previous state status of the output driver. Table 8 identifies the type of fault and the method by which the fault is communicated to the microprocessor. On each SPI communication, a 16-bit command word is sent to the 33879 and a 16-bit status word is received from the 33879. The MSB is sent and received first. As Table 6 shows, the Command Register defines the position and operation the 33879 will perform on rising edge of CS. The Table 6. Command Register Definition MSB LSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ON / OFF Open Load Detect 8 ON / OFF Open Load Detect 7 ON / OFF Open Load Detect 6 ON / OFF Open Load Detect 5 ON / OFF Open Load Detect 4 ON / OFF Open Load Detect 3 ON / OFF Open Load Detect 2 ON / OFF Open Load Detect 1 ON / OFF OUT 8 ON / OFF OUT 7 ON / OFF OUT 6 ON / OFF OUT 5 ON / OFF OUT 4 ON / OFF OUT 3 ON / OFF OUT 2 ON / OFF OUT 1 0 = Bits 0 to 7, Output commanded OFF. 0 = Bits 8 to 15, Open Load Detection Current OFF. 1 = Bits 0 to 7, Output commanded ON. 1 = Bits 8 to 15 Open Load Detection Current ON. Table 7. Fault Register Definition MSB LSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 OUT 8 Status OUT 7 Status OUT 6 Status OUT 5 Status OUT 4 Status OUT 3 Status OUT 2 Status OUT 1 Status 0 = Bits 0 to 7, No Fault at Output. 1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND, Open Load, or TLIM. Bits 8 to 15 will always return “0”. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION SPI DEFINITION Table 8. Fault Operation Serial Output (DO) Pin Reports Overtemperature Fault reported by serial output (DO) pin. Overcurrent DO pin reports short to battery/supply or overcurrent condition. Output ON Open Load Fault Not reported. Output OFF Open Load Fault DO pin reports output OFF open load condition only with Open Load Detection Current enabled. DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled. Device Shutdowns Overvoltage Total device shutdown at VPWR = VPWR(OV) V. Resumes normal operation with proper voltage. All outputs assuming the previous state upon recovery from overvoltage. Overtemperature Only the output experiencing an overtemperature shuts down. Output assumes previous state upon recovery from overtemperature. 33879 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION DEVICE OPERATION DEVICE OPERATION POWER SUPPLY SPI INTEGRITY CHECK The 33879 device has been designed with ultra-low Sleep mode currents. The device may enter Sleep mode via the EN pin or the VDD pin. In the Sleep mode (EN or VDD ≤ 0.8 V), the current consumed by the VPWR pin is less than 5.0 μA. Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system start-up or reset, the MCU will write one 32-bit pattern to the 33879. The first 16 bits read by the MCU will be 8 logic s followed by the fault status of the outputs. The second 16 bits will be the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 16-bit pattern the MCU sends to the device is the command word and will be transferred to the outputs with rising edge of CS. Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter will be acknowledged. SPI messages consisting of other than 16 + multiples of 8 SCLK pulses will be ignored by the device. Placing the 33879 in Sleep mode resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and Open Load Detection Current disabled. To place the 33879 in the Sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power from the VDD supply pin. Prior to removing VDD from the device, it is recommended that all control inputs from the MCU be low. PARALLELING OF OUTPUTS Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(ON) of MOSFETs have an inherent positive temperature coefficient that provides balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the output OFF Open Load Detection Currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is possible but not recommended. FAULT LOGIC OPERATION Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted and Open Load Detection Current enabled, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit / overtemperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short / overtemperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / shortto-battery for high-side drive or open / short-to-ground for lowside drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the fault is a short-to-ground / overtemperature for high-side drive or short-to-battery/overtemperature for low-side drive. The timing between two write words must be greater than 300 μs to allow adequate time to sense and report the proper fault status. OVERTEMPERATURE FAULT Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155°C to 185°C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15°C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down. OVERVOLTAGE FAULT An overvoltage condition on the VPWR pin will cause the device to shut down all outputs until the overvoltage condition is removed. When the overvoltage condition is removed, the outputs will resume their previous state. This device does not detect an overvoltage on the VDD pin. The overvoltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR overvoltage detection is global, causing all outputs to be turned OFF. OUTPUT OFF OPEN LOAD FAULT An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION DEVICE OPERATION An output OFF open load fault is indicated when the drainto-source voltage is less than the output threshold voltage (VOUT(flt-th)) of 2.5 V to 4.0 V. Hence, the 33879 will declare the load open in the OFF state when the output drain-tosource voltage is less than VOUT(flt-th). This device has an internal 80 μA current source connected from drain to source of the output MOSFET. The current source may be programmed on or off via SPI. The Power-ON Reset state for the current source is “off” and must be enabled via SPI. To achieve low Sleep mode quiescent currents, the Open Load Detection Current source of each driver is switched off when VDD or EN is removed. During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 μs to 300 μs is incorporated. A false fault reporting is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer will time out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the device will resume normal operation. The open load fault, however, will be latched in the output DO register for the MCU to read. OUTPUT VOLTAGE CLAMP Each output of the 33879 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive configurations. The total energy clamped (E J) can be calculated by multiplying the current area under the current curve (I A) times the clamp voltage (V CL) (see Figure 18). Characterization of the output clamps, using a single pulse non-repetitive method at 0.35 A, indicates the maximum energy per output to be 50 mJ at 150°C junction temperature. Drain-to-Source Clamp Voltage (V CL = 45 V) Drain Current (I D = 0.3 A) Clamp Energy (E J = I A x V CL) Drain-to-Source ON Voltage (V DS(ON)) Current Area (I A) GND SHORTED LOAD FAULT A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. There are two safety circuits progressively in operation during load short conditions that provide system protection: 1. The device’s output current is monitored in an analog fashion using SENSEFET approach and current limited. 2. The device’s output thermal limit is sensed and when attained causes only the specific faulted output to shut down. The output will remain off until cooled. The device will then reassert the output automatically. The cycle will continue until fault is removed or the command bit instructs the output off. Shorted load faults will be reported properly through SPI regardless of Open Load Detection Current enable bits. UNDERVOLTAGE SHUTDOWN An undervoltage condition on VDD or VPWR will result in the shutdown of all outputs. The VDD undervoltage threshold is between 0.8 V and 3.0 V. VPWR undervoltage threshold is between 3.0 V and 5.0 V. When the supplies fall below their respective thresholds, all outputs are turned OFF. As both supplies returns to normal levels, internal logic is reset and the device resumes normal operation. Drain Voltage Time Drain-to-Source ON Voltage (V DS(ON)) VS BAT GND Time Current Area (I A) Clamp Energy (E J = I A x V CL) Source Current (I S = 0.3 A) Source Clamp Voltage (V CL = -15 V) Source Voltage Figure 18. Output Voltage Clamping SPI CONFIGURATIONS The SPI configuration on the 33879 device is consistent with other devices in the Octal Serial Switch (OSS) family. This device may be used in serial SPI or parallel SPI with the 33298 and 33291. Different SPI configurations may be provided. For more information, contact Freescale Analog Products Division or local Freescale representative. REVERSE BATTERY The 33879 has been designed with reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral substrate diode. During the reverse battery condition, current will flow through the load via the substrate diode. Under this circumstance, relays may energize and lamps will turn on. Where load reverse battery protection is desired, a reverse battery blocking diode must be placed in series with the load. 33879 20 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below. DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 21 PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C 33879 22 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C 33879 Analog Integrated Circuit Device Data Freescale Semiconductor 23 REVISION HISTORY REVISION HISTORY REVISION 5.0 DATE 2/2006 DESCRIPTION OF CHANGES • • • • • • • • • • 6.0 7.0 6/2007 8/2008 • • • • Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram. Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition. Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains no hysteresis. Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max parameter has been increased from 70uA to 90uA. Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test. Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test. Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been decreased from 7uA to 5uA. Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin. Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right. ALL Pages; Updated Data Sheet to reflect Freescale formatting. • • • Added 33879A version Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information Added Device Variations on page 2 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on page 6. Added note with instructions from www.freescale.com. Changed Output Fault Detection Voltage Threshold(7) on page 8 Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on page 14 Changed Overvoltage on page 18 and Overvoltage Fault on page 19 • Updated package drawing. 33879 24 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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