Freescale Semiconductor Technical Data MM908E626 Rev 3.0, 12/2005 Document order number: Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication The 908E626 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOS TM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator (ICG) module. The analog control die provides fully protected H-Bridge outputs, voltage regulator, autonomous watchdog, and local interconnect network (LIN) physical layer. 908E626 STEPPER MOTOR DRIVER WITH EMBEDDED MCU AND LIN The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive stepper applications like climate control and light-levelling. Features • High-Performance M68HC08EY16 Core • 16 K Bytes of On-Chip Flash Memory • 512 Bytes of RAM • Internal Clock Generation Module • Two 16-Bit, 2-Channel Timers • 10-Bit Analog-to-Digital Converter • Four Low RDS(ON) Half-Bridge Outputs • 13 Microcontroller I/Os DWB SUFFIX 98ARL105910 54-TERMINAL SOICWB-EP Device MM908E626AVDWB Temperature Range (TA) Package -40°C to 115°C 54 SOIC WB-EP 908E626 Simplified Application Diagram 908E626 LIN VREFH VDDA EVDD VDD VSUP[1:3] HB1 HB2 VREFL VSSA EVSS VSS RST RST_A IRQ IRQ_A SS PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 FGEN BEMF PTD0/TACH0/BEMF HB3 HB4 HVDD GND[1:2] EP Port A I/Os Port B I/Os Port C I/Os Figure 1. 908E626 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. S N Bipolar Step Motor Switchable Internal VDD Output Microcontroller Ports 2 DDRA PORT A FLSVPP Security Module Power-ON Reset Module PTE0/TXD PTE1/RXD PTD0/TACH0 PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO BEMF Module Prescaler Module PTB0/AD0 PTA5/SPSCK Periodic Wake-up Timebase Module Arbiter Module MOSI PTC1/MOSI Configuration Register Module ADOUT SPSCK MISO SS PTC0/MISO PTE1/RXD Serial Peripheral Interface Module Computer Operating Properly Module PORT C DDRC PTC4/OSC1 PTC3/OSC2 Single External IRQ Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS IRQ RST 24 Integral System Integration Module PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 MCU Die PTB0/AD0 VREFH PTC2/MCLK PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 VDDA PTB4/AD4 EVDD PTB3/AD3 EVSS OSC2 Internal Clock OSC1 Generator Module IRQ PTA4/KBD4 VREFL Enhanced Serial Communication Interface Module SS PTA3/KBD3 VSSA Analog Multiplexer VSUP Prescaler Chip Temp Autonomous Watchdog SPI & CONTROL Interrupt Control Module Reset Control Module LIN Physical Layer BEMF BEMF FGEN BEMF FGEN FGEN BEMF FGEN RST_A PTA2/KBD2 RST User Flash Vector Space, 36 Bytes PTB1/AD1 PTA1/KBD1 PTA0/KBD0 PTD1/TACH1 2-channel Timer Interface Module B TXD LIN 2-channel Timer Interface Module A PTE0/TXD FGEN 5-Bit Keyboard Interrupt Module BEMF Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), 1024 Bytes PTD0/TACH0 Single Breakpoint Break Module VSUP VSUP VSUP VSUP Analog Die Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Switched VDD Driver & Diagnostic Voltage Regulator VSUP1-3 M68HC08 CPU CPU ALU Registers GND1-2 IRQ_A RXD PORT D PORT E DDRD DDRE Internal Bus DDRB PORT B Figure 2. Figure 1. 908E626 Simplified Internal Block Diagram 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor HB4 HB3 HB2 HB1 HVDD VDD VSS TERMINAL CONNECTIONS TERMINAL CONNECTIONS Transparent Top View of Package PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 IRQ RST 9 46 10 45 PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF 11 44 12 43 16 39 RST_A 17 38 IRQ_A SS 18 37 19 36 LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 13 14 15 42 Exposed Pad 41 40 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC Figure 3. 908E626 Terminal Connections Table 1. 908E626 TERMINAL DEFINITIONS A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14. Die Terminal Terminal Name Formal Name Definition MCU 1 2 6 7 8 11 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 3 4 5 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input MCU 10 RST External Reset This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. MCU 12 13 PTD0/TACH0/BEMF PTD1/TACH1 Port D I /Os These terminals are special-function, bidirectional I /O port terminals that are shared with other functional modules in the MCU. – 14, 21, 22, 28, 33, 35, 36, 37, 39 NC No Connect Not connected. This terminal is an asynchronous external interrupt input terminal. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. 908E626 TERMINAL DEFINITIONS A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14. Die Terminal Terminal Name Formal Name Definition MCU 42 PTE1/ RXD Port E I /O This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. MCU 43 48 VREFL VREFH ADC References These terminals are the reference voltage terminals for the analogto-digital converter (ADC). MCU 44 47 VSSA VDDA ADC Supply Terminals MCU 45 46 EVSS EVDD MCU Power Supply Terminals MCU 49 50 52 53 54 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I /Os MCU 51 FLSVPP Test Terminal Analog 15 FGEN Current Limitation Frequency Input This is the input terminal for the half-bridge current limitation PWM frequency. Analog 16 BEMF Back Electromagnetic Force Output This terminal gives the user information about back electromagnetic force (BEMF). Analog 17 RST_A Internal Reset Analog 18 IRQ_A Internal Interrupt Output Analog 19 SS Slave Select Analog 20 LIN LIN Bus This terminal represents the single-wire bus transmitter and receiver. Analog 23 26 29 32 HB1 HB2 HB3 HB4 Half-Bridge Outputs This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. Analog 24 27 31 VSUP1 VSUP2 VSUP3 Power Supply Terminals These terminals are device power supply terminals. Analog 25 30 GND1 GND2 Power Ground Terminals These terminals are device power ground connections. Analog 34 HVDD Switchable VDD Output This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. Analog 38 VDD Voltage Regulator Output The + 5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. Analog 40 VSS Voltage Regulator Ground Ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Analog 41 RXD LIN Transceiver Output – EP Exposed Pad Exposed Pad These terminals are the power supply terminals for the analog-todigital converter. These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For test purposes only. Do not connect in the application. This terminal is the bidirectional reset terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal is the SPI slave select terminal for the analog chip. This terminal is the output of LIN transceiver. The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. 908E626 4 Analog Integrated Circuit Device Data Freescale Semiconductor MAXIMUM RATINGS MAXIMUM RATINGS MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Analog Chip Supply Voltage under Normal Operation (SteadyState) VSUP(SS) - 0.3 to 28 Unit ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Transient Conditions V (1) VSUP(PK) - 0.3 to 40 VDD - 0.3 to 6.0 VIN (ANALOG) - 0.3 to 5.5 VIN (MCU) VSS - 0.3 to VDD + 0.3 Microcontroller Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip V Maximum Microcontroller Current per Terminal mA All Terminals Except VDD, VSS, PTA0 : PTA6, PTC0 : PTC1 IPIN(1) ±15 Terminals PTA0 : PTA6, PTC0 : PTC1 IPIN(2) ± 25 Maximum Microcontroller VSS Output Current IMVSS 100 mA Maximum Microcontroller VDD Input Current IMVDD 100 mA LIN Supply Voltage V VBUS(SS) -18 to 28 VBUS(DYNAMIC) 40 VESD1 ± 3000 VESD2 ± 150 VESD3 ± 500 TSTG - 40 to 150 °C Operating Case Temperature (5) TC - 40 to 115 °C Operating Junction Temperature(6) TJ - 40 to 135 °C TSOLDER 245 °C Normal Operation (Steady-State) Transient Conditions (1) ESD Voltage Human Body Model (2) Machine Model (3) Charge Device Model (4) V THERMAL RATINGS Storage Temperature Peak Package Reflow Temperature During Solder Mounting (7) Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 3. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 4. ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP = 4.0 pF). 5. 6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 8.0 – 18 V SUPPLY VOLTAGE Nominal Operating Voltage SUPPLY CURRENT NORMAL Mode IRUN VSUP = 12 V, Power Die ON (PSON = 1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled mA – 20 – DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Terminals RST_A, IRQ_A V Low-State Output Voltage (IOUT = - 1.5 mA) VOL – – 0.4 High-State Output Voltage (IOUT = 1.0 µA) VOH 3.85 – – Low-State Output Voltage (IOUT = - 1.5 mA) VOL – – 0.4 High-State Output Voltage (IOUT = 1.5 mA) VOH 3.85 – – CIN – 4.0 – Output Terminals BEMF, RXD Output Terminal RXD – Capacitance (8) V Input Terminals RST_A, FGEN, SS pF V Input Logic Low Voltage VIL – – 1.5 Input Logic High Voltage VIH 3.5 – – CIN – 4.0 – pF Terminals RST_A, IRQ_A – Pullup Resistor RPULLUP1 – 10 – kΩ Terminal SS – Pullup Resistor RPULLUP2 – 60 – kΩ RPULLDOWN – 60 – kΩ IPULLUP – 35 – µA Input Terminals RST_A, FGEN, SS – Capacitance (8) Terminals FGEN, MOSI, SPSCK – Pulldown Resistor Terminal TXD – Pullup Current Source Notes 8. This parameter is guaranteed by process monitoring but is not production tested. 908E626 6 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SYSTEM RESETS AND INTERRUPTS High-Voltage Reset V Threshold VHVRON 27 30 33 Hysteresis VHVRH – 1.5 – Threshold VLVRON 3.6 4.0 4.7 V Hysteresis VLVRH – 100 – mV Threshold VHVION 17.5 21 23 Hysteresis VHVIH – 1.0 – Threshold VLVION 6.5 – 8.0 Hysteresis VLVIH – 0.4 – Low-Voltage Reset High-Voltage Interrupt V Low-Voltage Interrupt V °C High-Temperature Reset (9) Threshold TRON – 170 – Hysteresis TRH 5.0 – – Threshold TION – 160 – Hysteresis TIH 5.0 – – 4.75 5.0 5.25 °C High-Temperature Interrupt (10) VOLTAGE REGULATOR Normal Mode Output Voltage VDDRUN IOUT = 60 mA, 6.0 V < VSUP < 18 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V V VLR mV – – 100 Notes 9. This parameter is guaranteed by process monitoring but is not production tested. 10. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C). 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 7 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER Output Low Level VLIN-LOW TXD LOW, 500 Ω Pullup to VSUP Output High Level – Leakage Current to GND – 1.4 VLIN-HIGH TXD HIGH, IOUT = 1.0 µA Pullup Resistor to VSUP V RSLAVE V VSUP - 1.0 – – 20 30 60 µA IBUS_PAS_REC 0.0 Recessive State (- 0.5 V < VLIN < VSUP) – 20 µA Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V IBUS_NO_GND – - 600 – Including Internal Pullup Resistor, VLIN @ +18 V IBUS – 25 – Recessive VIH 0.6 VLIN – VSUP Dominant VIL 0 – 0.4 VLIN VITH – VSUP / 2 – VIHY 0.01 VSUP – 0.1 VSUP LIN Receiver Threshold Input Hysteresis kΩ V 908E626 8 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit HALF-BRIDGE OUTPUTS (HB1 : HB4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A mΩ High Side RDS(ON)HB_HS – 425 500 Low Side RDS(ON)HB_LS – 400 500 High-Side Overcurrent Shutdown IHBHSOC 3.0 – 7.5 A Low-Side Overcurrent Shutdown IHBLSOC 2.5 – 7.5 A ICL1 – 55 – ICL2 210 260 315 Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) ICL3 300 370 440 Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) ICL4 450 550 650 Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) ICL5 600 740 880 Half-Bridge Output HIGH Threshold for BEMF Detection VBEMFH – - 30 0.0 V Half-Bridge Output LOW Threshold for BEMF Detection VBEMFL – - 60 - 5.0 mV VBEMFHY – 30 – mV CSA = 1 RATIOH 7.0 12.0 14.0 CSA = 0 RATIOL 1.0 2.0 3.0 IHVDDOCT 24 30 40 mA RATIOVSUP 4.8 5.1 5.35 – STTOV – 19 – mV/ °C VT25 1.7 2.1 2.5 V Low-Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Hysteresis for BEMF Detection mA Low-Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A]) V/A SWITCHABLE VDD OUTPUT (HVDD) Overcurrent Shutdown Threshold VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP / VADOUT) INTERNAL DIE TEMPERATURE SENSOR Voltage / Temperature Slope Output Voltage @ 25°C 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 9 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER Propagation Delay (11), (12) µs t TXD-LIN-LOW – – – – - 2.0 - 2.0 – – 4.0 4.0 – – 6.0 6.0 8.0 8.0 2.0 2.0 -1.0 - 2.0 - 3.0 1.0 2.0 3.0 SRS - 2.0 – 2.0 µs t OSC – 40 – µs AWD Period Low = 512 t OSC t AWDPH 16 22 28 ms AWD Period High = 256 t OSC t AWDPL 8.0 11 14 ms TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH t TXD-LIN-HIGH t LIN-RXD-LOW t LIN-RXD-HIGH TXD Symmetry t TXD-SYM RXD Symmetry t RXD-SYM Output Falling Edge Slew Rate (11), (13) SRF 80% to 20% Output Rising Edge Slew Rate (11), (13) SRR 20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF LIN Rise / Fall Slew Rate Symmetry (11), (13) V/µs V/µs AUTONOMOUS WATCHDOG (AWD) AWD Oscillator Period Notes 11. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0 : SRS1= 00). 12. See Figure 4, page 12. 13. See Figure 5, page 12. 908E626 10 Analog Integrated Circuit Device Data Freescale Semiconductor MICROCONTROLLER PARAMETRICS MICROCONTROLLER PARAMETRICS MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description Core High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with Two Channels (TIM A and TIM B) Flash 16 K Bytes RAM 512 Bytes ADC 10-Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module BEMF Counter Special Counter for SMARTMOS BEMF Output 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 11 TIMING DIAGRAMS TIMING DIAGRAMS t TXD-LIN-LOW t t TXD-LIN-HIGH tTx-LIN-high Tx-LIN-low TXD Tx TXD LIN LIN Recessive State 0.9 VSUP VSUP 0.9 Recessive State 0.6 VSUP VSUP 0.4 VSUP VSUP 0.1 SUP 0.1 V VSUP Dominant State Rx RXD t LIN-RXD-LOW t ttLIN-RXD-HIGH LIN-Rx-low LIN-Rx-high Figure 4. LIN Timing Description ∆t Fall-time ∆t Rise-time 0.8 VSUP 0.8 VSUP 0.8 VSUP VSUP ∆V Fall ∆V Rise 0.2 VSUP VSUP 0.2 0.2VSUP VSUP 0.2 Dominant State SRF = ∆V Fall ∆t Fall-time SRR = ∆V Rise ∆t Rise-time Figure 5. LIN Slew Rate Description 908E626 12 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS Functional Diagrams 1.6 1.4 1.2 TJ = 25°C Volts Volts 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Amperes Amperes 4.0 4.5 5.0 H-Bridge Low Side Figure 6. Free Wheel Diode Forward Voltage 250 200 Dropout Drop Out(mV) (mV) TA = 125°C 150 100 TA = 25°C 50 TA = -40°C 0 0 5 5.0 10 15 Load (mA) IILOAD (mA) 20 25 Figure 7. Dropout Voltage on HVDD 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E626 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E626 is well suited to perform stepper motor control, e.g. for climate or light-levelling control via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as four half-bridge outputs. Other ports are also provided including a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figures 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on Figures 3 for a depiction of the terminal locations on the package. PORT A I /O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt terminals, KBD0 : KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O TERMINALS (PTB1, PTB3:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6 : PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT D I /O TERMINALS (PTD0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are specialfunction, bidirectional I /O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application. PORT E I /O TERMINAL (PTE1) PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS (PTC2:4) EXTERNAL RESET TERMINAL (RST) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. 908E626 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT TERMINAL (FGEN) Input terminal for the half-bridge current limitation PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generated automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. BACK ELECTROMAGNETIC FORCE OUTPUT TERMINAL (BEMF) This terminal gives the user information about back electromagnetic force (BEMF). This feature allows stall detection and coil failures in step motor applications. In order to evaluate this signal the terminal must be directly connected to terminal PTD0 / TACH0 / BEMF. RESET TERMINAL (RST_A) RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pullup resistor and must be connected to the RST terminal of the MCU. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU. SLAVE SELECT TERMINAL (SS) This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I /O of the microcontroller. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT TERMINALS (HB1: HB4) The 908E626 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1: HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1: HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. POWER SUPPLY TERMINALS (VSUP1: VSUP3) VSUP1: VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality. POWER GROUND TERMINALS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality. SWITCHABLE VDD OUTPUT TERMINAL (HVDD) The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; The output is short-circuit protected. + 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR GROUND TERMINAL (VSS) The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL terminals must be connected together. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. This terminal should be either left open (not connected) or connected to GND. EXPOSED PAD TERMINAL The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. 908E626 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPTS The 908E626 has five different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. INTERRUPT FLAG REGISTER (IFR) Register Name and Address: IFR - $05 Read LOW-VOLTAGE INTERRUPT Write The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) are switched off. All other modules are not influenced by this interrupt. Reset HIGH-VOLTAGE INTERRUPT The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) are switched off. All other modules are not influenced by this interrupt. HIGH-TEMPERATURE INTERRUPT The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated. LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt. OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge or the HVDD output is detected and the OCIE bit is set and an interrupt generated. Bit 7 6 5 4 3 2 0 0 LINF HTF LVF HVF 0 0 0 0 0 0 1 Bit 0 OCF 0 0 0 LINF — LIN FLAG BIT This read / write flag is set on the falling edge at the LIN data line. Clear LINF by writing a logic [1] to LINF. Reset clears the LINF bit. Writing a logic [0] to LINF has no effect. • 1 = Falling edge on LIN data line has occurred. • 0 = Falling edge on LIN data line has not occurred since last clear. HTF — HIGH-TEMPERATURE FLAG BIT This read / write flag is set on a high-temperature condition. Clear HTF by writing a logic [1] to HTF. If a high-temperature condition is still present while writing a logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a logic [0] to HTF has no effect. • 1 = High-temperature condition has occurred. • 0 = High-temperature condition has not occurred. LVF — LOW-VOLTAGE FLAG BIT This read / write flag is set on a low-voltage condition. Clear LVF by writing a logic [1] to LVF. If a low-voltage condition is still present while writing a logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a logic [0] to LVF has no effect. • 1 = Low-voltage condition has occurred. • 0 = Low-voltage condition has not occurred. HVF — HIGH-VOLTAGE FLAG BIT This read / write flag is set on a high-voltage condition. Clear HVF by writing a logic [1] to HVF. If high-voltage condition is still present while writing a logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a logic [0] to HVF has no effect. • 1 = High-voltage condition has occurred. • 0 = High-voltage condition has not occurred. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OCF — OVERCURRENT FLAG BIT This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 8, which shows the two signals triggering the OCF. • 1 = High-current condition has occurred. • 0 = High-current condition has not occurred. HVDD_OCF This read / write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit. • 1 = Interrupt requests from HVF flag enabled. • 0 = Interrupt requests from HVF flag disabled. INTERRUPT MASK REGISTER (IMR) Register Name and Address: IMR - $04 Write Reset LVIE — LOW-VOLTAGE INTERRUPT ENABLE BIT HVIE — HIGH-VOLTAGE INTERRUPT ENABLE BIT Figure 8. Principal Implementation for OCF Read This read / write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit. • 1 = Interrupt requests from HTF flag enabled. • 0 = Interrupt requests from HTF flag disabled. This read / write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit. • 1 = Interrupt requests from LVF flag enabled. • 0 = Interrupt requests from LVF flag disabled. OCF HB_OCF HTIE — HIGH-TEMPERATURE INTERRUPT ENABLE BIT Bit 7 6 5 4 3 2 1 0 0 LINIE HTIE LVIE HVIE OCIE 0 0 0 0 0 0 0 Bit 0 0 0 LINIE — LIN LINE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. • 1 = Interrupt requests from LINF flag enabled. • 0 = Interrupt requests from LINF flag disabled. OCIE — Overcurrent Interrupt Enable Bit This read / write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. • 1 = Interrupt requests from OCF flag enabled. • 0 = Interrupt requests from OCF flag disabled. RESET The 908E626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 9 depicts the internal reset sources. SPI REGISTERS AWDRE Flag AWD Reset Sensor VDD HVRE Flag High-Voltage Reset Sensor HTRE Flag High-Temperature Reset Sensor RST_A MONO FLOP Low-Voltage Reset Figure 9. Internal Reset Routing 908E626 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET INTERNAL SOURCES Reset Mask Register (RMR) Register Name and Address: RMR - $06 Autonomous Watchdog AWD modules generates a reset because of a timeout (watchdog function). Bit 7 Read High-Temperature Reset Write To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high-temperature reset is disabled. Reset Low-Voltage Reset The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A terminal. TTEST 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 Bit 0 HVRE HTRE 0 0 TTEST — High-Temperature Reset Test This read / write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. • 1 = Low-temperature threshold enabled. • 0 = Low-temperature threshold disabled. HVRE — High-Voltage Reset Enable Bit High-Voltage Reset The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A terminal. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high-voltage reset is disabled. RESET EXTERNAL SOURCE External Reset Terminal The microcontroller has the capability of resetting the SMARTMOS device by pulling down the RST terminal. This read / write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. • 1 = High-voltage reset enabled. • 0 = High-voltage reset disabled. HTRE — High-Temperature Reset Enable Bit This read / write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. • 1 = High-temperature reset enabled. • 0 = High-temperature reset disabled. SERIAL PERIPHERAL INTERFACE The serial peripheral interface (SPI) creates the communication link between the microcontroller and the 908E626. The interface consists of four terminals (see Figure 10): • SS — Slave Select • MOSI — Master-Out Slave-In • MISO — Master-In Slave-Out • SPSCK — Serial Clock (maximum frequency 4.0 MHz) A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SS Read/Write, Address, Parity MOSI R/W A4 A3 A2 A1 A0 Data (Register write) P X D7 D6 System Status Register MISO S7 S6 S5 S4 S3 S2 D5 D4 D3 D2 D1 D0 D1 D0 Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 SPSCK Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data Figure 10. SPI Protocol During the inactive phase of SS, the new data transfer is prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance. MASTER ADDRESS BYTE • If R/ W = 1, the second byte of master contains no valid information, slave just transmits back register data. • If R/ W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS register on rising edge of SS. Parity P The parity bit is equal to “0” if the number of 1 bits is an even number contained within R/ W, A4 : A0. If the number of 1 bits is odd, P equals “1”. For example, if R/ W = 1, A4 : A0 = 00001, then P equals “0.” The parity bit is only evaluated during a write operation. Bit X A4 : A0 Not used. Contains the address of the desired register. Master Data Byte R/W Contains information about a read or a write operation. Table 2. Contains data to be written or no valid data during a read operation. 908E626 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 3. List of Registers Addr Register Name R/W $01 H-Bridge Output (HBOUT) R W $02 H-Bridge Control (HBCTL) W $03 System Control (SYSCTL) $04 Interrupt Mask (IMR) W $05 Interrupt Flag (IFR) W $06 Reset Mask (RMR) $07 Analog Multiplexer Configuration (ADMUX) $08 Reserved R R W R R R W R Bit 7 6 5 4 3 2 1 0 HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L OFC_EN CSA 0 0 0 CLS2 CLS1 CLS0 PSON SRS1 SRS0 0 0 0 0 0 0 LINIE HTIE LVIE HVIE OCIE 0 0 LINF HTF LVF HVF 0 0 0 0 0 0 0 0 0 SS3 0 0 0 0 0 0 0 0 0 0 0 TTEST 0 OCF 0 HVRE HTRE SS2 SS1 SS0 0 0 0 0 0 0 0 AWDRE 0 0 AWDF AWDR 0 0 0 0 HVDDON 0 HVDD_OCF 0 LVF HVF W R 0 W $09 Reserved R W $0a AWD Control (AWDCTL) $0b Power Output (POUT) $0c System Status (SYSSTAT) R W R 0 0 W R W 0 AWDRST 0 LINCL Slave Status Byte Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. Slave Data Byte Contains the contents of selected register. During a write operation it includes the register content prior to a write operation. SPI Register Overview Table 3 summarizes the SPI Register addresses and the bit names of each register. ANALOG DIE I / OS LIN Physical Layer The LIN bus terminal provides a physical layer for singlewire communication in automotive applications. The LIN HB_OCF HTF physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS TXD Terminal Table 4. Analog Multiplexer Configuration Register SS3 SS2 SS1 SS0 Channel 0 0 0 0 Current Recopy HB1 0 0 0 1 Current Recopy HB2 0 0 1 0 Current Recopy HB3 0 0 1 1 Current Recopy HB4 0 1 0 0 VSUP Prescaler 0 1 0 1 Temperature Sensor 0 1 1 0 0 1 1 1 1 0 0 0 Analog Multiplexer /ADOUT Terminal 1 0 0 1 The ADOUT terminal is the analog output interface to the ADC of the MCU (see Figure , page 2). An analog multiplexer is used to read six internal diagnostic analog voltages. 1 0 1 0 1 0 1 1 1 1 0 0 Current Recopy 1 1 0 1 1 1 1 0 1 1 1 1 The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure , page 2). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pullup current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V / 2.5 A or 5.0 V / 500 mA, respectively. (Refer to HalfBridge Current Recopy on page 25.) Not Used Power Output Register (POUT) Register Name and Address: POUT - $0b Temperature Sensor The 908E626 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. Analog Multiplexer Configuration Register (ADMUX) Register Name and Address: ADMUX - $07 Bit 7 6 5 4 0 0 0 0 Write Reset 0 0 0 0 Bit 7 6 0 0 Write Reset VSUP Prescaler Read Read 0 0 5 4 3 2 1 Bit 0 0 0 0 0 (14) (14) (14) (14) HVDDO N (14) 0 0 0 0 0 0 0 Notes 14. This bit must always be set to 0. HVDDON — HVDD On Bit This read/write bit enables HVDD output. Reset clears the HVDDON bit. • 1 = HVDD enabled. • 0 = HVDD disabled. 3 2 1 Bit 0 HALF-BRIDGES SS3 SS2 SS1 SS0 Outputs HB1 : HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high-side, or low-side configurations. 0 0 0 0 SS3, SS2, SS1, and SS0 — A / D Input Select Bits These read / write bits select the input to the ADC in the microcontroller according to Table 4, page 22. Reset clears SS3, SS2, SS1, and SS0 bits. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1: HB4 output features: • Short circuit (overcurrent) protection on high-side and low-side MOSFETs. • Current recopy feature (low side MOSFET). 908E626 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • Overtemperature protection. • Overvoltage and undervoltage protection. • Current limitation feature (low side MOSFET). VSUP Control On/Off High-Side Driver Status Charge Pump, Overtemperature Protection, Overcurrent Protection BEMF HBx On/Off Status Current Limit Low-Side Driver Current Recopy, Current Limitation, Overcurrent Protection GND Figure 11. Half-Bridge Push-Pull Output Driver Half-Bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high-side MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. Switching the high-side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low-side MOSFET on is blocked as long as the potential between gate and source of the high-side MOSFET did not fall below a certain threshold. Half-Bridge Output Register (HBOUT) Register Name and Address: HBOUT - $01 Read Write Reset Bit 7 6 5 4 3 2 1 Bit 0 HB4_ H HB4_ L HB3_ H HB3_ L HB2_ H HB2_ L HB1_ H HB1_ L 0 0 0 0 0 0 0 0 HBx_L — Low-Side On / Off Bits These read / write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits. • 1 = Low-side MOSFET turned on for half-bridge output x. • 0 = Low-side MOSFET turned off for half-bridge output x. HBx_H — High-Side On/Off Bits These read / write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. • 1 = High-side MOSFET turned on for half-bridge output x. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • 0 = High-side MOSFET turned on for half-bridge output x. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. HALF-BRIDGE CURRENT LIMITATION Functionality Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low-side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E626 offers five different current limits (refer to Table 5, page 27, for current limit values). The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 12). H-Bridge low-side MOSFET will be switched off if select current limit is reached. Coil Current H-Bridge low-side MOSFET will be turned on with each rising edge of the FGEN input. t (µs) Half-Bridge Low-Side Output t (µs) FGEN Input (MCU PWM Signal) t (µs) Minimum 50 µs Figure 12. Half-Bridge Current Limitation Offset Chopping If bit OFC_EN in the H-Bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low-side MOSFETs with the rising edge of the FGEN signal and HB3 and HB4 will switch on the low-side MOSFETs with the falling edge on the FGEN input. In step motor applications, this 908E626 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS feature allows the reduction of EMI due to a reduction of the di/dt (Figure ). Coil1 Current Coil2 Current FGEN Input (MCU PWM Signal) HB1 HB2 HB3 HB4 Coil1….. Coil2….. Current in VSUP Line Figure 13. Offset Chopping for Step Motor Control HALF-BRIDGE CURRENT RECOPY HALF-BRIDGE BEMF GENERATION Each low-side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. The BEMF output is set to “1” if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal) (see Figure 14, page 26). • CSA = 1: Low resolution selected (500 mA measurement range). • CSA = 0: High resolution selected (2.5 A measurement range). 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Coil Current Voltage on 1 1 BEMF Signal Figure 14. BEMF Signal Generation HALF-BRIDGE OVERTEMPERATURE PROTECTION The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the High-Temperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the outputs are automatically disabled. The overvoltage / undervoltage status flags are cleared (and the outputs re-enabled) by writing a logic [1] to the LVF / HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. HALF-BRIDGE OVERCURRENT PROTECTION Half-Bridge Control Register (HBCTL) The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high-side MOSFETs on all HB high-side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low-side MOSFETs are switched off automatically. In both cases, the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a logic [1] to the HB_OCF flag in the System Status Register or by reset. HALF-BRIDGE OVERVOLTAGE / UNDERVOLTAGE The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is Register Name and Address: HBCTL - $02 Read Write Reset Bit 7 6 OFC_EN CSA 0 0 5 4 3 0 0 0 0 0 0 2 1 Bit 0 CLS2 CLS1 CLS0 0 0 0 OFC_EN — H-Bridge Offset Chopping Enable Bit This read / write bit enables offset chopping. Reset clears the OFC_EN bit. • 1 = Offset chopping enabled. • 0 = Offset chopping disabled. 908E626 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS CSA — H-Bridges Current Sense Amplification Select Bit This read / write bit selects the current sense amplification of the H-Bridges. Reset clears the CSA bit. • 1 = Current sense amplification set for measuring 0.5 A. • 0 = Current sense amplification set for measuring 2.5 A. System Control Register (SYSCTL) Register Name and Address: SYSCTL - $03 Read CLS2 : CLS0 — H-Bridge Current Limitation Selection Bits Write These read / write bits select the current limitation value according to Table 5. Reset clears the CLS2 : CLS0 bits. Reset Table 5. H-Bridge Current Limitation Value Selection CLS2 CLS1 CLS0 Current Limit 0 0 0 0 0 1 0 1 0 0 1 1 55 mA (typ) 1 0 0 260 mA (typ) 1 0 1 370 mA (typ) 1 1 0 550 mA (typ) 1 1 1 No Limit 740 mA (typ) Bits Switchable VDD Outputs The HVDD terminal is a switchable VDD output terminal. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on / off with bit HVDDON in the Power Output Register. Low- or high-voltage conditions (LVI / HVI) have no influence on this circuitry. HVDD Overtemperature Protection Overtemperature protection is enabled if the hightemperature reset is enabled. 6 5 PSON SRS1 SRS0 0 0 0 4 3 2 1 0 0 0 0 Bit 0 0 (14) 0 0 0 0 0 Notes 15. This bit must always be set to 0. PSON — Power Stages On Bit This read / write bit enables the power stages (half-bridges, LIN transmitter and HVDD output). Reset clears the PSON bit. • 1 = Power stages enabled. • 0 = Power stages disabled. SRS0 : SRS1 — LIN Slew Rate Selection Bits These read / write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 6. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Table 6. LIN Slew Rate Selection Bits SRS1 SRS0 LIN Slew Rate 0 0 Initial Slew Rate (20 kBaud) 0 1 Slow Slew Rate (10 kBaud) 1 0 High Speed II (8 x) 1 1 High Speed I (4 x) System Status Register (SYSSTAT) Register Name and Address: SYSSTAT - $0c HVDD Overcurrent Protection The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set. Bit 7 Bit 7 Read Write Reset 6 LINCL 0 0 0 5 4 HVDD _OCF 0 0 0 3 2 LVF HVF 0 0 1 HB_ OCF 0 Bit 0 HTF 0 LINCL — LIN Current Limitation Bit This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. • 1 = Transmitter operating in current limitation region. • 0 = Transmitter not operating in current limitation region. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HVDD_OCF — HVDD Output Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the HVDD terminal. Clear HVDD_OCF and enable the output by writing a logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect. • 1 = Overcurrent condition on HVDD has occurred. • 0 = No overcurrent condition on HVDD has occurred. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. Autonomous Watchdog Control Register (AWDCTL) LVF — Low-Voltage Bit This read only bit is a copy of the LVF bit in the Interrupt Flag Register. • 1 = Low-voltage condition has occurred. • 0 = No low-voltage condition has occurred. Register Name and Address: AWDCTL - $0a Read Bit 7 6 5 0 0 0 Write AWDRST 4 3 AWDRE 0 0 (14) 0 0 HVF — High-Voltage Sensor Bit Reset This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. • 1 = High-voltage condition has occurred. • 0 = No high-voltage condition has occurred. Notes 16. This bit must always be set to 0. HB_OCF — H-Bridge Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect. • 1 = Overcurrent condition on H-Bridges has occurred. • 0 = No overcurrent condition on H-Bridges has occurred. HTF — Overtemperature Status Bit This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. • 1 = Overtemperature condition has occurred. • 0 = No overtemperature condition has occurred. AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module allows to protect the CPU against code runaways. The AWD is enabled if AWDRE in the AWDCTL Register is set. If this bit is cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. 0 0 0 2 1 Bit 0 (14) 0 AWDR 0 0 0 AWDRST — Autonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. • 1 = Reset AWD and restart timeout period. • 0 = No effect. AWDRE — Autonomous Watchdog Reset Enable Bit This read / write bit enables resets on AWD time-outs. A reset on the RST_A is asserted when the Autonomous Watchdog has reached the timeout and the Autonomous Watchdog is enabled. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. • 1 = Autonomous watchdog enabled. • 0 = Autonomous watchdog disabled. AWDR — Autonomous Watchdog Rate Bit This read / write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. • 1 = Fast rate selected (10 ms). • 0 = Slow rate selected (20 ms). VOLTAGE REGULATOR The 908E626 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. 908E626 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E626, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: • 0xFD80: 0xFDDF Trim and Calibration Values • 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependancies a ICG trim values is located at adress $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at adress $38 of the MCU. Important The value has to be copied after every reset. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 29 TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E626 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12V supply voltage some additional items have to be considered: • nominal 12V rather than 5V or 3V supply • high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principially possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board and second after the IC is soldered onto the pcb board. Chip level programming On Chip level the easiest way is to only power the MCU with +5V (see Figure 15) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:3]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well descripted in the MC68HC908EY16 datasheet - section development support. VSUP[1:3] VDD GND[1:2] VSS +5V VREFH VDDA RST EVDD RST_A +5V 1 1µF + 4 C1- GND C2+ V+ + 5 RS232 DB-9 VCC + 3 1µF C1+ 100nF VTST 16 C2- MAX232 V- 7 T2OUT 3 8 R2IN 1µF + 2 9.8304MHz CLOCK 6 +5V + CLK +5V PTB4/AD4 T2IN 10 6 10k 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 10k PTC4/OSC1 1µF 74HC125 5 VSSA EVSS 15 R2OUT 9 MM908E626 IRQ_A 1µF 74HC125 2 4.7µF VREFL IRQ 1 Figure 15. Normal Monitor Mode Circuit (MCU only) Of course its also possible to supply the whole system with Vsup (12V) instead as descibted in Figure 16, page 31. PCB level programming If the IC is soldered onto the pcb board its typically not possible to seperately power the MCU with +5V, the whole 908E626 30 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION system has to be powered up providing VSUP (see Figure 16). VDD VSUP 47µF + 100nF VSUP[1:3] VDD GND[1:2] VSS VREFH VDDA RST EVDD RST_A VDD 1 1µF VCC 16 + + 3 4 1µF C1+ 100nF VTST GND C1C2+ V+ + 5 RS232 DB-9 V- MAX232 C2- IRQ_A 1µF 3 8 R2IN 1µF 9.8304MHz CLOCK 6 VDD CLK 10k PTC4/OSC1 PTB4/AD4 1µF T2IN 10 6 10k DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 VDD 10k 5 74HC125 R2OUT 9 VSSA + 2 74HC125 7 T2OUT MM908E626 EVSS 15 + 2 4.7µF VREFL IRQ 1 5 Figure 16. Normal Monitor Mode Circuit Table 7 summarizes the possible configurations and the necessary setups. Table 7. Monitor Mode Signal Requirements and Options Mode IRQ RST Normal Monitor Forced Monitor VTST Reset Vector VDD X VDD $FFFF (blank) VDD Serial Communication Mode Selection PTA0 PTA1 PTB3 PTB4 1 0 0 1 1 0 X VDD VDD not $FFFF (not blank) X X X COP OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6MHz Nominal 6300 ON enabled enabled — Nominal 1.6MHz Nominal 6300 X GND User Communication Speed Normal Request Baud Bus Timeout External Clock Frequency Rate ICG X Notes 1. PTA0 must have a pullup resistor to VDD in monitor mode 2. 3. 4. 5. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5V ≤ VTST ≤ VDD + 4.5V 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 31 TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale website www.freescale.com. MCU digital supply terminals (EVDD and EVSS) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. VSUP terminals (VSUP1:VSUP3) Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behaviour. MCU analog supply terminals (VREFH, VDDA and VREFL, VSSA) LIN terminal To avoid noise on the analog supply terminals its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via seperate traces and connected to the voltage regulator output. Figure 17 and Figure 18 show the recommendations on schematics and layout level and Table 8 incidates recommended external components and layout considerations. For DPI (Direct Power Injection) and ESD (Electro Static Discharge) its recommended to place a high-quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrit in the LIN line will suppress some of the noise induced. Voltage regulator output terminals (VDD and AGND) Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VDD VSUP2 VSS VSUP3 VREFH VDDA L1 LIN LIN EVDD V1 C5 C3 MM908E625 C4 EVSS VSSA GND1 VREFL GND2 Figure 17. EMC/EMI recommendations 908E626 32 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION 1 54 2 53 3 52 4 51 5 50 49 7 VREFH 48 8 VDDA 47 9 EVDD 46 10 EVSS 45 11 VSSA 44 12 VREFL 43 13 14 42 NC 908E626 15 41 VSS 17 VDD 36 19 C5 V1 20 LIN 21 NC 22 NC 35 34 NC 24 VSUP1 VSUP3 31 25 GND1 GND2 30 29 26 27 C1 33 32 23 GND C4 38 37 18 L1 40 39 16 LIN C3 6 VSUP2 28 C2 VBAT Figure 18. PCB Layout Recommendations . Table 8. Component Value Recommendation Component Recommended Value(1) C1 Bulk Capacitor C2 100nF, SMD Ceramic, Low ESR Close (<5mm) to VSUP1, VSUP2 terminals with good ground return C3 100nF, SMD Ceramic, Low ESR Close (<3mm) to digital supply terminals (EVDD, EVSS) with good ground return. Comments / Signal routing The positive analog (VREFH, VDDA) and the digital (EVDD) supply should be connected right at the C3. C4 4,7uF, SMD Ceramic, Low ESR Bulk Capacitor C5 180pF, SMD Ceramic, Low ESR Close (<5mm) to LIN terminal. Total Capacitance on LIN has to be below 220pF. (Ctotal = CLIN-Terminal + C5 + CVaristor ~ 10pF + 180pF + 15pF) V1(2) L1 (2) Varistor Type TDK AVR-M1608C270MBAAB Optional (close to LIN connector) SMD Ferrite Bead Type TDK MMZ2012Y202B Optional, (close to LIN connector) Notes 1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. 2. Components are recommended to improve EMC and ESD performance. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 33 TYPICAL APPLICATIONS PACKAGING DIMENSIONS PACKAGING DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL105910. 10.3 5 7.6 7.4 9 C B NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY. 2.65 2.35 52X 1 54 0.65 PIN 1 INDEX 4 9 B 27 18.0 17.8 CL B 28 A 5.15 54X 2X 27 TIPS 0.3 SEATING PLANE 0.10 A A B C A R0.08 MIN C C 0˚MIN 0.25 GAUGE PLANE (1.43) A 8˚ 0˚ 10.9 9.7 0.1 0.0 0.9 0.5 SECTION B-B 0.30 A B C (0.29) 5.3 4.8 0.30 A B C DWB SUFFIX 54-TERMINAL PLASTIC PACKAGE 98Axxxxxxxx ISSUE B 0.30 0.25 BASE METAL (0.25) 0.38 0.22 6 0.13 M PLATING A B C 8 SECTION A-A ROTATED 90˚ CLOCKWISE VIEW C-C 908E626 34 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) ADDITIONAL DOCUMENTATION 908E626 THERMAL ADDENDUM (REV 1.0) Introduction This thermal addendum ia provided as a supplement to the MM908E626 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. 54-TERMINAL SOICW-EP Package and Thermal Considerations This MM908E626 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. TJ1 TJ2 = RθJA11 RθJA12 RθJA21 RθJA22 . DWB SUFFIX 98ARL105910 54-TERMINAL SOICW-EP Note For package dimensions, refer to the 908E626 device datasheet. P1 P2 The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 9. Thermal Performance Comparison Thermal Resistance m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 RθJAmn (1)(2) 23 20 24 RθJBmn (2)(3) 9.0 6.0 10 RθJAmn (1)(4) 52 47 52 1.0 0 2.0 RθJCmn (5) 1.0 1 = Power Chip, 2 = Logic Chip [°C/W] Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad. 1.0 0.2 0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane 54 Terminal SOIC-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Figure 19. Thermal Land Pattern for Direct Thermal Attachment Per JEDEC JESD51-5Thermal Test Board 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 35 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF RST_A IRQ_A SS LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Exposed Pad 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC 908E626 Terminal Connections 54-Terminal SOICW-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Figure 20. Thermal Test Board Device on Thermal Test Board Material: Outline: Area A: Ambient Conditions: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 10. Thermal Resistance Performance Thermal Resistance RθJAmn RθJSmn Area A (mm2) 1 = Power Chip, 2 = Logic Chip (°C/W) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 53 48 53 300 39 34 38 600 35 30 34 0 21 16 20 300 15 11 15 600 14 9.0 13 RθJA is the thermal resistance between die junction and ambient air. RθJSmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 908E626 36 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) Thermal Resistance [ºC/W] 60 50 40 30 20 x 10 RθJA11 RθJA22 RθJA12 = RθJA21 0 0 300 600 Heat spreading area A [mm²] Figure 21. Device on Thermal Test Board RθJA Thermal Resistance [ºC/W] 100 10 1 x 0.1 1.00E-03 1.00E-02 RθJA11 RθJA22 RθJA12 = RθJA21 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 22. Transient Thermal Resistance RθJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2) 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 37 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. 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