FREESCALE MPC5553MVZ80

Freescale Semiconductor
Data Sheet: Product Preview
Document Number: MPC5553
Rev. 2, 03/2007
MPC5553
Microcontroller Data Sheet
by: Microcontroller Division
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5553
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 6
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Electromagnetic Interference Characteristics . . . . . 9
3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10
3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 11
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 46
4
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 56
Overview
The MPC5553 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architecture™ embedded technology. This
family of parts contains many new features coupled with
high performance CMOS technology to provide
substantial reduction of cost per feature and significant
performance improvement over the MPC500 family.
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (with floating point library) with
the original Power PC™ user instruction set architecture
(UISA). The embedded architecture has enhancements
that improve the performance in embedded applications.
This core also has additional instructions, including
digital signal processing (DSP) instructions, beyond the
original Power PC instruction set. This family of parts
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Overview
contains many new features coupled with high performance CMOS technology to provide significant
performance improvement over the MPC565.
The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the
8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM
and 1.5 Mbyte internal Flash memory. The internal SRAM and flash memory can hold instructions and
data. The external bus interface has been designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5500 family are performed by an enhanced time
processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been
enhanced over the TPU by providing 24-bit timers, double-action hardware channels, variable number of
parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The
eTPU can be programmed using a high-level programming language.
The less complex timer functions of the MPC5500 family are performed by the enhanced modular
input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action,
double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control
capabilities include edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIO) signals.
The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter
(eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides
multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal
multiplexing.
The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps
Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access
controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or
100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which
uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to
connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and
DMA support.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
2
Freescale Semiconductor
Ordering Information
2
Ordering Information
M PC 5553 M ZP 80 R2
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = –40° C to 125° C
Package Identifier
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
VF = 208MAPBGA SnPb
VM = 208MAPBGA Pb-free
ZQ = 324PBGA SnPb
VZ = 324PBGA Pb-free
Operating Frequency
80 = 80 MHz
112 = 112 MHz
132 = 132 MHz
Tape and Reel Status
R2 = Tape and seel
(blank) = Trays
Qualification Status
P = Pre qualification
M = Full spec qualified
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5500 Family Part Number Example
Table 1. Orderable Part Numbers
Speed (MHz)
Freescale Part
Number1
Package Description
Nominal
Max3 (fMAX)
132
132
112
114
MPC5553MVR80
80
82
MPC5553MVZ132
132
132
112
114
MPC5553MVZ80
80
82
MPC5553MVM132
132
132
112
114
MPC5553MVM80
80
82
MPC5553MZP132
132
132
112
114
MPC5553MZP80
80
82
MPC5553MZQ132
132
132
112
114
80
82
MPC5553MVR132
MPC5553MVR112
MPC5553MVZ112
MPC5553MVM112
MPC5553MZP112
MPC5553MZQ112
MPC5553MZQ80
Operating Temperature2
MPC5553 Lead-free 416 package
MPC5553 Lead-free 324 package
MPC5553 Lead-free 208 package
MPC5553 Lead 416 package
MPC5553 Lead 324 package
Min (TL)
Max (TH)
–40° C
125° C
–40° C
125° C
–40° C
125° C
–40° C
125° C
–40° C
125° C
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
3
Electrical Characteristics
Table 1. Orderable Part Numbers (continued)
Operating Temperature2
Speed (MHz)
Freescale Part Number1
Package Description
MPC5553MVF132
MPC5553MVF112
MPC5553 Lead 208 package
MPC5553MVF80
Nominal
Max3 (fMAX)
132
132
112
114
80
82
Min (TL)
Max (TH)
–40° C
125° C
1
All devices are PPC5553, rather than MPC5553, until the product qualifications. Not all configurations are available in the PPC
parts.
2
The lowest operating temperature is referenced by TL; the highest operating temperature is referenced by TH.
3
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including any frequency modulation.
80 MHz parts allow for 80 MHz + 2% modulation. However, 132 MHz devices allow 128 MHz plus two percent frequency
modulation only.
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Ratings
Table 2. Absolute Maximum Ratings1
Spec
Characteristic
3
Symbol
Min
Max2
Unit
VDD
–0.3
1.7
V
1
1.5 V core supply voltage
2
Flash program/erase voltage
VPP
–0.3
6.5
V
3
Flash core voltage
VDDF
–0.3
1.7
V
4
Flash read voltage
VFLASH
–0.3
4.6
V
5
SRAM standby voltage
VSTBY
–0.3
1.7
V
6
Clock synthesizer voltage
VDDSYN
–0.3
4.6
V
7
3.3 V I/O buffer voltage
VDD33
–0.3
4.6
V
8
Voltage regulator control input voltage
VRC33
–0.3
4.6
V
9
Analog supply voltage (reference to VSSA)
VDDA
–0.3
5.5
V
VDDE
–0.3
4.6
V
VDDEH
–0.3
6.5
V
–1.06
–1.06
6.57
4.68
V
10
11
12
I/O supply voltage (fast I/O pads)
4
I/O supply voltage (slow and medium I/O pads)
4
voltage5
DC input
VDDEH powered I/O pads
VDDE powered I/O pads
VIN
13
Analog reference high voltage (reference to VRL)
VRH
–0.3
5.5
V
14
VSS differential voltage
VSS – VSSA
–0.1
0.1
V
15
VDD differential voltage
VDD – VDDA
–VDDA
VDD
V
16
VREF differential voltage
VRH – VRL
–0.3
5.5
V
MPC5553 Microcontroller Data Sheet, Rev. 2.0
4
Freescale Semiconductor
Electrical Characteristics
Table 2. Absolute Maximum Ratings1 (continued)
Spec
Characteristic
Symbol
Min
Max2
Unit
17
VRH to VDDA differential voltage
VRH – VDDA
–5.5
5.5
V
18
VRL to VSSA differential voltage
VRL – VSSA
–0.3
0.3
V
19
VDDEH to VDDA differential voltage
VDDEH – VDDA
–VDDA
VDDEH
V
20
VDDF to VDD differential voltage
VDDF – VDD
–0.3
0.3
V
21
This spec has been moved to Table 9, spec 43a.
22
VSSSYN to VSS differential voltage
VSSSYN – VSS
–0.1
0.1
V
23
VRCVSS to VSS differential voltage
VRCVSS – VSS
–0.1
0.1
V
9
24
Maximum DC digital input current
(per pin, applies to all digital pins)5
IMAXD
–2
2
mA
25
Maximum DC analog input current 10
(per pin, applies to all analog pins)
IMAXA
–3
3
mA
26
Maximum operating temperature range 11
Die junction temperature
TJ
TL
150.0
oC
27
Storage temperature range
TSTG
–55.0
150.0
oC
28
Maximum solder temperature 12
TSDR
—
260.0
oC
29
Moisture sensitivity level 13
MSL
—
3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima can affect device reliability or cause
permanent damage to the device.
2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have
not yet been determined.
3 1.5 V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC.
4 All functional non-supply I/O pins are clamped to V
SS and VDDE, or VDDEH.
5 AC signal overshoot and undershoot of up to +/– 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
6 Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
current greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state.
7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
8 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
9 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
10
Total injection current for all analog input pins must not exceed 15 mA.
11 Lifetime operation at these specification limits is not guaranteed.
12 Solder profile per CDF-AEC-Q100.
13
Moisture sensitivity per JEDEC test method A112.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
5
Electrical Characteristics
3.2
Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer device.
Table 3. Thermal Characteristics
Package
Spec
1
4
5
6
324
PBGA
416
PBGA
Unit
RθJA
41
30
29
°C/W
RθJA
25
21
21
°C/W
3
Junction to ambient (@200 ft./min., one-layer board)
RθJMA
33
24
23
°C/W
4
Junction to ambient (@200 ft./min., four-layer board 2s2p)
RθJMA
22
17
18
°C/W
RθJB
15
12
13
°C/W
RθJC
7
8
9
°C/W
ΨJT
2
2
2
°C/W
7
3
1, 3
208
MAPBGA
Junction to ambient
, natural convection
(four-layer board 2s2p)
6
2
Junction to ambient 1, 2, natural convection (one-layer board)
Symbol
2
5
1
MPC5553 Thermal Characteristic
Junction to board
Junction to case
4
(four-layer board 2s2p)
5
Junction to package top
6,
natural convection
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature for the package (oC)
RθJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
MPC5553 Microcontroller Data Sheet, Rev. 2.0
6
Freescale Semiconductor
Electrical Characteristics
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
• One oz (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RθJB × PD)
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RθJB = junction-to-board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (oC/W)
RθJC = junction-to-case thermal resistance (oC/W)
RθCA = case-to-ambient thermal resistance (oC/W)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
7
Electrical Characteristics
RθJC is device related and is not affected by other factors. The thermal environment can be controlled to
change the case-to-ambient thermal resistance, RθCA. For example, change the air flow around the device,
add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to the heat sink to ambient. For
most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TT = thermocouple temperature on top of the package (oC)
ΨJT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. A small amount of epoxy is placed on the
thermocouple junction and approximately 1 mm of wire extending from the junction. The thermocouple
wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of
the thermocouple wire.
References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA., 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
• 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
• 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
• 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego,
1999, pp. 212–220.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
8
Freescale Semiconductor
Electrical Characteristics
3.3
Package
The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering
Information.”
Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
3.4
EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications1
Spec
Characteristic
Minimum
Typical
Maximum
Unit
0.15
—
1000
MHz
1
Scan range
2
Operating frequency
—
—
132
MHz
3
VDD operating voltages
—
1.5
—
V
4
VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages
—
3.3
—
V
5
VPP, VDDEH, VDDA operating voltages
—
5.0
—
V
—
142
dBuV
6
Maximum amplitude
—
323
7
Operating temperature
—
—
oC
25
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
2 Measured with single-chip EMI program.
3 Measured with expanded EMI program.
3.5
ESD Characteristics
Table 5. ESD Ratings1, 2
Characteristic
Symbol
Value
Unit
2000
V
R1
1500
Ω
C
100
pF
ESD for Human Body Model (HBM)
HBM circuit description
500 (all pins)
ESD for Field Induced Charge Model (FDCM)
750 (corner pins)
V
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)
—
—
1
1
—
—
Interval of pulses
—
1
second
1
2
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
Device failure is defined as: if after exposure to ESD pulses, the device no longer meets the device specification requirements.
Complete DC parametric and functional testing will be performed per applicable device specification at room temperature
followed by hot temperature, unless specified otherwise in the device specification.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
9
Electrical Characteristics
3.6
Voltage Regulator Controller (VRC) and
Power-On Reset (POR) Electrical Specifications
Table 6. VRC/POR Electrical Specifications
Spec
Characteristic
3
4
5
6
7
8
Max
Units
1.5 V (VDD) POR negated (ramp up)
1.5 V (VDD) POR asserted (ramp down)
V_POR15
1.1
1.1
1.35
1.35
V
2
3.3 V (VDDSYN) POR negated (ramp up)
3.3 V (VDDSYN) POR asserted (ramp down)
V_POR33
2.0
2.0
2.85
2.85
V
3
RESET pin supply (VDDEH6) POR negated (ramp up)1
RESET pin supply (VDDEH6) POR asserted (ramp down)1
V_POR5
2.0
2.0
2.85
2.85
V
4
VRC33 voltage before the regulator controller allows the pass
transistor to start turning on
V_TRANS_START
1.0
2.0
V
5
VRC33 voltage when the regulator controller allows the pass
transistor to completely turn on2, 3
V_TRANS_ON
2.0
2.85
V
6
VRC33 voltage greater than the voltage at which the VRC
keeps the 1.5 V supply in regulation4, 5
V_VRC33REG
3.0
—
V
7
Current can be sourced by VRCCTL
I_VRCCTL6
mA
– 40o C
11.0
—
mA
25o
C
9.0
—
mA
150o C (Tj)
7.5
—
mA
—
1.0
V
—
50
V/ms
– 40o C
55.09
—
—
25o C
58.09
—
—
500
—
8
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and
VDDEH6 reach the V_POR33 and V_POR5 minimums
respectively.
9
Absolute value of slew rate on power supply pins
Required gain:
IDD / I_VRCCTL (@VDD = 1.35 V, fsys = fMAX)5, 7
150o
2
Min
1
10
1
Symbol
VDD33_LAG
BETA8
9
C (Tj)
70.0
VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to V_POR5.
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the
pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 Ω). VRCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF
(nominal) bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors
consisting of eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the VDD supply signals.
I_VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, V_VRCCTL = 2.2 V.
Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
BETA is measured on a per-part basis and is calculated as (IDD ÷ I_VRCCTL), and represents the worst-case external
transistor BETA.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
10
Freescale Semiconductor
Electrical Characteristics
9
3.7
Preliminary value. Final specification pending characterization.
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is nit used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
VDD33.”
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current
consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the
1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR
negates again. All oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between VRC33 and VDDSYN is required for the VRC to operate within specification.
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which
supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 7. Power Sequence Pin Status for Fast Pads
Pin Status for Fast Pad Output Driver
VDDE
VDD33
VDD
POR
pad_fc (fast)
Low
—
—
Asserted
Low
VDDE
Low
Low
Asserted
High
VDDE
Low
VDD
Asserted
High
VDDE
VDD33
Low
Asserted
High impedance (Hi-Z)
VDDE
VDD33
VDD
Asserted
Hi-Z
VDDE
VDD33
VDD
Negated
Functional
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
11
Electrical Characteristics
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
Table 8. Power Sequence Pin Status for Medium / Slow Pads
Pin Status for Medium and Slow Pad Output Driver
3.7.1
VDDEH
VDD
POR
pad_mh (medium) pad_sh (slow)
Low
—
Asserted
Low
VDDEH
Low
Asserted
High impedance (Hi-Z)
VDDEH
VDD
Asserted
Hi-Z
VDDEH
VDD
Negated
Functional
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Figure 2. Power-Up Sequence (VRC33 Grounded)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
12
Freescale Semiconductor
Electrical Characteristics
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence when VRC33 is grounded is that if VDD decreases to
less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the
VDD power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is
reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset
properly.
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications
Spec
Characteristic
Symbol
Min
Max
Unit
1
Core supply voltage (average DC RMS voltage)
VDD
1.35
1.65
V
2
I/O supply voltage (fast I/O)
VDDE
1.62
3.6
V
3
I/O supply voltage (slow / medium I/O)
VDDEH
3.0
5.25
V
4
3.3 V I/O buffer voltage
VDD33
3.0
3.6
V
5
Voltage regulator control input voltage
VRC33
3.0
3.6
V
6
Analog supply
voltage1
VDDA
4.5
5.25
V
8
Flash programming voltage2
VPP
4.5
5.25
V
9
Flash read voltage
VFLASH
3.0
3.6
V
10
SRAM standby voltage3
VSTBY
0.8
1.2
V
11
Clock synthesizer operating voltage
VDDSYN
3.0
3.6
V
12
Fast I/O input high voltage
VIH_F
0.65 × VDDE
VDDE + 0.3
V
13
Fast I/O input low voltage
VIL_F
VSS – 0.3
0.35 × VDDE
V
14
Medium / slow I/O input high voltage
VIH_S
0.65 × VDDEH VDDEH + 0.3
V
15
Medium / slow I/O input low voltage
VIL_S
0.35 × VDDEH
V
16
Fast I/O input hysteresis
VHYS_F
0.1 × VDDE
V
17
Medium / slow I/O input hysteresis
VHYS_S
0.1 × VDDEH
V
18
Analog input voltage
VINDC
VSSA – 0.3
VDDA + 0.3
V
19
Fast I/O output high voltage ( IOH_F = –2.0 mA )
VOH_F
0.8 × VDDE
—
V
20
Slow / medium I/O output high voltage ( IOH_S = –2.0 mA )
VOH_S
0.8 × VDDEH
—
V
21
Fast I/O output low voltage ( IOL_F = 2.0 mA )
VOL_F
—
0.2 × VDDE
V
22
Slow / medium I/O output low voltage ( IOL_S = 2.0 mA )
VOL_S
—
0.2 × VDDEH
V
23
4
—
—
—
—
10
20
30
50
pF
pF
pF
pF
Load capacitance (fast I/O)
DSC (SIU_PCR[8:9] ) = 0b00
DSC (SIU_PCR[8:9] ) = 0b01
DSC (SIU_PCR[8:9] ) = 0b10
DSC (SIU_PCR[8:9] ) = 0b11
CL
VSS – 0.3
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
13
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec
Characteristic
Symbol
Min
Max
Unit
24
Input capacitance (digital pins)
CIN
—
7
pF
25
Input capacitance (analog pins)
CIN_A
—
10
pF
26
Input capacitance
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[12]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
CIN_M
—
12
pF
IDD
IDD
IDD
IDD
—
—
—
—
5509
4509
6009
4909
mA
mA
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
4609
3809
5209
4209
mA
mA
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
3509
2909
4009
3309
mA
mA
mA
mA
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
20
30
50
μA
μA
μA
IDDSTBY @ 60o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
70
100
200
μA
μA
μA
IDDSTBY @ 150o C (Tj)
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
1200
1500
2000
μA
μA
μA
VDD3311
IDD33
—
2 + (values
derived from
procedure of
Footnote 11)
mA
VFLASH
IVFLASH
—
10
mA
VDDSYN
IDDSYN
—
15
mA
27a Operating current5 1.5 V supplies @ 132 MHz:
VDD (including VDDF max current)6, 7 @1.65 V typical use
VDD (including VDDF max current)6, 7 @1.35 V typical use
VDD (including VDDF max current) 7, 8 @1.65 V high use
VDD (including VDDF max current)7, [email protected] V high use
27b Operating current 51.5 V supplies @ 114 MHz:
VDD (including VDDF max current)6, [email protected] V typical use
VDD (including VDDF max current)6, [email protected] V typical use
VDD (including VDDF max current)7, 8 @1.65 V high use
VDD (including VDDF max current)7, 8 @1.35 V high use
27c Operating current5 1.5 V supplies @ 82 MHz:
VDD (including VDDF max current)6, 7 @1.65 V typical use
VDD (including VDDF max current)6, 7 @1.35 V typical use
VDD (including VDDF max current)7, 8 @1.65 V high use
VDD (including VDDF max current)7, 8 @1.35 V high use
27d Refer to Figure 3 for an interpolation of this data. 10
IDDSTBY @ 25o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
28
Operating current 3.3 V supplies @ 132 MHz
MPC5553 Microcontroller Data Sheet, Rev. 2.0
14
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec
29
Characteristic
31
Operating current VDDE12 supplies:
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
Max
Unit
IDDA
IREF
IPP
—
—
—
20.0
1.0
25.0
mA
mA
mA
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
Refer to
Footnote 12
mA
mA
mA
mA
mA
mA
mA
mA
mA
10
20
20
110
130
170
μA
μA
μA
10
20
20
100
130
170
μA
μA
μA
IACT_S
10
20
150
170
μA
μA
IINACT_D
– 2.5
2.5
μA
IIC
– 2.0
2.0
mA
IINACT_A
–150
150
nA
IINACT_AD
– 2.5
2.5
μA
VSS – VSSA
– 100
100
mV
VRL
VSSA – 0.1
VSSA + 0.1
V
VRL – VSSA
–100
100
mV
VRH
VDDA – 0.1
VDDA + 0.1
V
VRH – VRL
4.5
5.25
V
Fast I/O weak pullup current13
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
Fast I/O weak pulldown current13
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
32
Min
Operating current 5.0 V supplies
(12 MHz ADCLK):
VDDA (VDDA0 + VDDA1)
Analog reference supply current (VRH, VRL)
VPP
30
Symbol
Slow / medium I/O weak pullup/down current14
3.0–3.6 V
4.5–5.5 V
33
I/O input leakage current15
34
DC injection current (per pin)
35
Analog input current, channel off 16
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15])
IACT_F
36
VSS differential voltage17
37
Analog reference low voltage
38
VRL differential voltage
39
Analog reference high voltage
40
VREF differential voltage
41
VSSSYN to VSS differential voltage
VSSSYN – VSS
–50
50
mV
42
VRCVSS to VSS differential voltage
VRCVSS – VSS
–50
50
mV
43
VDDF to VDD differential voltage2
VDDF – VDD
–100
100
mV
43a VRC33 to VDDSYN differential voltage
VRC33 – VDDSYN
–0.1
18
0.1
V
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
15
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec
Characteristic
44
Analog input differential signal range
(with common mode 2.5 V)
45
Operating temperature range, ambient (packaged)
46
Slew rate on power-supply pins
Symbol
Min
Max
Unit
VIDIFF
– 2.5
2.5
V
TA = (TL to TH)
TL
TH
οC
—
—
50
V/ms
1
| VDDA0 – VDDA1 | must be < 0.1 V.
VPP can drop to 3.0 V during read operations.
3
During standby operation, if standby operation is not required, connect VSTBY to ground.
4
Applies to CLKOUT, external bus pins, and Nexus pins.
5
Maximum average RMS DC current.
6
Average current measured on Automotive benchmark.
7 Peak currents can be higher on specialized code.
8
High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously
from SRAM to SRAM. Higher currents are possible if an idle loop that crosses cache lines is run from cache. Design and write
code to avoid this condition.
9 Preliminary. Final specification pending characterization.
10 Figure 3 shows an illustration of the IDD
STBY values interpolated for these temperature values.
11 Power requirements for the V
supply
depend on the frequency of operation and load of all I/O pins, and the voltages on
DD33
the I/O segments. Refer to Table 11 for values to calculate power dissipation for specific operation.
12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular
I/O segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific
operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the
segment.
13 Absolute value of current, measured at V and V .
IL
IH
14 Absolute value of current, measured at V and V .
IL
IH
15 Weak pullup/down inactive. Measured at V
=
3.6
V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
DDE
16 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 oC to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
17 V
SSA refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
18 Up to 0.6 V during power up and power down.
2
MPC5553 Microcontroller Data Sheet, Rev. 2.0
16
Freescale Semiconductor
Electrical Characteristics
Figure 3 shows an approximate interpolation of the ISTBY worst-case specification to help estimate the
values at different voltages and temperatures. The vertical lines inside the graph show the actual
specifications listed in Table 9. Refer to the IDDSTBY specifications (27d) in Table 9 for more information.
ISTBY Related to Junction Temperature
2000
1900
1800
1700
1600
1500
1400
µA
1300
1200
1100
1000
0.8V
1.0V
900
1.2V
800
700
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
Temperature (C)
Figure 3. ISTBY Worst-case Specifications
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a particular segment. The output pin current
can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
17
Electrical Characteristics
Table 10. I/O Pad Average DC Current1
Spec
Pad Type
Symbol
Voltage (V)
Drive Select /
Slew Rate
Control Setting
Current (mA)
25
50
5.25
11
8.0
2
10
50
5.25
01
3.2
Slow
IDRV_SH
2
50
5.25
00
0.7
2
200
5.25
00
2.4
5
50
50
5.25
11
17.3
6
20
50
5.25
01
6.5
4
7
Medium
IDRV_MH
3.33
50
5.25
00
1.1
8
3.33
200
5.25
00
3.9
9
66
10
3.6
00
2.8
10
66
20
3.6
01
5.2
11
66
30
3.6
10
8.5
12
66
50
3.6
11
11.0
13
66
10
1.98
00
1.6
14
66
20
1.98
01
2.9
15
66
30
1.98
10
4.2
16
66
50
1.98
11
6.7
17
56
10
3.6
00
2.4
18
56
20
3.6
01
4.4
19
56
30
3.6
10
7.2
20
56
50
3.6
11
9.3
21
2
Load2 (pF)
1
3
1
Frequency
(MHz)
Fast
IDRV_FC
56
10
1.98
00
1.3
22
56
20
1.98
01
2.5
23
56
30
1.98
10
3.5
24
56
50
1.98
11
5.7
25
40
10
3.6
00
1.7
26
40
20
3.6
01
3.1
27
40
30
3.6
10
5.1
28
40
50
3.6
11
6.6
29
40
10
1.98
00
1.0
30
40
20
1.98
01
1.8
31
40
30
1.98
10
2.5
32
40
50
1.98
11
4.0
These values are estimates from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
18
Freescale Semiconductor
Electrical Characteristics
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The
power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output
pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast
(pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage,
frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. VDD33 Pad Average DC Current1
Spec
Pad Type
Symbol
Frequency
(MHz)
Load2
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
Current
(mA)
Inputs
1
Slow
I33_SH
66
0.5
3.6
5.5
NA
0.003
2
Medium
I33_MH
66
0.5
3.6
5.5
NA
0.003
3
66
10
3.6
3.6
00
0.35
4
66
20
3.6
3.6
01
0.53
5
66
30
3.6
3.6
10
0.62
Outputs
6
66
50
3.6
3.6
11
0.79
7
66
10
3.6
1.98
00
0.35
8
66
20
3.6
1.98
01
0.44
9
66
30
3.6
1.98
10
0.53
10
66
50
3.6
1.98
11
0.7
11
56
10
3.6
3.6
00
0.30
12
56
20
3.6
3.6
01
0.45
13
56
30
3.6
3.6
10
0.52
14
56
50
3.6
3.6
11
0.67
56
10
3.6
1.98
00
0.30
16
56
20
3.6
1.98
01
0.37
17
56
30
3.6
1.98
10
0.45
18
56
50
3.6
1.98
11
0.60
19
40
10
3.6
3.6
00
0.21
20
40
20
3.6
3.6
01
0.31
21
40
30
3.6
3.6
10
0.37
15
Fast
I33_FC
22
40
50
3.6
3.6
11
0.48
23
40
10
3.6
1.98
00
0.21
24
40
20
3.6
1.98
01
0.27
25
40
30
3.6
1.98
10
0.32
26
40
50
3.6
1.98
11
0.42
1
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
2
All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
19
Electrical Characteristics
3.9
Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
fref_crystal
fref_ext
fref_1:1
8
8
24
20
20
fsys ÷ 2
Unit
1
PLL reference frequency range:
Crystal reference
External reference
Dual controller (1:1 mode)
MHz
2
System frequency 1
fsys
fICO(MIN) ÷ 2RFD
fMAX 2
MHz
3
System clock period
tCYC
—
1 ÷ fsys
ns
4
Loss of reference frequency 3
fLOR
100
1000
kHz
5
Self clocked mode (SCM) frequency 4
fSCM
7.4
17.5
MHz
EXTAL input high voltage
crystal mode 5
VIHEXT
VXTAL + 0.4 V
—
V
All other modes (dual controller (1:1),
bypass, external reference)
VIHEXT
[(VDDE5 ÷ 2) + 0.4 V]
—
V
EXTAL input low voltage
crystal mode 6
VILEXT
—
VXTAL – 0.4 V
V
VILEXT
—
[(VDDE5 ÷ 2) – 0.4 V]
V
IXTAL
0.8
3
mA
6
7
All other modes (dual controller (1:1),
bypass, external reference)
8
XTAL current 7
9
Total on-chip stray capacitance on XTAL
CS_XTAL
—
1.5
pF
10
Total on-chip stray capacitance on EXTAL
CS_EXTAL
—
1.5
pF
11
Crystal manufacturer’s recommended
capacitive load
CL
Refer to crystal
specification
Refer to crystal
specification
pF
12
Discrete load capacitance to connect to
EXTAL
CL_EXTAL
—
(2 × CL) – CS_EXTAL
– CPCB_EXTAL8
pF
13
Discrete load capacitance to connect to
XTAL
CL_XTAL
—
(2 × CL) – CS_XTAL –
CPCB_XTAL8
pF
14
PLL lock time9
tlpll
—
750
μs
15
Dual controller (1:1) clock skew
(between CLKOUT and EXTAL) 10, 11
tskew
–2
2
ns
16
Duty cycle of reference
tDC
40
60
%
17
Frequency un-LOCK range
fUL
– 4.0
4.0
% fSYS
18
Frequency LOCK range
fLCK
– 2.0
2.0
% fSYS
MPC5553 Microcontroller Data Sheet, Rev. 2.0
20
Freescale Semiconductor
Electrical Characteristics
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
—
5.0
%
fCLKOUT
—
0.01
CLKOUT period jitter,12, 13
measured at fSYS maximum
peak-to-peak jitter
(clock edge to clock edge)
Long term jitter
(averaged over 2 ms interval)
CJITTER
20
Frequency modulation range limit 14
(do not exceed fsys maximum)
CMOD
0.8
2.4
%fSYS
21
ICO frequency
fico = [ fref × (MFD + 4) ] ÷ (PREDIV + 1)15
fico
48
fsys
MHz
22
Predivider output frequency (to PLL)
fPREDIV
4
fMAX
MHz
19
1
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (refer to Table 1).
3 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into
self-clocked mode.
4 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
5 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
6 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal – Vextal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
7 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
10 PLL is operating in 1:1 PLL mode.
11 V
DDE = 3.0–3.6 V
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f .
sys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
13
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
14 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
15 f
RFD).
sys = fico ÷ (2
2
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
21
Electrical Characteristics
3.10
eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
FADCLK
1
12
MHz
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
1
ADC clock (ADCLK) frequency1
Conversion cycles
Differential
Single ended
CC
2
3
Stop mode recovery time2
ADCLK
cycles
TSR
10
—
μs
4
Resolution
3
—
1.25
—
mV
5
INL: 6 MHz ADC clock
INL6
–4
4
Counts3
6
INL: 12 MHz ADC clock
INL12
–8
7
8
9
10
DNL: 6 MHz ADC clock
DNL: 12 MHz ADC clock
Offset error with calibration
Full-scale gain error with calibration
current 7, 8, 9, 10
8
Counts
DNL6
–3
4
34
Counts
DNL12
–6 4
64
Counts
OFFWC
–4 5
4
5
Counts
GAINWC
–8 6
86
Counts
IINJ
–1
1
mA
11
Disruptive input injection
12
Incremental error due to injection current. All channels have
same 10 kΩ < Rs <100 kΩ
Channel under test has Rs = 10 kΩ,
IINJ = IINJMAX, IINJMIN
EINJ
–4
4
Counts
13
Total Unadjusted Error for single ended conversions with
calibration11, 12, 13, 14, 15
TUE
–4
4
Counts
1
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a
maximum 16 factor.
2
Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform
conversions.
3 At V
RH – VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.
4
Guaranteed 10-bit monotonicity.
5 The absolute value of the offset error without calibration ≤ 100 counts.
6 The absolute value of the full scale gain error without calibration ≤ 120 counts.
7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than
VRH, and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not
affect device reliability or cause permanent damage.
9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pads on the internal pad.
11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12
TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).
15
Depending on the input impedance, the analog input leakage current (DC Electrical specification 35a) can affect the actual
TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
MPC5553 Microcontroller Data Sheet, Rev. 2.0
22
Freescale Semiconductor
Electrical Characteristics
3.11
H7Fa Flash Memory Electrical Characteristics
Table 14. Flash Program and Erase Specifications1
Spec
Spec
3
1
2
3
4
5
6
Flash Program Characteristic
Doubleword (64 bits) program time4
Symbol
Min
Typical
Initial
Max2
Max3
Unit
Tdwprogram
—
10
—
500
μs
Tpprogram
—
22
44
500
μs
16 Kbyte block pre-program and erase time
T16kpperase
—
325
525
5000
ms
9
48 Kbyte block pre-program and erase time
T48kpperase
—
435
525
5000
ms
10
64 Kbyte block pre-program and erase time
T64kpperase
—
525
675
5000
ms
8
128 Kbyte block pre-program and erase time
T128kpperase
—
675
1800
15,000
ms
11
Minimum operating frequency for program and erase
operations6
—
25
—
—
—
MHz
4
4
Page program time
7
5
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
Actual hardware programming times. This does not include software overhead.
Page size is 256 bits (8 words).
Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
Spec
1
Characteristic
Symbol
Min
Typical1
Unit
—
cycles
1a
Number of program/erase cycles per block for 16 Kbyte, 48 Kbyte, and
64 Kbyte blocks over the operating temperature range (TJ)
P/E
100,000
1b
Number of program/erase cycles per block for 128 Kbyte blocks over the
operating temperature range (TJ)
P/E
10,000
2
Data retention
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–100,000 P/E cycles
Retention
100,000 cycles
—
years
20
5
Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for
Nonvolatile Memory.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
23
Electrical Characteristics
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference
manual for definitions of these bit fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz)
APC
RWSC
WWSC
DPFEN
IPFEN
PFLIM
BFEN
Up to and including 82 MHz1
0b001
0b001
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000
to
0b1103
0b0,
0b14
Up to and including 102 MHz5
0b001
0b010
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000
to
0b1103
0b0,
0b14
Up to and including132 MHz6
0b010
0b011
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000
to
0b1103
0b0,
0b14
Default setting after reset
0b111
0b111
0b11
0b00
0b00
0b000
0b0
1
2
3
4
5
6
Allows for 80 MHz system clock with 2% frequency modulation.
For maximum flash performance, set to 0b11.
For maximum flash performance, set to 0b110.
For maximum flash performance, set to 0b1.
Allows for 100 MHz system clock with 2% frequency modulation.
Allows for 128 MHz system clock with 2% frequency modulation.
3.12
3.12.1
AC Specifications
Pad AC Specifications
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1
Spec
SRC/DSC
(binary)
Pad
11
1
Slow high voltage (SH)
01
00
11
2
Medium high voltage (MH)
01
00
Out Delay2, 3, 4
(ns)
Rise / Fall4, 5
(ns)
Load Drive
(pF)
26
15
50
82
60
200
75
40
50
137
80
200
377
200
50
476
260
200
16
8
50
43
30
200
34
15
50
61
35
200
192
100
50
239
125
200
MPC5553 Microcontroller Data Sheet, Rev. 2.0
24
Freescale Semiconductor
Electrical Characteristics
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1 (continued)
Spec
Out Delay2, 3, 4
(ns)
SRC/DSC
(binary)
Pad
Rise / Fall4, 5
(ns)
Load Drive
(pF)
2.7
10
2.5
20
2.4
30
2.3
50
00
3
01
Fast
3.1
10
11
1
2
3
4
5
4
Pullup/down (3.6 V max)
—
—
7500
50
5
Pullup/down (5.5 V max)
—
—
9000
50
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 132 MHz, VDD = 1.35–1.65 V, VDDE = 1.62–1.98 V, VDDEH = 4.5–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,
TA = TL to TH.
This parameter is supplied for reference and is guaranteed by design and tested.
Out delay is shown in Figure 4. Add a maximum of one system clock to the output delay for delay with respect to system
clock.
Delay and rise and fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Table 18. De-rated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)1
Spec
SRC/DSC
(binary)
Pad
11
1
Slow high voltage (SH)
01
00
11
2
Medium high voltage (MH)
01
00
Out Delay2, 3, 4
(ns)
Rise/Fall3, 5
(ns)
Load Drive
(pF)
39
23
50
120
87
200
101
52
50
188
111
200
507
248
50
597
312
200
23
12
50
64
44
200
50
22
50
90
50
200
261
123
50
305
156
200
2.4
10
2.2
20
2.1
30
2.1
50
00
3
01
Fast
10
3.2
11
1
4
Pullup/down (3.6 V max)
—
—
7500
50
5
Pullup/down (5.5 V max)
—
—
9500
50
These are worst-case values that are estimated from simulation and not tested. The values in the table are simulated at:
FSYS = 132 MHz; VDD = 1.35–1.65 V; VDDE = 3.0–3.6 V; VDDEH = 3.0–3.6 V; VDD33 and VDDSYN = 3.0–3.6 V; and
TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
25
Electrical Characteristics
2
This parameter is supplied for reference and is guaranteed by design and tested.
The delay, and the rise and fall, are measured to 20% or 80% of the respective signal.
4
Out delay is shown in Figure 4. Add a maximum of one system clock to the output delay for delay with respect to system clock.
5
This parameter is guaranteed by characterization before qualification rather than 100% tested.
3
VDD ÷ 2
Pad
internal data
input signal
Rising-edge
out delay
Falling-edge
out delay
VOH
Pad
output
VOL
Figure 4. Pad Output Delay
3.13
AC Timing
3.13.1
Reset and Configuration Pin Timing
Table 19. Reset and Configuration Pin Timing1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
RESET pulse width
tRPW
10
—
tCYC
2
RESET glitch detect pulse width
tGPW
2
—
tCYC
3
PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid
tRCSU
10
—
tCYC
4
PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid
tRCH
0
—
tCYC
Reset timing specified at: FSYS = 132 MHz; VDDEH = 3.0–5.25 V; VDD = 1.35–1.65 V; and TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
26
Freescale Semiconductor
Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 5. Reset and Configuration Pin Timing
3.13.2
IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
TCK cycle time
tJCYC
100
—
ns
2
TCK clock pulse width (measured at VDDE ÷ 2)
tJDC
40
60
ns
3
TCK rise and fall times (40% to 70%)
tTCKRISE
—
3
ns
4
TMS, TDI data setup time
tTMSS, tTDIS
5
—
ns
5
TMS, TDI data hold time
tTMSH, tTDIH
25
—
ns
6
TCK low to TDO data valid
tTDOV
—
20
ns
7
TCK low to TDO data invalid
tTDOI
0
—
ns
8
TCK low to TDO high impedance
tTDOHZ
—
20
ns
9
JCOMP assertion time
tJCMPPW
100
—
ns
10
JCOMP setup time to TCK low
tJCMPS
40
—
ns
11
TCK falling-edge to output valid
tBSDV
—
50
ns
12
TCK falling-edge to output valid out of high impedance
tBSDVZ
—
50
ns
13
TCK falling-edge to output high impedance (Hi-Z)
tBSDHZ
—
50
ns
14
Boundary scan input valid to TCK rising-edge
tBSDST
50
—
ns
15
TCK rising-edge to boundary scan input invalid
tBSDHT
50
—
ns
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35–1.65 V, VDDE = 3.0–3.6 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. Refer to Table 21 for functional
specifications.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
27
Electrical Characteristics
TCK
2
3
2
1
3
Figure 6. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 7. JTAG Test Access Port Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
28
Freescale Semiconductor
Electrical Characteristics
TCK
10
JCOMP
9
Figure 8. JTAG JCOMP Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
29
Electrical Characteristics
TCK
11
13
Output
signals
12
Output
signals
14
15
Input
signals
Figure 9. JTAG Boundary Scan Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
30
Freescale Semiconductor
Electrical Characteristics
3.13.3
Nexus Timing
Table 21. Nexus Debug Port Timing1
Spec
Characteristic
1
MCKO cycle time
2
MCKO duty cycle
3
MCKO low to MDO data valid
3
3
4
5
Unit
tMCYC
12
8
tCYC
tMDC
40
60
%
tMDOV
–1.5
3.0
ns
tMSEOV
–1.5
3.0
ns
tEVTOV
–1.5
3.0
ns
5
MCKO low to EVTO data valid
3
6
EVTI pulse width
tEVTIPW
4.0
—
tTCYC
7
EVTO pulse width
tEVTOPW
1
—
tMCYC
4
8
TCK cycle time
tTCYC
4
—
tCYC
9
TCK duty cycle
tTDC
40
60
%
10
TDI, TMS data setup time
tNTDIS, tNTMSS
8
—
ns
11
TDI, TMS data hold time
tNTDIH, tNTMSH
5
—
ns
VDDE = 2.25–3.0 V
0
12
ns
VDDE = 3.0–3.6 V
0
9
ns
—
—
—
13
3
Max
MCKO low to MSEO data valid
12
2
Min
4
TCK low to TDO data valid
1
Symbol
RDY valid to
tJOV
MCKO5
—
JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of
MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35–1.65 V, VDDE = 2.25–3.6 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
The Nexus AUX port runs up to 82 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than
82 MHz.
MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.
Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25–3.0 V) or 22 MHz (VDDE = 3.0–3.6 V) to meet the timing
specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification.
The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1
2
MCKO
4
3
5
MDO
MSEO
EVTO
Output Data Valid
Figure 10. Nexus Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
31
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 11. Nexus TDI, TMS, TDO Timing
3.13.4
External Bus Interface (EBI) Timing
Table 22. Bus Operation Timing1
Spec
Characteristic
and
Description
1
CLKOUT period
2
CLKOUT duty cycle
3
4
CLKOUT rise time
CLKOUT fall time
Symbol
40 MHz
(ext. bus)2
56 MHz
(ext. bus)2
66 MHz
(ext. bus)2
Unit
Notes
Signals are
measured at 50%
VDDE.
Min
Max
Min
Max
Min
Max
TC
25.0
—
17.9
—
15.2
—
ns
tCDC
45%
55%
45%
55%
45%
55%
TC
tCRT
tCFT
3
—
—
—
—3
3
—
—
—
—3
—
—
3
ns
—
—3
ns
MPC5553 Microcontroller Data Sheet, Rev. 2.0
32
Freescale Semiconductor
Electrical Characteristics
Table 22. Bus Operation Timing1 (continued)
Spec
Characteristic
and
Description
CLKOUT positive edge to
output signal invalid or
Hi-Z (hold time)
5
6
Min
tCOH
1.0
Max
4
56 MHz
(ext. bus)2
Min
Max
1.04
—
1.5
66 MHz
(ext. bus)2
Min
Unit
—
1.5
Notes
Max
1.04
EBTS=0
—
ns
1.5
EBTS=1
External bus interface
ADDR[8:31]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
WE/BE[0:3]
Hold time
selectable via
SIU_ECCR[EBTS]
bit.
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_CS[0, 2:3]
CAL_DATA[0:15]
CAL_WE/BE[0:1]
tCCOH
CLKOUT positive edge to
output signal valid
(output delay)
tCOV
1.05
1.04
—
1.5
1.04
—
EBTS=0
—
ns
1.5
1.5
EBTS=1
Hold time
selectable via
SIU_ECCR[EBTS]
bit.
10.04
—
7.54
—
6.04
8.5
11.0
ns
EBTS=0
—
7.0
EBTS=1
Output valid time
selectable via
SIU_ECCR[EBTS]
bit.
External bus interface
ADDR[8:31]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
WE/BE[0:3]
CLKOUT positive edge to
output signal valid
(output delay)
6a
Symbol
40 MHz
(ext. bus)2
11.04
tCCOV
8.54
—
—
12.0
7.04
ns
EBTS=0
—
9.5
8.0
EBTS=1
Output valid time
selectable via
SIU_ECCR[EBTS]
bit.
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_CS[0, 2:3]
CAL_DATA[0:15]
CAL_WE/BE[0:1]
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
33
Electrical Characteristics
Table 22. Bus Operation Timing1 (continued)
Spec
Characteristic
and
Description
Symbol
40 MHz
(ext. bus)2
56 MHz
(ext. bus)2
66 MHz
(ext. bus)2
Unit
Min
Max
Min
Max
Min
Max
tCIS
10.0
—
7.0
—
5.0
—
ns
tCCIS
11.0
—
8.0
—
6.0
—
ns
tCIH
1.0
—
1.0
—
1.0
—
ns
tCCIH
1.0
—
1.0
—
1.0
—
ns
Notes
Input signal valid to CLKOUT
positive edge (setup time)
7
External bus interface
ADDR[8:31]
BDIP
DATA[0:31]
OE
RD_WR
TA
TEA
TS
WE/BE[0:3]
Input signal valid to CLKOUT
positive edge (setup time)
7a
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_CS[0, 2:3]
CAL_DATA[0:15]
CAL_WE/BE[0:1]
CLKOUT positive edge to
input signal invalid (hold time)
8
External bus interface
ADDR[8:31]
BDIP
DATA[0:31]
OE
RD_WR
TA
TEA
TS
WE/BE[0:3]
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_CS[0, 2:3]
CAL_DATA[0:15]
CAL_WE/BE[0:1]
1
2
3
4
5
EBI timing specified at VDD = 1.35–1.65 V, VDDE = 1.6–3.6 V (unless stated otherwise),
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
The external bus is limited to half the speed of the internal bus.
Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
The EBTS = 0 timings are tested and valid at VDDE = 2.25–3.6 V only,
whereas EBTS = 1 timings are tested and valid at VDDE = 1.6–3.6 V.
The EBTS = 0 timings are tested and valid at VDDE = 2.25–3.6 V only,
whereas EBTS = 1 timings are tested and valid at VDDE = 1.6–3.6 V.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
34
Freescale Semiconductor
Electrical Characteristics
Voh_f
VDDE ÷ 2
CLKOUT
Vol_f
2
3
2
4
1
Figure 12. CLKOUT Timing
VDDE ÷ 2
CLKOUT
6
5
VDDE ÷ 2
5
Output
bus
VDDE ÷ 2
6
5
5
Output
signal
VDDE ÷ 2
6
Output
signal
VDDE ÷ 2
Figure 13. Synchronous Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
35
Electrical Characteristics
CLKOUT
VDDE ÷ 2
7
8
Input
bus
VDDE ÷ 2
7
8
Input
signal
VDDE ÷ 2
Figure 14. Synchronous Input Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
36
Freescale Semiconductor
Electrical Characteristics
3.13.5
External Interrupt Timing (IRQ Signals)
Table 23. External Interrupt Timing1
Spec
Characteristic
1
IRQ pulse-width low
2
IRQ pulse-width high
3
2
IRQ edge-to-edge time
Symbol
Min
Max
Unit
tIPWL
3
—
tCYC
TIPWH
3
—
tCYC
tICYC
6
—
tCYC
1
IRQ timing specified at FSYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,
TA = TL to TH, and CL = 200pF with SRC = 0b11.
2
Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
IRQ
2
1
3
Figure 15. External Interrupt Timing
CLKOUT
4
IRQ
Figure 16. External Interrupt Setup Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
37
Electrical Characteristics
3.13.6
eTPU Timing
Table 24. eTPU Timing1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
eTPU input channel pulse width
tICPW
4
—
tCYC
2
eTPU output channel pulse width
tOCPW
2
—
tCYC
eTPU timing specified at FSYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,
TA = TL to TH, and CL = 200 pF with SRC = 0b11.
2
eTPU
output
eTPU input
and TCRCLK
1
Figure 17. eTPU Timing
CLKOUT
4
eTPU
output
3
eTPU input
and TCRCLK
Figure 18. eTPU Input/Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
38
Freescale Semiconductor
Electrical Characteristics
3.13.7
eMIOS (MTS) Timing
Table 25. MTS Timing1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
eMIOS (MTS) input pulse width
tMIPW
4
—
tCYC
2
eMIOS (MTS) output pulse width
tMOPW
1
—
tCYC
MTS timing specified at FSYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,
TA = TL to TH, and CL = 50 pF with SRC = 0b11.
3.13.8
DSPI Timing
Table 26. DSPI Timing1
80 MHz
Spec
1
2
3
4
Characteristic
SCK cycle time2,3
PCS to SCK
After SCK
112 MHz
132 MHz
Symbol
delay4
delay5
SCK duty cycle
Max
Min
Max
Min
Max
tSCK
25 ns
2.9 ms
17.9 ns
2.0 ms
15.2 ns
1.7 ms
—
tCSC
23
—
15
—
13
—
ns
tASC
22
—
14
—
12
—
ns
—
—
—
—
ns
tSDC
5
Slave access time
(SS active to SOUT driven)
6
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
7
Unit
Min
(tSCK ÷ 2) (tSCK ÷ 2)
– 2 ns
+ 2 ns
tA
—
25
—
25
—
25
ns
tDIS
—
25
—
25
—
25
ns
PCSx to PCSS time
tPCSC
4
—
4
—
4
—
ns
8
PCSS to PCSx time
tPASC
5
—
5
—
5
—
ns
tSUI
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
20
2
–4
20
—
—
—
—
20
2
3
20
—
—
—
—
20
2
6
20
—
—
—
—
ns
ns
ns
ns
tHI
10
Data hold time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
–4
7
21
–4
—
—
—
—
–4
7
14
–4
—
—
—
—
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
tSUO
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
ns
ns
ns
ns
tHO
12
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–5
5.5
8
–5
—
—
—
—
–5
5.5
4
–5
—
—
—
—
–5
5.5
3
–5
—
—
—
—
ns
ns
ns
ns
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
39
Electrical Characteristics
1
2
3
4
5
6
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of
S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated using the SMPL_PT bit field in DSPI_MCR set to 0b10.
2
3
PCSx
1
4
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
9
SIN
10
First data
Data
12
SOUT
First data
Last data
11
Data
Last data
Figure 19. DSPI Classic SPI Timing—Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0
40
Freescale Semiconductor
Electrical Characteristics
PCSx
SCK output
(CPOL=0)
10
SCK output
(CPOL=1)
9
Data
First data
SIN
Last data
12
SOUT
11
Data
First data
Last data
Figure 20. DSPI Classic SPI Timing—Master, CPHA = 1
3
2
SS
1
4
SCK input
(CPOL=0)
4
SCK input
(CPOL=1)
5
SOUT
First data
9
SIN
12
11
Data
Last data
Data
Last data
6
10
First data
Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
41
Electrical Characteristics
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
SOUT
First data
9
SIN
Data
Last data
Data
Last data
10
First data
Figure 22. DSPI Classic SPI Timing—Slave, CPHA = 1
3
PCSx
4
1
2
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
9
SIN
First data
10
12
SOUT
First data
Last data
Data
11
Data
Last data
Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0
42
Freescale Semiconductor
Electrical Characteristics
PCSx
SCK output
(CPOL=0)
SCK output
(CPOL=1)
10
9
SIN
First data
Last data
Data
12
First data
SOUT
11
Last data
Data
Figure 24. DSPI Modified Transfer Format Timing—Master, CPHA = 1
3
2
SS
1
SCK input
(CPOL=0)
4
4
SCK input
(CPOL=1)
SOUT
First data
Data
First data
6
Last data
10
9
SIN
12
11
5
Data
Last data
Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA =0
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
43
Electrical Characteristics
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
First data
SOUT
9
Last data
Data
Last data
10
First data
SIN
Data
Figure 26. DSPI Modified Transfer Format Timing—Slave, CPHA =1
7
8
PCSS
PCSx
Figure 27. DSPI PCS Strobe (PCSS) Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
44
Freescale Semiconductor
Electrical Characteristics
3.13.9
eQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics (Pads at 3.3 V or 5.0 V)
CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.
Spec
Rating
Symbol
Minimum
Typical
Maximum
Unit
tFCK
2
—
17
tSYS_CLK
2
FCK period (tFCK = 1 ÷ fFCK) 1, 2
3
Clock (FCK) high time
tFCKHT
tSYS_CLK − 6.5
—
9 × (tSYS_CLK + 6.5)
ns
4
Clock (FCK) low time
tFCKLT
tSYS_CLK − 6.5
—
8 × (tSYS_CLK + 6.5)
ns
5
SDS lead / lag time
tSDS_LL
–7.5
—
+7.5
ns
6
SDO lead / lag time
tSDO_LL
–7.5
—
+7.5
ns
7
EQADC data setup time (inputs)
tEQ_SU
22
—
—
ns
8
EQADC data hold time (inputs)
tEQ_HO
1
—
—
ns
1
SS timing specified at FSYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,
TA = TL to TH, and CL = 50 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master
pad delays, and slave pad delays.
2 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
FCK
5
4
SDS
25th
6
SDO
1st (MSB)
5
2nd
26th
External device data sample at
FCK falling-edge
8
7
SDI
1st (MSB) 2nd
25th
26th
EQADC data sample at
FCK rising-edge
Figure 28. EQADC SSI Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
45
Electrical Characteristics
3.14
Fast Ethernet AC Timing Specifications
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic
(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC
signals are independent of the system clock frequency (part speed designation).
3.14.1
MII FEC Receive Signal Timing
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.
There is no minimum frequency requirement. The processor clock frequency must exceed four times the
FEC_RX_CLK frequency.
Table 28 lists MII FEC receive channel timings.
Table 28. MII FEC Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
3
FEC_RX_CLK pulse-width high
35%
65%
FEC_RX_CLK period
4
FEC_RX_CLK pulse-width low
35%
65%
FEC_RX_CLK period
Figure 29 shows MII FEC receive signal timings listed in Table 28.
M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 29. MII FEC Receive Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 2.0
46
Freescale Semiconductor
Electrical Characteristics
3.14.2
MII FEC Transmit Signal Timing
FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK
The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one
percent. There is no minimum frequency requirement. In addition, the processor clock frequency must
exceed twice the FEC_TX_CLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER) can be programmed to transition
from either the rising- or falling-edge of TX_CLK, and the timing is the same in either case. These options
allow the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the device reference manual for details of this option
and how to enable it.
Table 29 lists MII FEC transmit channel timings.
Table 29. MII FEC Transmit Signal Timing
Spec
Characteristic
Min
Max
Unit
5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
25
ns
7
FEC_TX_CLK pulse-width high
35%
65%
FEC_TX_CLK period
8
FEC_TX_CLK pulse-width low
35%
65%
FEC_TX_CLK period
Figure 30 shows MII FEC transmit signal timings listed in Table 29.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 30. MII FEC Transmit Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
47
Electrical Characteristics
3.14.3
MII FEC Asynchronous Inputs Signal Timing
FEC_CRS and FEC_COL
Table 30 lists MII FEC asynchronous input signal timing.
Table 30. MII FEC Asynchronous Inputs Signal Timing
Spec
9
Characteristic
Min
Max
Unit
1.5
—
FEC_TX_CLK period
FEC_CRS, FEC_COL minimum pulse width
Figure 31 shows MII FEC asynchronous input timing listed in Table 30.
FEC_CRS, FEC_COL
M9
Figure 31. MII FEC Asynchronous Inputs Timing Diagram
3.14.4
MII FEC Serial Management Channel Timing
FEC_MDIO and FEC_MDC
Table 31 lists MII FEC serial management channel timings. The FEC functions correctly with a maximum
FEC_MDC frequency of 2.5 MHz.
Table 31. MII FEC Serial Management Channel Timing
Spec
Characteristic
Min
Max
Unit
10
FEC_MDC falling-edge to FEC_MDIO output invalid
(minimum propagation delay)
0
—
ns
11
FEC_MDC falling-edge to FEC_MDIO output valid
(maximum propagation delay)
—
25
ns
12
FEC_MDIO (input) to FEC_MDC rising-edge setup
10
—
ns
13
FEC_MDIO (input) to FEC_MDC rising-edge hold
0
—
ns
14
FEC_MDC pulse-width high
40%
60%
FEC_MDC period
15
FEC_MDC pulse-width low
40%
60%
FEC_MDC period
Figure 32 shows MII FEC serial management channel timings listed in Table 31.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
48
Freescale Semiconductor
Electrical Characteristics
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 32. MII FEC Serial Management Channel Timing Diagram
CLKOUT
5
5
RESET
6
6
RSTOUT
Figure 33. Reset and Configuration Pin Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
49
Mechanicals
4
Mechanicals
4.1
Pinouts
4.1.1
MPC5553 416 PBGA Pinout
Figure 34, Figure 35, and Figure 36 show the pinout for the MPC5553 416 PBGA package. While the
MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 BGA is shown to
highlight the balls that are not connected to any signal on the MPC5553 (the eTPUB[0:31] and TSIZ[0:1]).
The alternate Fast Ethernet Controller (FEC) signals that are multiplexed with the data bus are not shown
for the MPC5553.
NOTE
Some pins have names that include functions that are not available on all
MPC55xx devices. For example, ball R25 of the 416 BGA package is named
‘SINA,’ but the MPC5553 does not have a DSPI A module. In this case, the
SINA pin can only be used for its alternate functions of GPIO[94] or
PCSC[2]. Refer to the specific device Reference Manual for functions
available on each device.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
50
Freescale Semiconductor
Mechanicals
A
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS
VSTBY
AN37
AN11
VDDA1
AN16
AN1
AN5
VRH
AN23
AN27
AN28
AN35
VSSA0
AN15
ETRIG
1
NC_1
NC_2
NC_3
NC_4
GPIO
205
NC_5
NC_6
NC_7
NC_8 MDO10 MDO7
NC_10 NC_11 NC_12 MDO9
VDD
C VDD33
D
VSS
AN36
AN39
AN19
AN20
AN0
AN4
REF
BYPC
AN22
AN26
AN31
AN32
VSSA0
AN14
ETRIG
0
VDD
VSS
AN8
AN17
VSSA1
AN21
AN3
AN7
VRL
AN25
AN30
AN33
VDDA0
AN13
NC_9
VDD
VSS
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34 VDDEH AN12
9
ETPUA ETPUA
30
31
ETPUA ETPUA VDDEH
E
28
29
1
ETPUA ETPUA ETPUA VDDEH
24
27
26
1
G
ETPUA ETPUA ETPUA ETPUA
23
22
25
21
MDO2 VDDEH
8
Version 2.1 – 13 July 2004
ETPUA ETPUA ETPUA ETPUA
H
20
19
18
17
J
ETPUA ETPUA ETPUA ETPUA
16
15
14
13
K
ETPUA ETPUA ETPUA ETPUA
12
11
10
9
23
24
25
26
VDD
VDD33
VSS
MDO4
MDO0
VSS
MDO1
VSS
VDDE7
VDD
C
VSS
VDDE7
TCK
TDI
D
VDDE7 B
VDDE7
TMS
E
TDO
TEST
MSEO0 JCOMP
EVTI
EVTO F
MSEO1 MCKO
GPIO
204
NC_17 G
RDY
GPIO
203
NC_18 NC_19 H
VSS
VSS
VSS
VSS
VSS
VSS
VDDE7 VDDE7 VDDE7 VDDE7
NC_23 NC_24 NC_25 NC_26 K
VSS
VSS
VSS
VSS
VSS
VDDE7
ETPUA ETPUA ETPUA ETPUA
4
3
2
1
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VDDE7
NC_31 NC_32 NC_33
ETPUA TCRCLK
0
A
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 N
PCSA3 PCSB4 SCKB PCSB2 P
BDIP
TEA
NC_27 NC_28 NC_29 NC_30 L
P
CS3
CS2
CS1
CS0
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VSS
R
WE3
WE2
WE1
WE0
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VSS
PCSB5 SOUTA
VDDE2 VDDE2 VDDE2 VDDE2
VSS
VSS
PCSA1 PCSA0 PCSA2
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
VSS
VSS
VDDE2
T VDDE2 NC_34 RD_WR VDDE2
ADDR
U
NC_35
16
TA
VDD33
V
ADDR
18
ADDR
17
TS
ADDR
8
W
ADDR
20
ADDR
19
ADDR
9
ADDR
10
Y
ADDR
22
ADDR
21
ADDR
VDDE2
11
ADDR
AA
24
ADDR
23
ADDR
13
ADDR
12
AB VDDE2
ADDR
25
ADDR
15
ADDR
14
ADDR
AC
26
ADDR
27
ADDR
31
VSS
AD
ADDR
28
ADDR
30
VSS
VDD
AE
ADDR
29
VSS
VDD
DATA
17
VSS
VDD
DATA
16
DATA
18
1
2
3
4
AF
A
VDDEH NC_20 NC_21 NC_22
J
6
ETPUA ETPUA ETPUA ETPUA
L
8
7
6
5
N
MDO3
VDD
F
M
NC_13 NC_14 NC_15 NC_16 MDO5
MDO6
22
MDO11 MDO8
VSS
VSS
SINA
SINB
SCKA R
VPP
NC_36
NC_37
WKP
CFG
No connect. AC22 & AD23 reserved
VDDE2
DATA
31
DATA
8
DATA
10
VDDE2
DATA
12
DATA
29
VDD33
GPIO
207
DATA
9
DATA
11
DATA
13
DATA
15
DATA
23
DATA
0
DATA
2
DATA
4
DATA
6
OE
BR
BG
DATA
22
GPIO
206
DATA
1
DATA
3
VDDE2
DATA
5
DATA
7
7
8
9
10
11
12
13
VDD
DATA
28
DATA
24
DATA
25
DATA
27
DATA
19
DATA
21
VDDE2
DATA
20
5
6
DATA
14
BOOT
CFG1
VDDEH PLL
6
CFG1
VDD
DATA
30
DATA
26
EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36
2
8
12
21
4
VSS
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37
3
6
10
15
17
22
VRC
CTL
VRC
VSS
16
17
18
19
20
21
22
23
Y
XTAL
AB
VDD
VRC33
VDD
SYN
AC
VSS
VDD
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
1
5
9
13
16
19
23
15
VSS
SYN
BOOT EXTAL
AA
CFG0
PLL
CFG0
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
0
4
7
11
14
18
20
14
V
RXDB CNRXC TXDB RESET W
No connects (x = 1 to 38)
NC_X
T
PCSA4 TXDA PCSA5 VFLASH U
CNTXC RXDA RSTOUT RST
CFG
Note:
M
24
VDD33 AD
VDD
AE
ENG
CLK
VSS
AF
25
26
Figure 34. MPC5553 416 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
51
Mechanicals
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
VSTBY
AN37
AN11
VDDA1
AN16
AN1
AN5
VRH
AN23
AN27
AN28
AN35
B
VDD
VSS
AN36
AN39
AN19
AN20
AN0
AN4
REF
BYPC
AN22
AN26
AN31
AN32
VDD
VSS
AN8
AN17
VSSA1
AN21
AN3
AN7
VRL
AN25
AN30
AN33
VDD
VSS
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34
C VDD33
D
ETPUA ETPUA
30
31
E
ETPUA ETPUA VDDEH
28
29
1
F
ETPUA ETPUA ETPUA VDDEH
24
27
26
1
G
ETPUA ETPUA ETPUA ETPUA
23
22
25
21
H
ETPUA ETPUA ETPUA ETPUA
20
19
18
17
J
ETPUA ETPUA ETPUA ETPUA
16
15
14
13
K
ETPUA ETPUA ETPUA ETPUA
12
11
10
9
VSS
VSS
VSS
VSS
L
ETPUA ETPUA ETPUA ETPUA
8
7
6
5
VSS
VSS
VSS
VSS
M
ETPUA ETPUA ETPUA ETPUA
4
3
2
1
VDDE2 VDDE2
VSS
VSS
ETPUA TCRCLK
0
A
VDDE2 VDDE2
VSS
VSS
VDD
Version 2.1 – 13 July 2004
N
BDIP
TEA
P
CS3
CS2
CS1
CS0
VDDE2 VDDE2
VSS
VSS
R
WE3
WE2
WE1
WE0
VDDE2 VDDE2
VSS
VSS
VDDE2
T VDDE2 NC_34 RD_WR VDDE2
U
ADDR
NC_35
16
TA
VDD33
V
ADDR
18
ADDR
17
TS
ADDR
8
W
ADDR
20
ADDR
19
ADDR
9
ADDR
10
Y
ADDR
22
ADDR
21
ADDR
VDDE2
11
ADDR
AA
24
ADDR
23
ADDR
13
ADDR
12
AB VDDE2
ADDR
25
ADDR
15
ADDR
14
AC
ADDR
26
ADDR
27
ADDR
31
VSS
VDD
DATA
26
DATA
28
AD
ADDR
28
ADDR
30
VSS
VDD
DATA
24
DATA
25
DATA
27
DATA
29
AE
ADDR
29
VSS
VDD
DATA
17
DATA
19
DATA
21
DATA
23
AF
VSS
VDD
DATA
16
DATA
18
VDDE2
DATA
20
1
2
3
4
5
6
VSS
Note:
VSS
VDDE2 VDDE2
VDDE2 VDDE2 VDDE2
No connects (x = 1 to 38)
NC_X
No connect. AC22 & AD23 reserved
NC_36 NC_37
VDDE2 DATA
30
DATA
31
DATA
8
DATA
10
VDDE2
VDD33
GPIO
207
DATA
9
DATA
11
DATA
13
DATA
0
DATA
2
DATA
4
DATA
6
OE
BR
DATA
22
GPIO
206
DATA
1
DATA
3
7
8
9
10
VDDE2 DATA
5
11
12
DATA
7
13
Figure 35. MPC5553 416 Package, Left Side
MPC5553 Microcontroller Data Sheet, Rev. 2.0
52
Freescale Semiconductor
Mechanicals
14
15
16
VSSA0
AN15
ETRIG
1
NC_1
NC_2
NC_3
NC_4
VSSA0
AN14
ETRIG
0
NC_5
NC_6
NC_7
NC_8 MDO10 MDO7
VDDA0
AN13
NC_9
NC_10 NC_11 NC_12 MDO9
VDDEH AN12
9
17
18
19
20
NC_13 NC_14 NC_15 NC_16 MDO5
21
22
23
24
25
26
VDD
VDD33
VSS
MDO4
MDO0
VSS
MDO1
VSS
VDDE7
VDD
C
VSS
VDDE7
TCK
TDI
D
VDDE7
TMS
TDO
TEST
E
MSEO0 JCOMP
EVTI
EVTO
F
MSEO1 MCKO
GPIO
204
NC_17 G
GPIO MDO11 MDO8
205
MDO6
MDO3
MDO2 VDDEH
8
RDY
GPIO
203
A
VDDE7 B
NC_18 NC_19 H
VDDEH NC_20 NC_21 NC_22
J
6
VDDE7 VDDE7 VDDE7 VDDE7
NC_23 NC_24 NC_25 NC_26 K
VSS
VSS
VSS
VDDE7
NC_27 NC_28 NC_29 NC_30 L
VSS
VSS
VSS
VDDE7
NC_31 NC_32 NC_33
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 N
VSS
VSS
VSS
VSS
PCSA3 PCSB4 SCKB PCSB2 P
VSS
VSS
VSS
VSS
PCSB5 SOUTA
VDDE2 VDDE2
VSS
VSS
PCSA1 PCSA0 PCSA2
VDDE2 VDDE2
VSS
VSS
PCSA4 TXDA PCSA5 VFLASH U
SINA
CNTXC RXDA RSTOUT
SINB
M
SCKA R
VPP
RST
CFG
T
V
RXDB CNRXC TXDB RESET W
WKP
CFG
BOOT
CFG1
VDDEH PLL
6
CFG1
BOOT EXTAL
AA
CFG0
PLL
CFG0
XTAL
AB
VSS
VDD
VRC33
VDD
SYN
AC
VSS
VDD
DATA
15
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37
3
6
10
15
17
22
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
1
5
9
13
16
19
23
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
0
4
7
11
14
18
20
15
16
17
18
19
20
21
22
Y
VRC
CTL
DATA
14
14
VSS
SYN
VDD
DATA
12
BG
EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36
2
8
12
21
4
VRC
VSS
23
24
VDD33 AD
VDD
AE
ENG
CLK
VSS
AF
25
26
Figure 36. MPC5553 416 Package, Right Side
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
53
Mechanicals
4.1.2
MPC5553 324 PBGA Pinout
Figure 37 is a pinout for the MPC5553 324 PBGA package.
A
1
2
3
4
5
VSS
VDD
VSTBY
AN37
AN11
B VDD33
VSS
6
7
VDDA1 VSSA1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
AN1
AN5
VRH
VRL
AN27
AN28
AN35
VSSA0
AN12 MDO11 MDO10 MDO8
VDD
VDD33
AN0
AN4
REF
BYPC
AN23
AN26
AN31
AN32
VSSA0
AN13
MDO9
MDO7
MDO4
MDO0
VSS
VDDA0
22
VSS
A
VDD
AN36
AN39
AN19
AN16
VSS
VDD
AN8
AN17
AN20
AN21
AN3
AN7
AN22
AN25
AN30
AN33
AN14
MDO5
MDO2
MDO1
VSS
VDDE7
VDD
C
VSS
VDD
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34 VDDEH AN15
9
MDO6
MDO3
C
ETPUA ETPUA
30
31
D
ETPUA ETPUA ETPUA
28
29
26
VDDE7 B
VSS
VDDE7
TCK
TDI
D
ETPUA ETPUA ETPUA ETPUA
E
24
27
25
21
VDDE7
TMS
TDO
TEST
E
ETPUA ETPUA ETPUA ETPUA
F
23
22
17
18
VDDE7 JCOMP
EVTI
EVTO
F
ETPUA ETPUA ETPUA ETPUA
G
20
19
14
13
RDY
Version 2.2p – 13 July 2004
ETPUA ETPUA ETPUA VDDEH
H
16
15
10
1
MCKO MSEO0 MSEO1 G
VDDEH GPIO
10
203
GPIO
204
SINB
H
ETPUA ETPUA ETPUA ETPUA
J
6
9
12
11
VSS
VSS
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 J
ETPUA ETPUA ETPUA ETPUA
K
5
8
7
2
VSS
VSS
VSS
VSS
VSS
VSS
PCSA3 PCSB4 SCKB PCSB2 K
ETPUA ETPUA ETPUA ETPUA
L
1
4
3
0
VSS
VSS
VSS
VSS
VSS
VSS
PCSB5 SOUTA
M
TCRCLK
BDIP
A
CS1
N
CS3
P
ADDR
16
ADDR
RD_WR VDD33
17
R
ADDR
18
CS2
WE1
WE0
ADDR VDDE2
19
TA
ADDR
T
20
ADDR
21
ADDR
12
TS
ADDR
U
22
ADDR
23
ADDR
13
ADDR
14
ADDR
24
ADDR
25
ADDR
15
ADDR
31
V
ADDR
ADDR
W
VDDE2
30
26
ADDR
Y
28
ADDR
AA
29
AB
ADDR
27
VSS
VSS
VDD
1
2
VSS
VDD
VSS
VDD
Note:
4
NC
VSS
VSS
VSS
VSS
PCSA1 PCSA0 PCSA2
VSS
VDDE2
VSS
VSS
VSS
PCSA4 TXDA PCSA5 VFLASH N
VSS
VSS
VDDE2
VSS
VSS
VSS
CNTXC RXDA RSTOUT
RXDB
No connect. Reserved (W18 & Y19 are shorted to each other)
VDDE2 VDD33 VDDE2 DATA
11
VDDE2 DATA
8
DATA
9
DATA
10
GPIO
207
DATA
5
DATA
7
VDDE2
GPIO
206
DATA
2
DATA
3
DATA
4
DATA
6
OE
5
6
7
8
9
DATA
12
DATA
14
EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5
21
4
12
2
8
DATA
13
DATA
15
EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5
22
17
10
15
6
NC
VPP
RST
CFG
M
P
CNRXC TXDB RESET R
BOOT
CFG1
VDDEH PLL
6
CFG1
VDD
VDD
SCKA L
VSS
WKP
CFG
VDDE2 DATA
1
DATA
VDDE2
0
3
VDDE2 VDDE2
CS0
SINA
VRC
CTL
VRC
VSS
VSS
SYN
T
BOOT
EXTAL U
CFG0
PLL
CFG0
XTAL
V
VDD
SYN
W
VSS
VDD
VRC33
NC
VSS
VDD
VDD33 Y
VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
23
19
16
3
5
9
13
VDD
AA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
20
18
14
0
1
4
7
11
ENG
CLK
VSS
AB
21
22
10
11
12
13
14
15
16
17
18
19
20
Figure 37. MPC5553 324 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
54
Freescale Semiconductor
Mechanicals
4.1.3
MPC5553 208 MAP BGA Pinout
Figure 38 is a pinout for the MPC55MPC5553 208 MAP BGA package.
NOTES
VDDEH10 and VDDEH6 are connected internally on the 208-ball package and
are listed as VDDEH6.
1
2
3
4
A
VSS
AN9
AN11
B
VDD
VSS
AN38
AN21
C VSTBY
VDD
VSS
D VDD33
AN39
5
6
7
8
9
10
11
12
13
AN1
AN5
VRH
VRL
AN27
VSSA0
AN12
MDO2
MDO0 VDD33
VSS
A
AN0
AN4
REF
BYPC
AN22
AN25
AN28
VDDA0
AN13
MDO3
MDO1
VSS
VDD
B
AN17
AN34
AN16
AN3
AN7
AN23
AN32
AN33
AN14
AN15
VSS
MSEO0
TCK
C
VDD
VSS
AN18
AN2
AN6
AN24
AN30
AN31
AN35 VDDEH
9
VSS
TMS
EVTO
TEST
D
AN37
VDD
VDDE7
TDI
EVTI
VDDEH
6
TDO
VDDA1 VSSA1
14
15
16
E
ETPUA ETPUA
30
31
F
ETPUA ETPUA ETPUA
28
29
26
G
ETPUA ETPUA ETPUA ETPUA
24
27
25
21
VSS
VSS
VSS
VSS
SOUTB PCSB3
H
ETPUA ETPUA ETPUA ETPUA
23
22
17
18
VSS
VSS
VSS
VSS
PCSA3 PCSB4 PCSB2 PCSB1 H
J
ETPUA ETPUA ETPUA ETPUA
14
20
19
13
VSS
VSS
VSS
VSS
PCSB5 TXDA PCSA2 SCKB J
K
ETPUA ETPUA ETPUA VDDEH
16
15
7
1
VSS
VSS
VSS
VSS
CNTXC RXDA RSTOUT
L
ETPUA ETPUA ETPUA TCRCLK
12
11
6
A
TXDB CNRXC
M
ETPUA ETPUA ETPUA ETPUA
1
5
9
10
RXDB
PLL
CFG0
BOOT
CFG1
N
ETPUA ETPUA ETPUA
0
4
8
VSS
VDD
VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33
2
10
21
4
12
VSS
VRC
CTL
PLL
CFG1
P
ETPUA ETPUA
2
3
VSS
VDD
GPIO
207
VDDE2
EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA
6
8
22
16
17
VDD
VSS
VRC33
XTAL
P
GPIO
206
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB
4
3
9
11
14
19
23
VDD
VSS
VDD
SYN
R
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5
0
1
5
7
13
15
18
20
ENG
CLK
VDD
VSS
T
14
15
16
R
CS0
VSS
VDD
T
VSS
VDD
OE
1
2
3
AN36
4
8 June 2005p
5
6
7
8
9
10
11
12
13
MSEO1 E
MCKO JCOMP F
SINB
WKP
CFG
PCSB0 G
VPP
K
RESET L
VSS
SYN
M
EXTAL N
Figure 38. MPC5553 208 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
55
Mechanicals
4.2
4.2.1
Package Dimensions
MPC5553 416-Pin Package
The package drawings of the MPC5553 416 pin TEPBGA package are shown in Figure 39.
Figure 39. MPC5553 416 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
56
Freescale Semiconductor
Mechanicals
Figure 39. MPC5553 416 TEPBGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
57
Mechanicals
4.2.2
MPC5553 324-Pin Package
The package drawings of the MPC5553 324-pin TEPBGA package are shown in Figure 40.
Figure 40. MPC5553 324 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
58
Freescale Semiconductor
Mechanicals
Figure 40. MPC5553 324 TEPBGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
59
Mechanicals
4.2.3
MPC5553 208-Pin Package
The package drawings of the MPC5553 208-pin MAP BGA package are shown in Figure 41.
Figure 41. MPC5553 208 MAP BGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0
60
Freescale Semiconductor
Mechanicals
Figure 41. MPC5553 208 MAP BGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
61
MPC5553 Revision History
5
MPC5553 Revision History
Table 32 provides a revision history of the MPC5553 Data Sheet.
Table 32. MPC5553 Revision History
Revision
Location(s)
Rev. 0
Rev. 1
This is the first released version of this document.
Table 1
Footnote added to Freescale Part Number column.
Table 2
Footnotes 6, 8, and 9 changed from 1mA to 2mA.
Figure 39, Figure 40,
Figure 41
Figure 37
Rev. 1.1
Substantive Change(s)
Throughout
Second page of package drawings added.
Removed note about pin R1 in the figure and added a Note above it instead.
Editorial changes: subscripting, simplifying language.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
62
Freescale Semiconductor
MPC5553 Revision History
Table 33 is the new format for the Revision History and changes continue from Table 32.
Table 33. MPC5553 Revision History (continued)
Revision
Author
Date
Substantive Change(s)
Rev. 1.1
NH
02/02/07
Changes per RD initial review:
• Changed the values in Table 14 for the H7Fa Flash pre-program and erase times.
Typical and Initial Max values changed.
• Typical Values —
16 Kbytes: from 265 to 325
48 Kbytes: from 340 to 435
64 Kbytes: from 400 to 525
128 Kbytes: from 500 to 675
• Initial Max Values —
16 Kbytes: from 400 to 525
48 Kbytes: from 400 to 525
64 Kbytes: from 500 to 675
128 Kbytes: from 1250 to 1800
Rev. 1.1
NH
02/06/07
Changes per RD second review:
• Added Figure 3 to show interpolated IDDSTBY values listed in Table 9.
• Table 9 DC Electrical Specifications: Changed wording of footnote 3. Spec 28:
Corrected conditional text error showing wrong frequency. Spec 29: Deleted
frequency information.
• Table 6 FMPLL Electrical Characteristics: Grouped (2 x Cl) in Specs 12 and 13.
• Table 7 Power Sequence Pin Status for Fast Pads, updated paragraph.
• Table 8 Power Sequence Pin Status, updated preceding paragraph.
• Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33 Updated
paragraph to remove redundancy,
• Table 16 Flash BIU Settlings: Changed wording of footnote from “Can be changed
after Analysis and Characterization” to “These values may change after
characterization.”
• Table 17and Table 18: Deleted the words ‘not’ from footnote 2. Changed from ‘This
parameter is supplied for reference and is not guaranteed by design and not tested’
to ‘This parameter is supplied for reference and is guaranteed by design and tested.’
• Table 22 Bus Operation Timing: Specs 5 and 6: corrected format to show the bus
timing values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Specs 6 and 7: Added the calibrations signals: CAL_ADDR, CAL_WE/BE, CAL_CS,
CAL_DATA.
• Table 26 DSPI Timing: Added to beginning of footnote 1 ‘All DSPI timing
specifications use the fastest slew rate (SRC=0b11) on pad type M or MH. DSPI
signals using pad types of S or SH have an additional delay based on the slew rate.’
• Table 27 EQADC SS Timing Characteristics: combined footnotes 1 and 2. Moved
footnotes 1 and 2 to Spec 2 and deleted Spec 1.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
63
MPC5553 Revision History
Table 33. MPC5553 Revision History (continued)
Revision
Author
Date
Substantive Change(s)
Rev 2.0
NH
02/07/07
Changes per RD sign-off review:
• Changed paragraph preceding Table 7 Power Sequence Pin Status for the Fast
Pad:
From: Although there are no power up/down sequencing requirements to prevent
issues like latch-up, excessive current spikes, etc., the state of the I/O pins during
power up/down varies depending on power. Prior to exiting POR, the pads are in
a high impedance state (Hi-Z).
To: There are no power up/down sequencing requirements to prevent issues such
as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O
pins during power up/down varies depending on which supplies are powered.
• Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33,” changed
From:
To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and
RSTCFG are not treated as ones (1s) when POR negates, VDD33 must not lag
VDDSYN and the RESET pin power (VDDEH6) when powering the device by
more than the VDD33 lag specification in Table 6. VDD33 individually can lag
either VDDSYN or the RESET power pin (VDDEH6) by more than the VDD33 lag
specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot
lag both by more than the VDD33 lag specification. This VDD33 lag specification
only applies during power up. VDD33 has no lead or lag requirements when
powering down.
To:
When powering the device, VDD33 must not lag VDDSYN and the RESET power
pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6. This
avoids accidentally selecting the bypass clock mode because the internal versions
of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the
default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This
VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.
• Table 22 Bus Operation Timing:
Added the correct pins to the calibration signals:
CAL_ADDR[10:11, 27:30], CAL_WE/BE[0:1], CAL_CS[0, 2:3], and
CAL_DATA[0:15]. Added calibration signals to Specs 5 and 8.
• Corrected the following EBI signals:
Specs 7 and 8: Added the following signals to Specs 7 and 8 the EBI section: OE,
RD_WR, and BDIP. Broke out Spec 6 CLKOUT Posedge to output signal valid into
Spec 6 for the EBI signals, and Spec 6a for the calibration signals, Broke out Spec 7
Input Signal Valid to CLKOUT Posedge into Spec 7 for the EBI signals, and Spec 7a
for the calibration signals.
• Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)” Deleted the underscore
in ORed_POR to become ORed POR.
Rev 2.0
NH
2/09/07
Table 22 Bus Operation Timing:
Removed references to CAL_OE, CAL_RD_WR, and CAL_TS because they really use
the EBI signals OE, RD_WR, and TS on the MPC5553.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
64
Freescale Semiconductor
MPC5553 Revision History
Table 33. MPC5553 Revision History (continued)
Revision
Author
Date
Substantive Change(s)
Rev 2.0
NH
2/27/07
Per RD comments:
Table 2 Absolute Maximum Ratings: changed footnote 6 from:
Keep the negative DC current greater than 0.6 V on eTPUB[15] and SINB during the
internal power-on reset (POR) state.
To: Keep the negative DC current greater than –0.6 V on eTPUB[15] and SINB during
the internal power-on reset (POR) state.
Figure 38 MPC5553 208 Map BGA Pinout: Deleted two lines referring to the CS[0]
signal ball assignment for the 208.
Rev 2.0
NH
3/1/07
Corrected the signal names in Section 3.14, “Fast Ethernet AC Timing Specifications”
to include the FEC_ prefix for the signal name. Waiting on response from Jim Eifert,
Randy Dees, Jeffery Hopkins, and Bill Terry about the following Bugs filed against the
Data Sheets: 1474, 1480, 1482, 1483, 1811, 1815, 1884, 2254, 2419, 2717, 2873
before preparing for final sign-off again.
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
65
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Document Number: MPC5553
Rev. 2.0
03/2007
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