FUJITSU MB15F63ULPVA1

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21382-1E
ASSP DTS
Bi-CMOS
Dual Serial Input
PLL Frequency Synthesizer
MB15F63UL
■ DESCRIPTION
MB15F63UL has a 2000 MHz PLL frequency synthesizer with a high-speed frequency switching function based
on the Fractional-N PLL (Phase Locked Loop), and 600 MHz Integer-N PLL frequency synthesizer which enables
pulse swallow operation. Encased in a subminiature package (thin-BCC20), MB15F63UL has successfully
achieved a small thin external form (BCC20 package dimensions: 3.50 mm × 3.50 mm × 0.60 mm). MB15F63UL
is suitable for use in digital mobile communication devices such as GSM.
■ FEATURES
100 MHz to 1800 MHz (RF : 2.7 V ≤ Vcc < 2.9 V) /
100 MHz to 2000 MHz (RF : 2.9 V ≤ Vcc ≤ 3.3 V)
50 MHz to 600 MHz (IF)
Fractional-N function :
Modulo 1048576 (Σ∆ method)
:
Fractional-N, enabling high-speed PLL lock-up and low phase noise
Low voltage operation :
Vcc = 2.7 V to 3.3 V
Ultra Low power supply current : 6.1 mA Typ (RF) +1.4 mA (IF) Vcc = 3.0 V, Ta = + 25 °C, in locking state
Direct power saving function : Power supply current in power saving mode
(controllable in external pin) 0.1 µA Typ (Vcc = 3.0 V, Ta = + 25 °C)
10 µA Max (Vcc = 3.0 V)
Internal automatic switch changeover circuit (changeover time selectable)
Bit function to update the changeover time
Constant-current charge pump circuit capable of switching control of the current value through serial data control
or internal changeover circuit :
For steady-state operation: 94 µA
For high-speed changeover: 4.5 mA
(Continued)
• High frequency operation :
•
•
•
•
•
•
Copyright©2006 FUJITSU LIMITED All rights reserved
MB15F63UL
(Continued)
• Open-drain NMOS switch that can be turned on and off from the internal changeover circuit
• Prescaler division ratio : 2000 MHz prescaler (16/17/20/21) /600 MHz prescaler (8/9, 16/17)
• 29-bit shift register input control
• Serial input 14-bit programmable reference divider : Binary 6-bit 1 to 63 (RF side) / Binary 14-bit swallow
counter 3 to 16383 (IF side)
• Serial input programmable divider consisting of :
Binary 4-bit swallow counter 0 to 15 (RF side) / Binary 7-bit swallow counter 0 to 127 (IF side)
Binary 7-bit programmable counter 5 to 127 (RF side) /Binary 11-bit swallow counter 3 to 2047 (IF side)
• On-chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking
• Extended operating temperature : Ta = −40 °C to +85 °C
2
MB15F63UL
■ PIN ASSIGNMENTS
(TOP VIEW)
finIF
PSIF
17
OSCin
2
16
VccIF
GND
3
15
CLK
SW
4
14
Data
DoRF
5
13
LE
VPRF
6
12
VccRF
LD/fout
7
11
finRF
VPIF
1
DoIF
20
XfinIF
8
19
9
18
10
XfinRF
PSRF
GND
(LCC-20P-M06)
3
MB15F63UL
■ PIN DESCRIPTIONS
Pin no. Pin name
4
I/O
Descriptions
1
VPIF
⎯
Charge pump power supply for the IF-PLL
2
DoIF
O
Charge pump output for the IF-PLL
3
GND
⎯
Ground pin
4
SW
O
Open-drain switch pin for changing over the high-speed mode filter
5
DoRF
O
Charge pump output for the RF-PLL
6
VPRF
⎯
Power supply for the RF-PLL charge pump
7
LD/fout
O
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin.
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” : outputs fout signal/LDS bit = “L” : outputs LD signal
8
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited. )
PS = “H” : Normal mode/PS = “L” : Power saving mode
9
GND
⎯
10
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
11
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
12
VccRF
⎯
13
LE
I
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
14
Data
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
15
CLK
I
Clock input pin for the 29-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
16
VccIF
⎯
17
OSCin
I
The programmable reference divider input pin. TCXO should be connected with an
AC coupling capacitor.
18
XfinIF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
19
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
20
PSIF
I
Power saving mode control pin for the IF-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PS bit = “H” : Normal mode/PS bit = “L” : Power saving mode
Ground pin
Power supply pin for the RF-PLL
Power supply pin for the IF-PLL
MB15F63UL
■ BLOCK DIAGRAM
Prescaler
( IF )
8/9, 16/17
finIF 19
XfinIF 18
Programmable
Counter ( IF )
Lock
Detect ( IF )
11 bit latch
SWIF
Phase
Comparator
( IF )
Swallow
Counter ( IF )
VccIF 16
GND
1
VPIF
2
DoIF
7 bit latch
3
PSIF 20
Charge
Pump ( IF )
SWIF
PSIF
SW FC CS PS
IF IF IF IF
Reference
Counter ( IF )
14 bit latch
26-bit Shift
Register
OSCin
17
24 bit CN1 CN2
LDIF
LD
frIF
fpIF
fpRF
frRF
finRF 11
XfinRF 10
Prescaler
( RF )
16/17/20/21
Sigma Delta
Fractional
Modulation
Programmable
Counter ( RF )
Swallow
Counter ( RF )
GND
9
13 LE
7
LD/fout
Phase
Comparator
( RF )
Charge
Pump ( RF )
6
VPRF
5
DoRF
4
SW
4 bit latch
Reference
Counter ( RF )
12
15 CLK
Lock
Detect ( RF )
7 bit latch
20 bit latch
VccRF
LDRF
Selector
14 Data
PSRF FCRF
2 bit latch
2 bit latch
Timer
TMC,TM1-7
PSRF
8
PSRF
SW
control
ODSW
5
MB15F63UL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Min
Max
Vcc
− 0.5
+ 3.6
V
Vp
Vcc
3.6
V
VI
− 0.5
Vcc + 0.5
V
LD/fout
VO
GND
Vcc
V
Do
VDO
GND
Vp
V
Tstg
− 55
+125
°C
Power supply voltage
Input voltage
Output voltage
Rating
Symbol
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Rating
Unit
Min
Typ
Max
Vcc
2.7
3.0
3.3
V
Vp
Vcc
⎯
3.3
V
Input voltage
VI
GND
⎯
Vcc
V
Operating temperature
Ta
−40
⎯
+85
°C
Power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB15F63UL
■ ELECTRICAL CHARACTERISTICS
(Vcc = 2.7 V to 3.3 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Power supply current
Power saving current
IF 3
fin *
finRF*3
IccIF*1
finIF
Unit
Min
Typ
Max
IF-PLL section
⎯
1.4
3.0
mA
Icc *
RF-PLL section
⎯
6.1
10.0
mA
IF-PLL section
⎯
0.1*9
10
µA
IpsRF*10
RF-PLL section
⎯
0.1*9
10
µA
finIF
IF-PLL section
50
⎯
600
MHz
RF-PLL section
(2.7 V ≤ Vcc < 2.9 V)
100
⎯
1800
MHz
RF-PLL section
(2.9 V ≤ Vcc ≤ 3.3 V)
100
⎯
2000
MHz
Reference counter setting
value : R = 1
5
⎯
20
MHz
Reference counter setting
value : 2 ≤ R ≤ 63
5
⎯
40
MHz
IF-PLL section
50 Ω termination
−15
⎯
+2
dBm
RF-PLL section
50 Ω termination
(fin = 200 MHz to 2000 MHz)
−15
⎯
+2
RF-PLL section
50 Ω termination
(fin = 100 MHz to 200 MHz)
−10
⎯
+2
⎯
0.5
⎯
1.5
Vp-p
0.4
⎯
20
MHz
finRF
fosc
PfinIF
Input sensitivity
finRF
Value
IpsIF*10
RF 2
Operating
frequency
OSCin
Condition
PfinRF
dBm
Input available
OSCin
voltage
VOSC
Operating frequency of
phase comparator
fMAIN_PD
RF-PLL section
“H” level input
voltage
VIH
Schmitt trigger input
0.7 Vcc + 0.4
⎯
⎯
V
VIL
Schmitt trigger input
⎯
⎯
0.3 Vcc − 0.4
V
“L” level input
voltage
“H” level input
voltage
“L” level input
voltage
“H” level input
current
“L” level input
current
“H” level output
voltage
“L” level output
voltage
Data,
LE,
CLK
PSIF,
PSRF
Data,
LE,
CLK
VIH
⎯
0.7 Vcc
⎯
⎯
V
VIL
⎯
⎯
⎯
0.3 Vcc
V
IIH*4
⎯
−1.0
⎯
+1.0
µA
IIL*4
⎯
−1.0
⎯
+1.0
µA
Vcc − 0.4
⎯
⎯
V
⎯
⎯
0.4
V
VOH
Vcc = 3.0 V, IOH = −1 mA
VOL
Vcc = 3.0 V, IOL = 1 mA
LD/fout
(Continued)
7
MB15F63UL
(Vcc = 2.7 V to 3.3 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
VDOH
VccIF = VPIF = 3.0 V,
IDOH = −0.5 mA
Vp − 0.4
⎯
⎯
V
VDOL
VccIF = VPIF = 3.0 V,
IDOL = 0.5 mA
⎯
⎯
0.4
V
VDOH
VccRF = VPRF = 3.0 V,
IDOH = −0.01 mA
Vp − 0.4
⎯
⎯
V
VDOL
VccRF = VPRF = 3.0 V,
IDOL = 0.01 mA
⎯
⎯
0.4
V
IOFF
Vcc = Vp = 3.0 V,
VOFF = 0.5 V to Vcc−0.5 V
⎯
⎯
2.5
nA
IOH*4
Vcc = 3.0 V
⎯
⎯
−1.0
mA
IOL
Vcc = 3.0 V
1.0
⎯
⎯
mA
“H” level output
current
IDOH*4
−2.2
−1.5
−0.8
mA
“L” level output
current
IDOL
VccIF = VPIF = 3.0 V,
VDoIF = VPIF/2
CSIF = “L”, Ta = + 25 °C
+0.8
+1.5
+2.2
mA
VccIF = VPIF = 3.0 V,
VDoIF = VPIF/2
CSIF = “H”, Ta = + 25 °C
−8.2
−6.0
−4.1
mA
+4.1
+6.0
+8.2
mA
VccRF = VPRF = 3.0 V,
VDoRF = VPRF/2
In steady state (locking state) :
Ta = + 25 °C
−160
−94
−40
µA
+40
+94
+160
µA
VccRF = VPRF = 3.0 V,
VDoRF = VPRF/2 channels in
changeover : Ta = + 25 °C
−6.1
−4.5
−2.4
mA
+2.4
+4.5
+6.1
mA
VDO = Vp/2
⎯
3
⎯
%
0.5V ≤ VDO ≤ Vcc − 0.5 V
⎯
10
⎯
%
−40 °C ≤ Ta ≤ + 85 °C,
VDO = Vcc/2
⎯
5
⎯
%
VDO = Vp/2
⎯
8.0
15.0
%
100
⎯
⎯
kΩ
⎯
35
70
Ω
“H” level output
voltage
“L” level output
voltage
“H” level output
voltage
“L” level output
voltage
High impedance
cutoff current
“H” level output
current
“L” level output
current
“H” level output
current
DoIF
DoRF
DoIF
DoRF
LD/fout
DoIF
IDOH*4
“L” level output
current
IDOL
“H” level output
current
IDOH*4
“L” level output
current
IDOL
“H” level output
current
DoRF
IDOH*4
“L” level output
current
IDOL
IDOL/IDOH IDOMT*5
Charge
DoIF
pump
current rate
vs. VDo I
vs. Ta
DOVD 6
*
IDOTA*7
DoRF IDOL/IDOH IDOMT*8
Open-drain output resistance
ZSSH
for high-speed (SW)
At normal mode (OFF)
At high-speed mode (ON)
*1 : finIF = 190 MHz, fosc = 19.2 MHz, frIF = 100 kHz, VCCIF = VPIF = 3.0 V, Ta = + 25 °C, in locking state.
*2 : finRF = 1600 MHz, fosc = 19.2 MHz, frRF = 19.2 MHz, VCCRF = VPRF = 3.0 V, Ta = + 25 °C, in locking state.
(Continued)
8
MB15F63UL
(Continued)
*3 : AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4 : The symbol “−” means direction of current flow.
*5 : Vcc = Vp = 3.0 V, Ta = +25 °C
(||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100%
*6 : Vcc = Vp = 3.0V, Ta = +25 °C (IDOL, IDOH respectively)
[ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100%
*7 : Vcc = Vp = 3.0V, Ta = +25 °C (IDOL, IDOH respectively)
[ (||IDO (85c) | − |IDO (−40c) ||) / 2] / [ (|IDO (85c) | + |IDO (−40C) |) / 2] × 100%
*8 : VCC = Vp = 3.0 V, Ta = +25 °C (||IDOL| − |IDOH||) / [ (|IDOL| + |IDOH|) / 2] × 100%
*9 : Power supply current at PS = GND (Data, LE and CLK are VIL = GND and VIH = Vcc setting.)
*10 : Power supply current at fosc = 19.2 MHz, VCC = VP = 3.0 V, Ta = +25 °C, PS = GND (Data, LE and CLK are
VIL = GND, VIH = Vcc setting.)
I2
I1
I3
IDOL
IDOH
I1
I2
0.5 V
I4
Vp/2
Vp − 0.5 V
Vp
Charge pump output potential [V]
9
MB15F63UL
■ FUNCTIONAL DESCRIPTION
1. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data.
The following table shows the shift register configuration and combinations of data transfer control bits.
LSB
Destination of serial data
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
0
0
0
1
1
0
1
1
R1
IF
A1
IF
F1
RF
N4
RF
R2
IF
A2
IF
F2
RF
N5
RF
R3
IF
A3
IF
F3
RF
N6
RF
R4
IF
A4
IF
F4
RF
N7
RF
R5
IF
A5
IF
F5
RF
R1
RF
R6
IF
A6
IF
F6
RF
R2
RF
R7
IF
A7
IF
F7
RF
R3
RF
R8
IF
N1
IF
F8
RF
R4
RF
R9
IF
N2
IF
F9
RF
R5
RF
R10 R11 R12 R13 R14 CS SW FC LD
T1 T2 ×
IF IF IF IF IF IF IF IF S
N3 N4 N5 N6 N7 N8 N9 N10 N11 PS
× ×
IF IF IF IF IF IF IF IF IF IF
F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 A1
RF RF RF RF RF RF RF RF RF RF RF RF
R6 FC TM TM TM TM TM TM TM TM
OD
×
RF RF C 1 2 3 4 5 6 7
SW
×
×
×
×
×
×
×
×
×
×
×
×
A2 A3 A4 N1 N2 N3
RF RF RF RF RF RF
PS
SC × × × ×
RF
Note : Start data input with MSB first.
2. Setting data
a) Fractional-N Synthesizer in the RF-PLL section
Set each setting value for the Fractional-N Synthesizer counter, according to the following equations.
fvcoRF = NTOTAL × fOSC ÷ R
NTOTAL = P × N + A + 3 + F/Q
F: Set the numerator of fractional division with its fractional portion discarded.
When value F is even-numbered as a result of the division calculation, “1” is added to F.
b) Integer-N Synthesizer in the IF-PLL section
The Integer-N Synthesizer counter is set, according to the following equations.
fvcoIF = NTOTAL × fOSC ÷ R
NTOTAL = P × N + A
10
fvcoRF/fvcoIF
NTOTAL
fosc
R
:
:
:
:
P
:
N
:
A
:
F
Q
:
:
Output frequency of externally connected VCO
Total number of divisions from prescaler input to phase comparator input
Reference oscillation frequency (OSCin input frequency)
RF side : Setting value for binary 6-bit reference counter (1 to 63)
IF side : Setting value for binary 14-bit reference counter (1 to 16383)
RF side : Division ratio for prescaler (16)
IF side : Division ratio for prescaler (8, 16)
RF side : Setting value for binary 7-bit programmable counter (5 to 127)
IF side : Setting value for binary 11-bit programmable counter (3 to 2047)
RF side : Setting value for binary 4-bit swallow counter (0 to 15)
IF side : Setting value for binary 4-bit swallow counter (0 to 127, A < N)
Numerator of fractional division (0 to 1048575, F < Q)
Denominator of fractional division (220 = 1048576)
MB15F63UL
c) Data bit description
Bit name
Description
F1RF to F20RF
Bits for setting the fractional numerator for the RF-PLL (Setting range: 0 to 1048575)
(Refer to Table 1)
A1RF to A4RF
Bits for setting the division ratio of the RF-side swallow counter (Setting range: 0 to 15)
(Refer to Table 2)
N1RF to N7RF
Bits for setting the RF-side main counter (Setting range: 5 to 127) (Refer to Table 3)
R1RF to R6RF
Bits for setting the division ratio of the RF-side reference counter (Setting range: 1 to 63)
(Refer to Table 4)
A1IF to A7IF
Bits for setting the division ratio of the IF-side swallow counter (Setting range: 0 to 127)
(Refer to Table 5)
N1IF to N11IF
Bits for setting the IF-side main counter (Setting range: 3 to 2047) (Refer to Table 6)
R1IF to R14IF
Bits for setting the division ratio of the IF-side reference counter (Setting range: 3 to 16383)
(Refer to Table 7)
TMC
Control bit for setting Speedup Mode (Refer to Table 9)
TMC_bit = “0”→ disabled
TMC_bit = “1”→ enabled
TM1 to TM7
Bits for setting the speedup timer (Refer to Table 8)
PSRF
Power saving bit for the RF-PLL section
FCRF
Phase switching bit for the RF-side phase comparator (Refer to Table 11)
ODSW
Control bit for the open-drain switch
ODSW bit = “0”→Dynamic
ODSW bit = “1”→OFF
FCIF
Phase switching bit for the IF-side phase comparator (Refer to Table 11)
CSIF
Charge pump switching bit for the IF-PLL section
CSIF bit = “0”→ Icp = ±1.5mA
CSIF bit = “1”→ Icp = ±6.0mA
SWIF
Bits for setting the division ratio of the IF-side prescaler
SWIF = “0”→ 16/17
SWIF = “1”→ 8/9
PSIF
Power saving bit for the IF-PLL section
LDS, T1, T2
Control bits for selecting monitor function (Refer to Table 10)
SC
Bit for switching the order of Σ∆
SC bit = “0”→ 2nd order
SC bit = “1”→ 3rd order
×
Dummy bit: Must be fixed to “0”
11
MB15F63UL
Table 1 - Fractional counter F numerator value Setting
Setting value F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
(F)
RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
•
••
•
••
1048574
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1048575
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 2 - Swallow counter setting
Table 3 - Main counter setting
Setting value A4 A3 A2 A1
(A)
RF RF RF RF
0
0
0
0
0
5
0
0
0
0
1
0
1
1
0
0
0
1
6
0
0
0
0
1
1
0
••
•
••
•
••
•
••
•
14
1
1
1
0
126
1
1
1
1
1
1
0
15
1
1
1
1
127
1
1
1
1
1
1
1
Table 4 - Reference counter setting
Table 5 - Swallow counter setting
Setting value R6 R5 R4 R3 R2 R1
RF RF RF RF RF RF
(R)
Setting value A7 A6 A5 A4 A3 A2 A1
(A)
IF IF IF IF IF IF IF
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
2
0
0
0
0
1
0
1
0
0
0
0
0
0
1
•
••
12
Setting value N7 N6 N5 N4 N3 N2 N1
(N)
RF RF RF RF RF RF RF
•
••
•
••
•
••
62
1
1
1
1
1
0
126
1
1
1
1
1
1
0
63
1
1
1
1
1
1
127
1
1
1
1
1
1
1
MB15F63UL
Table 6 - Main counter setting
Setting value N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
(N)
IF IF IF IF IF IF IF IF IF IF IF
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Table 7 - Reference counter setting
Setting value R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
(R)
IF IF IF IF IF IF IF IF IF IF IF IF IF IF
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
••
•
••
•
16382
1
1
1
1
1
1
1
1
1
1
1
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 8 - Speedup timer update value setting
Setting value
1
TM TM TM TM TM TM TM
7 6 5 4 3 2 1
0
0
0
•
•
•
0
0
0
1
•
•
•
case) fosc = 19.2 MHz
3.3
Charge pump current switching time =
64/fosc × TM
•
•
•
126
1
1
1
1
1
1
0
420.0
127
1
1
1
1
1
1
1
423.3
unit:µs
Table 9 - Charge pump output current setting
Charge pump output current
TMC
± 0.094 mA fixed
0
± 4.5 mA → ± 0.094 mA switched
1
13
MB15F63UL
Table 10 - LD/fout output setting
LD/fout
LDS
T1
T2
Maximum operating
frequency [MHz]*
LD output
0
⎯
⎯
1800
frIF
1
0
0
frRF
1
1
0
fpIF
1
0
1
fpRF
1
1
1
fout
2000
* : The maximum operating frequency varies depending on the output state of the LD/fout pin (LD output or fout
output).
Table 11 - Comparator polarity setting
FC = “1”
FC = “0”
Do
Do
fp < fr
H
L
fr < fp
L
H
fr = fp
Z
Z
VCO Polarity
(1)
(2)
Note : Set the FC bit in accordance with the low pass filter and VCO polarity, when designing a PLL frequency
synthesizer.
high
When VCO is (1)
FC : “H”
When VCO is (2)
FC : “L”
(1)
VCO
output
Frequency
(2)
high
VCO Input Voltage
14
MB15F63UL
3. Power Saving Mode (Intermittent Operation)
PSIF
ExternalPIN
SerialData
0
0
0
IFPLL
PSRF
RFPLL
ExternalPIN
SerialData
Power save
0
0
Power save
1
Power save
0
1
Power save
1
0
Power save
1
0
Power save
1
1
Active
1
1
Active
The intermittent operation allows internal circuits to operate only when required and to stop otherwise. It is
designed to control the power consumed by the entire circuit block. However, if the circuit starts operating directly
from a stop state, the phase relation is undefined, even when the comparison frequency (fp) is the same as the
reference frequency (fr) input to the phase comparator. As a result, the phase comparator generates excessive
error signals, causing the problem of unlocking the PLL. To solve this problem, the intermittent operation control
has been implemented to control fluctuations in the locked frequency by performing forcible phase adjustment
at the beginning of operation.
• Operation mode
The set channel and crystal oscillator circuit are in operation and the PLL performs normal operation.
• Power save mode
This mode realizes low current consumption by stopping the circuits which will not cause any problem even when
stopped. In this condition, the standard consumption current is 0.1 µA per channel with the maximum of 10 µA.
At this point, Do and LD are set to the same levels as when the PLL was locked. The Do enters a high impedance
state, and the voltage input to the voltage control oscillator (VCO) remains the same as the voltage for operation
mode (i.e. locked state) with the time constant of the low pass filter. Therefore, the VCO output frequency can
be maintained almost at the same level as the lock frequency.
Notes : • When power (VCC) is first applied, the device must be in power saving mode (external pin = L, due to the
undefined serial data) .
• The serial data input after the power supply became stable, and then the power saving mode is released
after completed the data input.
OFF
ON
VCC
tv ≥ 1 µs
CLK
Data
LE
tps ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H)
15
MB15F63UL
4. Serial Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st. data
2nd. data
Control bit
Invalid data
∼
Data
MSB
LSB
∼
∼
CLK
t1
LE
t0
t2
t5
t4
∼
t3
100 ns ≤ t0, t6
20 ns ≤ t1, t2, t4
30 ns ≤ t3, t5
LE should be “L” when the data is transferred into the shift register.
16
t6
MB15F63UL
■ PHASE COMPARATOR OUTPUT WAVEFORM
frRF
fpRF
tWU
tWL
LD
(FC bit = “H”)
DoRF
(FC bit = “L”)
DoRF
• LD Output Logic
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes : • Phase error detection range : −2π to +2π
• Pulses on Do signal during locked state are output to prevent dead zone.
RF-PLL section :
• LD output becomes “L” when phase is tWU or more. LD output becomes “H” when phase error is
tWL or less and continues to be so for ten cycles or more.
• tWU and tWL depend on fin input frequency.
ex.) fin = 1629.9 MHz : tWU ≥ 9.82 ns
tWU ≥ 1 / (fin / 16) [s]
tWL ≤ 2 / (fin / 16) [s]
: tWL ≤ 19.63 ns
IF-PLL section
• LD output becomes “L” when phase is tWU or more. LD output becomes “H” when phase error
is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency.
tWU ≥ 2 / fosc [s]
ex.) fosc = 13.0 MHz : tWU ≥ 153 ns
: tWL ≤ 256 ns
tWL ≤ 4 / fosc [s]
17
MB15F63UL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCCIF
S.G
1000 pF
Controller
(setting divide ratio)
50 Ω
VCCRF
LE
Data
0.1 µF
CLK
S.G
1000 pF
50 Ω
finRF
OSCin
17
16
15
14
13
12
11
XfinIF
10
18
XfinRF
1000 pF
S.G
finIF
1000 pF
MB15F63UL
19
9
Bump Chip Carrier-20
PSIF
50 Ω VCCIF
GND
VCCRF
20
8
PSRF
VPIF
LD/fout
1
2
DoIF
0.1 µF
3
4
5
SW DoRF
6
7
VPRF
GND
0.1 µF
18
Oscilloscope
MB15F63UL
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
RF input sensitivity − Input frequency
10
RF input sensitivity (dBm)
5
0
−5
SPEC
−10
−15
−20
−25
−30
−35
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
−40
−45
−50
0
500
1000
1500
2000
2500
3000
Input frequency (MHz)
IF input sensitivity − Input frequency
10
5
IF input sensitivity (dBm)
0
−5
SPEC
−10
−15
−20
−25
−30
−35
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
−40
−45
−50
0
500
1000
1500
Input frequency (MHz)
19
MB15F63UL
2. OSCin Input Sensitivity
OSCin input sensitivity − Input frequency
10
OSCin input sensitivity (dBm)
5
SPEC
0
−5
−10
−15
−20
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
−25
−30
0
10
20
30
40
50
60
Input frequency (MHz)
20
70
80
90
100
MB15F63UL
3. RF Do output current
• CP = 94 µA
IDO − VDO
Charge pump output current IDO (µA)
200
0.0
VCCRF = VPRF = 3.0 V
−200
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
• CP = 4.5 mA
IDO − VDO
Charge pump output current IDO (mA)
6.0
0.0
VCCRF = VPRF = 3.0 V
−6.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
21
MB15F63UL
4. IF Do output current
• CP = 1.5 mA
IDO − VDO
Charge pump output current IDO (mA)
2.0
0.0
VCCIF = VPIF = 3.0 V
−2.0
0.0
2.0
1.0
3.0
Charge pump output voltage VDO (V)
• CP = 6 mA
IDO − VDO
Charge pump output current IDO (mA)
7.0
0.0
VCCIF = VPIF = 3.0 V
−7.0
0.0
1.0
2.0
Charge pump output voltage VDO (V)
22
3.0
MB15F63UL
5. fin input impedance
finIF input impedance
4 : 6.2119 Ω
−21.005 Ω
12.628 pF
600.000 000 MHz
1 : 82.813 Ω
−246.07 Ω
100 MHz
2 : 22.242 Ω
−117.85 Ω
200 MHz
3 : 7.8457 Ω
−49.664 Ω
400 MHz
1
4
2
3
START 100.000 000 MHz
STOP 600.000 000 MHz
finRF input impedance
4 : 12.429 Ω
2.9873 Ω
237.72 pH
2 000.000 000 MHz
1 : 32.969 Ω
−153.25 Ω
500 MHz
2 : 17.539 Ω
−65.531 Ω
1 GHz
3 : 18.783 Ω
−26.514 Ω
1.5 GHz
4
1
3
2
START 100.000 000 MHz
STOP 2 000.000 000 MHz
23
MB15F63UL
6. OSCin input impedance
4 : 195.13 Ω
−3.0835 kΩ
2.5808 pF
20.000 000 MHz
1 : 4.116 kΩ
−10.916 kΩ
5 MHz
2:
996 Ω
−6.3023 kΩ
10 MHz
4
321
START 5.000 000 MHz
24
STOP 20.000 000 MHz
3 : 195.13 Ω
−3.0835 kΩ
20 MHz
MB15F63UL
■ REFERENCE INFORMATION
S.G.
OSCin
fvco = 800 MHz Vcc = Vp = 3.0 V
Kv = 25 MHz/V
Vvco = 5.0 V
fr = 6.5 MHz (R = 2) Ta = + 25 °C
fosc = 13.0 MHz TMC = “1”, TM = “4”
CS = “0”, ODSW = “0”, SC = “1”, MODE = “0”
Do
LPF
fin
SW
Do
Spectrum
Analyzer
VCO
VCO
2200 pF
10000 pF
0.62 kΩ
3.6 kΩ
SW
• PLL Phase Noise & Spurious Noise
C/N 1 kHz Offset
ATTEN 10 dB
RL 0 dBm
D
S
VAVG 20
10 dB/
C/N 200 kHz Offset
∆ MKR −88.56 dB/Hz
1.00 kHz
∆ MKR
1.00 kHz
−88.56 dB/Hz
ATTEN 10 dB
RL 0 dBm
D
S
CENTER 800.00000 MHz
VBW 100 Hz
RBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
VAVG 20
10 dB/
∆ MKR −116.8 dB/Hz
200.0 kHz
∆ MKR
200.0 kHz
−116.8 dB/Hz
CENTER 800.0000 MHz
SPAN 500.0 kHz
VBW 1.0 kHz
∗RBW 1.0 kHz
SWP 1.30 s
Ref. Leakage 6.5 MHz Offset
ATTEN 10 dB
RL 0 dBm
D
S
VAVG 20
10 dB/
∆ MKR −82.17 dB
6.50 MHz
∆ MKR
6.50 MHz
−82.17 dB
CENTER 812.50 MHz
VBW 30 kHz
∗RBW 30 kHz
SPAN 15.00 MHz
SWP 50.0 ms
25
MB15F63UL
PLL Lock Up time
L : 800 MHz → H : 835 MHz ± 1 kHz
L ch → H ch 373 µs
835.004000 MHz
835.000000 MHz
834.996000 MHz
0.00 s
500.0 µs
100.0 µs/div
1.000 ms
PLL Lock Up time
H : 835 MHz → L : 800 MHz ± 1 kHz
H ch → L ch 364 µs
800.004000 MHz
800.000000 MHz
799.996000 MHz
0.00 s
26
500.0 µs
100.0 µs/div
1.000 ms
MB15F63UL
■ APPLICATION EXAMPLE
18 Ω
Output
18 Ω
LPFRF
VCCIF
VCO, RF-PLL
18 Ω
Controller
(setting divide ratio)
0.1 µF
VCCRF
LE
Data
0.1 µF
CLK
OSCin
TCXO
finRF
17
16
15
14
13
12
11
1000 pF
XfinIF
XfinRF
18
10
1000 pF
1000 pF
finIF
MB15F63UL
19
9
Bump Chip Carrier-20
GND
VCCIF
VCCRF
PSIF
Output
20
8
PSRF
18 Ω
18 Ω
VPIF
1
2
3
5
6
7
LD/fout
VPRF
SW
DoIF
18 Ω
4
0.1 µF
0.1 µF
Lock Det.
GND
LPFIF
DoRF
VCO, IF-PLL
Note : CLK, Data and LE are the built-in schmitt trigger circuits (insert a pull-down or pull-up register to prevent
oscillation when open-circuit in the input) .
27
MB15F63UL
■ PRECAUTIONS FOR USE
The Fractional-N PLL used in the RF section is based on the Σ∆ system and has the following characteristics.
(1) Integer operation when F = 0
When F is set to “0”, the Σ∆ circuit block is stopped completely and the same operation as a normal Integer
product is performed. Therefore, the most preferable noise characteristics can be achieved.
(2) Generation of spurious signals
1.Spurious signals are generated in the offset part of fp, which is a comparison frequency (equivalent of a
reference leak in the integer type).
Example:
If fosc is set to 13 MHz and R is set to 2 when fvco is 800 MHz in the GSM 800 MHz band, Ntotal becomes
124 and F becomes 0. (Integer mode)
Spurious signals are generated at “fp / R = 13 MHz / 2 = 6.5 MHz” offset. (Reference leak)
(The waveform resembles that of the reference leakage shown on Ref Leakage of “REFERENCE INFORMATION”. A filter can be used to eliminate the
effects.)
2. Due to the Σ∆ circuit operation, spurious signals are generated where “F / Q × fp” or “(Q − F) / Q × fp”
is located.
Example:
fosc = 13 MHz; R = 2 in GSM 800 MHz band:
When fvco is 806.2 MHz, Ntotal becomes 142.0307692... and F becomes 32263. Consequently, spurious
signals are generated at “F / Q × fp =: 200 kHz” offset.
C/N 200 kHz Offset
ATTEN 10 dB
RL 0 dBm
D
S
VAVG 20
10 dB/
∆ MKR −82.50 dB
200.0 kHz
∆ MKR
200.0 kHz
−82.50 dB
CENTER 806.2000 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
SPAN 500.0 kHz
SWP 1.30 s
Adjusting the filter may reduce these spurious signals. Furthermore, modifying R and fr may change the setting
value to avoid to generate spurious signals.
For example, when fosc = 13 MHz and R = 2, Ntotal becomes 125.0307692…, where fvco is 812.7 MHz.
Therefore, F becomes 32263. Spurious signals are supposed to be generated at “F / Q × fp =: 200 kHz” and
200 kHz offset. However, if R is changed to 3, F will become 572683 and “F / Q × fp =: 2.366 MHz” and
spurious signals will be the outer frequencies. Therefore, the effects will not be foreseen.
28
MB15F63UL
Note that the problem cannot be avoided when the setting value of the swallow counter (A) is odd-numbered
(also applicable to the 806.2 MHz environment, used in the above explanation).
However, the spurious signals can be reduced by changing fr (reducing it) to limit the band. Note that in this
case, the comparison frequency itself changes, resulting in a change in the loop band and deterioration of CN.
Therefore,each case should be handled in accordance with the system used. Some example waveforms are
attached to the following.
29
MB15F63UL
R = 2 (200 kHz offset)
ATTEN 10 dB
RL 0 dBm
VAVG 20
10 dB/
∆ MKR −89.50 dB
200.0 kHz
∆ MKR
200.0 kHz
D −89.50 dB
S
R = 3 (200kHz offset)
ATTEN 10 dB
RL 0 dBm
∆ MKR −90.83 dB
200.0 kHz
∆ MKR
200.0 kHz
D −90.83 dB
S
CENTER 812.7000 MHz
VBW 1.0 kHz
∗RBW 1.0 kHz
SPAN 500.0 kHz
SWP 1.30 s
CENTER 812.7000 MHz
VBW 1.0 kHz
∗RBW 1.0 kHz
R = 2 (loop band waveform)
ATTEN 10 dB
RL 0 dBm
VAVG 20
10 dB/
∆ MKR −3.00 dB
12.00 kHz
∆ MKR
12.00 kHz
D −3.00 dB
S
R = 3 (loop band waveform)
ATTEN 10dB
RL 0 dBm
SPAN 50.00 kHz
SWP 1.40 s
VAVG 20
10 dB/
∆ MKR −3.00 dB
10.08 kHz
CENTER 812.70000 MHz
VBW 300 Hz
RBW 300 Hz
R = 2 (1kHz offset)
ATTEN 10dB
RL 0 dBm
SPAN 500.0 kHz
SWP 1.30 s
∆ MKR
10.08 kHz
D −3.00 dB
S
CENTER 812.70000 MHz
VBW 300 Hz
RBW 300 Hz
VAVG 20
10 dB/
∆ MKR −89.23 dB/Hz
1.00 kHz
∆ MKR
1.00 kHz
D −89.23 dB/Hz
S
CENTER 812.70000 MHz
VBW 100 Hz
RBW 100 Hz
30
VAVG 20
10 dB/
SPAN 50.00 kHz
SWP 1.40 s
R = 3 (1kHz offset)
ATTEN 10 dB
RL 0 dBm
VAVG 20
10 dB/
∆ MKR −82.57 dB/Hz
1.00 kHz
∆ MKR
1.00 kHz
D −82.57 dB/Hz
S
SPAN 10.00 kHz
SWP 802 ms
CENTER 812.70000 MHz
VBW 100 Hz
RBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
MB15F63UL
3. Excessive spurious signals are generated when setting a binary division such as F/Q = 1/2, 1/4, 1/8…
If it is difficult to reduce the excess level, value F can be shifted to the acceptable range of frequency differences
to reduce it.
Example:
Spurious noise is generated on the entire floor when F = 524288 (F/Q = 1/2).
Spurious noise is generated on the entire floor when F = 262144 (F/Q = 1/4).
The following section shows examples of spurious waveforms generated in the above cases as well as
examples of waveforms when 5 and 10 are added to value F.
31
MB15F63UL
F = 524288(F/Q = 1/2)
ATTEN 10 dB
RL 0 dBm
D
S
10 dB/
F = 262144(F/Q = 1/4)
MKR −8.83 dBm
809.2500 MHz
MKR
809.2500 MHz
−8.83 dBm
ATTEN 10dB
RL 0 dBm
D
S
CENTER 809.2500 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
SPAN 200.0 kHz
∗SWP 500 ms
D
S
10 dB/
CENTER 807.6250 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
MKR
809.2500 MHz
−8.50 dBm
ATTEN 10 dB
RL 0 dBm
D
S
SPAN 200.0 kHz
SWP 500 ms
D
S
10 dB/
32
MKR −8.67 dBm
807.6250 MHz
CENTER 807.6250 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
SPAN 200.0 kHz
SWP 500 ms
F = 262144 + 10
MKR −9.17 dBm
809.2500 MHz
ATTEN 10 dB
RL 0 dBm
10 dB/
MKR −9.17 dBm
807.6250 MHz
MKR
807.6250 MHz
D −9.17 dBm
S
MKR
809.2500 MHz
−9.17 dBm
CENTER 809.2500 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
10 dB/
MKR
807.6250 MHz
−8.67 dBm
F = 524288 + 10
ATTEN 10 dB
RL 0 dBm
SPAN 200.0 kHz
∗SWP 500 ms
F = 262144 + 5
MKR −8.50 dBm
809.2500 MHz
CENTER 809.2500 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
MKR −8.50 dBm
807.6250 MHz
MKR
807.6250 MHz
−8.50 dBm
F = 524288 + 5
ATTEN 10 dB
RL 0 dBm
10 dB/
SPAN 200.0 kHz
∗SWP 500 ms
CENTER 807.6250 MHz
∗VBW 3.0 kHz
∗RBW 1.0 kHz
SPAN 200.0 kHz
SWP 500 ms
MB15F63UL
Notes : • VCCRF and VCCIF must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep
them equal. It is recommended that the non-use PLL is controlled by power saving function.
• To protect against damage by electrostatic discharge, note the following handling precautions :
- Store and transport devices in conductive containers.
- Use properly grounded workstations, tools, and equipment.
- Turn off power before inserting device into or removing device from a socket.
- Protect leads with a conductive sheet when transporting a board-mounted device.
33
MB15F63UL
■ ORDERING INFORMATION
Part number
MB15F63ULPVA1
34
Package
20-pin, Plastic BCC
(LCC-20P-M06)
Remarks
MB15F63UL
■ PACKAGE DIMENSIONS
20-pin plastic BCC
Lead pitch
0.50 mm
Package width ×
package length
3.50 mm × 3.50 mm
Sealing method
Plastic mold
Mounting height
0.60 mm MAX
Weight
0.01 g
(LCC-20P-M06)
20-pin plastic BCC
(LCC-20P-M06)
3.00(.118)REF.
0.55±0.050
(.022±.0020)
Mount height
3.50±0.10
(.138±.004)
0.50±0.10
(.020±.004)
11
17
0.50(.020)
TYP
11
0.50(.020)
TYP.
2.90(.114)
TYP.
INDEX AREA
3.50±0.10
(.138±.004)
2.90(.114)
TYP.
7
0.075±0.025
(.003±.001)
(Stand off)
7
0.14(.006)
MIN
Details of "B" part
0.40±0.06
(.016±.002)
0.40±0.06
(.016±.002)
0.30±0.06
(.012±.002)
0.20(.008)
0.05(.002)
0.30±0.06
(.012±.002)
2004 FUJITSU LIMITED C20057S-c-1-1
1PIN INDEX
"B"
1.55(.061)
1
Details of "A" part
C
0.95
(.037)
"A"
1.00(.004)
REF.
1
17
0.20(.008)
1PIN INDEX
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
35
MB15F63UL
FUJITSU LIMITED
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Edited
Business Promotion Dept.
F0610