FUJITSU SEMICONDUCTOR DATA SHEET DS04-21369-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F78UL ■ DESCRIPTION The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 4.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The data format is the same as the previous one MB15F08SL, MB15F78SP. Fast locking is achieved for adopting the new circuit. The new package (BCC20) decreases a mount area of MB15F78UL more than 30% comparing with the former BCC16 (for dual PLL) . MB15F78UL is ideally suited for wireless mobile communications, such as GSM and PCS. ■ FEATURES • High frequency operation : RX synthesizer : 2600 MHz Max. : TX synthesizer : 1200 MHz Max. • Low power supply voltage : VCC = 2.4 to 3.6 V • Ultra low power supply current : ICC = 4.5 mA Typ. (VCC = Vp = 2.7 V, Ta = +25 °C, SWTX = SWRX = 0, in TX/RX locking state) (Continued) ■ PACKAGES 20-pin plastic TSSOP 20-pad plastic BCC (FPT-20P-M06) (LCC-20P-M05) MB15F78UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C) Max. 10 µA (VCC = Vp = 2.7 V) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ. • Dual modulus prescaler : 2600 MHz prescaler (32/33 or 64/65) /1200 MHz prescaler (16/17 or 32/33) • 23-bit shift register • Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 • Serial input programmable divider consisting of : - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 • Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit • On-chip phase control for phase comparator • On-chip phase comparator for fast lock and low noise • Built-in digital locking detector circuit to detect PLL locking and unlocking • Operating temperature : Ta = −40 to +85 °C • Serial data format compatible with MB15F08SL ■ PIN ASSIGNMENTS (TSSOP-20) TOP VIEW (BCC-20) TOP VIEW OSCIN 1 20 Clock GND 2 19 Data finTX 3 18 LE XfinTX 4 17 finRX GNDTX 5 16 XfinRX VCCTX 6 15 GNDRX PSTX 7 14 VCCRX VpTX 8 13 PSRX DoTX 9 12 VpRX LD/fout 10 11 DoRX (FPT-20P-M06) 2 OSCIN Data GND Clock finTX 1 XfinTX 2 GNDTX VCCTX 3 4 PSTX 5 VpTX 6 20 19 18 17 16 15 14 13 12 7 8 9 10 11 DoRX DoTX LD/fout VpRX (LCC-20P-M05) LE finRX XfinRX GNDRX VCCRX PSRX MB15F78UL ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions TSSOP BCC 1 19 OSCIN 2 20 GND 3 1 finTX I Prescaler input pin for the TX-PLL. Connection to an external VCO should be via AC coupling. 4 2 XfinTX I Prescaler complimentary input pin for the TX-PLL section. This pin should be grounded via a capacitor. 5 3 GNDTX 6 4 VCCTX Power supply voltage input pin for the TX-PLL section (except for the charge pump circuit) , the oscillator input buffer and the shift register. 7 5 PSTX I Power saving mode control pin for the TX-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSTX = “H” ; Normal mode/PSTX = “L” ; Power saving mode 8 6 VpTX Power supply voltage input pin for the TX-PLL charge pump. 9 7 DOTX O Charge pump output pin for the TX-PLL section. 10 8 LD/fout O Lock detect signal output (LD) /phase comparator monitoring output (fout) .The output signal is selected by LDS bit in the serial data. LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal 11 9 DORX O Charge pump output pin for the RX-PLL section. 12 10 VpRX Power supply voltage input pin for the RX-PLL charge pump. 13 11 PSRX I Power saving mode control pin for the RX-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSRX = “H” ; Normal mode/PSRX = “L” ; Power saving mode 14 12 VCCRX Power supply voltage input pin for the RX-PLL section (except for the charge pump circuit) 15 13 GNDRX 16 14 XfinRX I Prescaler complimentary input pin for the RX-PLL section. This pin should be grounded via a capacitor. 17 15 finRX I Prescaler input pin for the RX-PLL. Connection to an external VCO should be via AC coupling. 18 16 LE I Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. I The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. Ground pin for OSC input buffer and the shift register circuit. Ground pin for the TX-PLL section. Ground pin for the RX-PLL section 19 17 Data I Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (TX-ref. counter, TX-prog. counter, RX-ref.counter, RX-prog.counter) according to the control bit in a serial data. 20 18 Clock I Clock input pin for the 23-bit shift register (with a schmitt trigger circuit) One bit of data is shifted into the shift register on a rising edge of the clock. 3 MB15F78UL ■ BLOCK DIAGRAM PSTX 7 (5) Intermittent mode control (TX-PLL) 3 bit latch 7 bit latch LDS SWTX FCTX (1) finTX 3 XfinTX 4 (2) Binary 7-bit swallow counter TX-PLL) 11 bit latch Phase comp. (TX-PLL) Binary 11-bit programmable counter (TX-PLL) Prescaler (TX-PLL) (16/17, 32/33) fpTX 2 bit latch T1 T2 14 bit latch 1 bit latch Binary 14-bit programmable ref. counter(TX-PLL) C/P setting counter Fast lock Tuning VCCTX GNDTX 6 (4) 5 (3) VpTX 8 (6) Charge Current pump Switch 9 DoTX (TX-PLL) (7) Lock Det. (TX-PLL) LDTX frTX Fast lock Tuning LD/fout AND OSCIN 1 (19) LD frTX frRX fpTX fpRX OR frRX (15) finRX 17 XfinRX 16 (14) Prescaler (RX-PLL) (32/33, 64/65) PSRX 13 (11) Intermittent mode control (RX-PLL) LE 18 (16) (17) Data 19 Clock 20 (18) T2 2 bit latch Schmitt circuit Schmitt circuit Schmitt circuit C/P setting counter 14 bit latch 1 bit latch LDRX fpRX LDS SWRX FCRX Binary 7-bit swallow counter (RX-PLL) 3 bit latch 7 bit latch 4 11 bit latch Phase comp. (RX-PLL) Charge pump Current (RX-PLL) Switch Latch selector C C N N 23-bit shift register 1 2 2 (20) GND O : TSSOP ( ) : BCC Binary 11-bit programmable counter (RX-PLL) Lock Det. (RX-PLL) Fast lock Tuning T1 Binary 14-bit programmable ref. counter (RF-PLL) 10 LD/ (8) fout 14 (12) 15 (13) VCCRX GNDRX 12 (10) VpRX 11 DoRX (9) MB15F78UL ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Min. Max. VCC −0.5 4.0 V Vp VCC 4.0 V VI −0.5 VCC + 0.5 V LD/fout VO GND VCC V DoTX, DoRX VDD GND Vp V Tstg −55 +125 °C Power supply voltage Input voltage Output voltage Rating Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Remarks 3.6 V VCCRX = VCCTX 2.7 3.6 V GND VCC V −40 +85 °C Min. Typ. Max. VCC 2.4 2.7 Vp VCC Input voltage VI Operating temperature Ta Power supply voltage Note : • VCCRX, VpRX, VCCTX and VpTX must supply equal voltage. Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. • Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. • When storing and transporting the device, put it in a conductive case. • Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench. • Before fitting the device into or removing it from the socket, turn the power supply off. • When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB15F78UL ■ ELECTRICAL CHARACTERISTICS (VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol “H” level input voltage “L” level input voltage “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current Min. Typ. Max. Unit finTX = 910 MHz VCCTX = VpTX = 2.7 V 1.1 1.7 2.4 mA ICCRX *1 finRX = 2500 MHz VCCRX = VpRX = 2.7 V 1.8 2.8 3.9 mA IPSTX PSTX = PSRX = “L” 0.1 *2 10 µA IPSRX PSTX = PSRX = “L” 0.1 *2 10 µA finTX *3 finTX TX PLL 100 1200 MHz RX 3 fin * finRX RX PLL 400 2600 MHz OSCIN fOSC 3 40 MHz Power saving current Input sensitivity Value ICCTX *1 Power supply current Operating frequency Condition finTX PfinTX TX PLL, 50 Ω system −15 +2 dBm finRX PfinRX RX PLL, 50 Ω system −15 +2 dBm OSCIN VOSC 0.5 VCC VP − P Data, LE, Clock VIH Schmitt trigger input 0.7 VCC + 0.4 V VIL Schmitt trigger input 0.3 VCC − 0.4 V PSTX PSRX VIH 0.7 VCC V VIL 0.3 VCC V IIH *4 −1.0 +1.0 µA IIL *4 −1.0 +1.0 µA IIH 0 +100 µA IIL *4 −100 0 µA VCC − 0.4 V 0.4 V Data LE Clock PSTX PSRX OSCIN VOH VCC = Vp = 2.7 V, IOH = −1 mA “L” level output voltage VOL VCC = Vp = 2.7 V, IOL = 1 mA “H” level output voltage VDOH VCC = Vp = 2.7 V, IDOH = −0.5 mA Vp − 0.4 V VDOL VCC = Vp = 2.7 V, IDOL = 0.5 mA 0.4 V IOFF VCC = Vp = 2.7 V VOFF = 0.5 V to Vp − 0.5 V 2.5 nA IOH *4 VCC = Vp = 2.7 V −1.0 mA IOL VCC = Vp = 2.7 V 1.0 mA “H” level output voltage “L” level output voltage High impedance cutoff current “H” level output current “L” level output current LD/fout DoTX DoRX DoTX DoRX LD/fout (Continued) 6 MB15F78UL (Continued) (VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter “H” level output current “L” level output current Charge pump current rate Symbol Condition DoTX *8 DoRX IDOH *4 DoTX *8 DoRX IDOL IDOL/IDOH IDOMT *5 DOVD 6 vs VDO I * vs Ta IDOTA *7 Value Unit Min. Typ. Max. VCC = Vp = 2.7 V, CS bit = “H” VDOH = Vp / 2, CS bit = “L” Ta = +25 °C −8.2 −6.0 −4.1 mA −2.2 −1.5 −0.8 mA VCC = Vp = 2.7 V, CS bit = “H” VDOL = Vp / 2, CS bit = “L” Ta = +25 °C 4.1 6.0 8.2 mA 0.8 1.5 2.2 mA VDO = Vp / 2 3 % 0.5 V ≤ VDO ≤ Vp − 0.5 V 10 % −40 °C ≤ Ta ≤ +85 °C, VDO = Vp / 2 5 % *1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state. *2 : VCCTX = VpTX = VCCRX = VpRX = 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode. PSTX = PSRX = GND VIH = VCC, VIL = GND (at CLK, Data, LE) *3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency. *4 : The symbol “–” (minus) means the direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%) *6 : VCC = Vp = 2.7 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH) *7 : VCC = Vp = 2.7 V, [||IDO (+85 °C) | − |IDO (–40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (–40 °C) | / 2] × 100 (%) (Applied to both IDOL and IDOH) *8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”. I1 I3 I2 IDOL IDOH I4 I2 I1 0.5 Vp/2 Vp − 0.5 Vp Charge pump output voltage (V) 7 MB15F78UL ■ FUNCTIONAL DESCRIPTION 1. Pulse swallow function fVCO = [ (P × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (16 or 32 for TX-PLL, 32 or 64 for RX-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. Serial Data Input The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RXPLL sections, programmable reference dividers of TX/RX-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. The programmable reference counter for the TX-PLL The programmable reference counter for the RX-PL The programmable counter and the swallow counter for the TX-PLL The programmable counter and the swallow counter for the RX-PLL CN1 0 1 0 1 CN2 0 0 1 1 (1) Shift Register Configuration • Programmable Reference Counter (LSB) 1 2 3 Data Flow 4 5 6 7 8 9 10 11 12 13 (MSB) 14 15 16 17 18 19 20 21 22 23 CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X CS : Charge pump current select bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) T1, 2 : LD/fout output setting bit CN1, 2 : Control bit X : Dummy bits (Set “0” or “1”) Note : Data input with MSB first. 8 X X MB15F78UL • Programmable Counter (LSB) 1 2 Data Flow 3 4 CN1 CN2 LDS 5 SW FC TX/RX TX/RX A1 to A7 6 7 8 9 (MSB) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 : Divide ratio setting bits for the swallow counter (0 to 127) N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047) LDS : LD/fout signal select bit SWTX/RX : Divide ratio setting bit for the prescaler (TX : SWTX, RX : SWRX) FCTX/RX : Phase control bit for the phase detector (TX : FCTX, RX : FCRX) CN1, 2 : Control bit Note : Data input with MSB first. (2) Data setting • Binary 14-bit Programmable Reference Counter Data Setting Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 • • • 16383 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 0 • • • 1 0 • • • 1 Note : Divide ratio less than 3 is prohibited. • Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 • • • 2047 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 0 • • • 1 0 • • • 1 Note : Divide ratio less than 3 is prohibited. • Binary 7-bit Swallow Counter Data Setting Divide ratio A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 • • • 127 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 9 MB15F78UL • Prescaler Data Setting Divide ratio SW = “H” SW = “L” Prescaler divide ratio TX-PLL 16/17 32/33 Prescaler divide ratio RX-PLL 32/33 64/65 • Charge Pump Current Setting Current value CS ±6.0 mA 1 ±1.5 mA 0 • LD/fout output Selectable Bit Setting LD/fout pin state LDS T1 T2 0 0 0 0 1 0 0 1 1 frTX 1 0 0 frRX 1 1 0 fpTX 1 0 1 fpRX 1 1 1 LD output fout output • Phase Comparator Phase Switching Data Setting FC = “H” FC = “L” DoTX/DoRX DoTX/DoRX fr > fp H L fr < fp L H Z Z Phase comparator input fr = fp Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High (1) VCO polarity FC = “H” (2) VCO polarity FC = “L” (1) VCO Output Frequency (2) LPF Output voltage Note : Give attention to the polarity for using active type LPF. 10 Max. MB15F78UL 3. Power Saving Mode (Intermittent Mode Control Circut) PSTX/PSRX pins Status Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pins high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : • When power (VCC) is first applied, the device must be in standby mode, PSTX = PSRX = Low, for at least 1 µs. • PS pins must be set at “L” at Power-ON OFF VCC ON tV ≥ 1 µs Clock Data LE tPS ≥ 100 ns PSTX PSRX (1) (2) (3) (1) PSTX = PSRX = “L” (power saving mode) at Power-ON (2) Set serial data at least 1 µs after the power supply becomes stable (VCC ≥ 2.2 V) . (3) Release power saving mode (PSTX, PSRX : “L” → “H”) at least 100 ns after setting serial data. 11 MB15F78UL 4. Serial data input timing Divide ratio setting is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 2nd data 1st data Control bit Data MSB Invalid data LSB Clock t1 t2 t3 t6 t7 LE t4 Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 20 ns t5 100 ns t2 20 ns t6 20 ns t3 30 ns t7 100 ns t4 30 ns Note : LE should be “L” when the data is transferred into the shift register. 12 t5 MB15F78UL ■ PHASE COMPARATOR OUTPUT WAVEFORM frTX/ frRX fpTX/ fpRX tWU tWL LD (FC bit = High) DoTX/ DoRX H Z L (FC bit = Low) DoTX/ DoRX H Z L LD Output Logic Table TX-PLL section RX-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes : • Phase error detection range = −2 π to +2 π • Pulses on DoTX/DoRX signals are output to prevent dead zone. • LD output becomes low when phase error is tWU or more. • LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency as follows. tWU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz tWU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz 13 MB15F78UL ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) fout Oscilloscope 1000 pF VCCTX VpTX 0.1 µF 1000 pF S.G. 50 Ω 0.1 µF 1000 pF LD/ fout DoTX VpTX PSTX VCCTX GNDTX XfinTX finTX GND OSCIN 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 DoRX VpRX PSRX VCCRX GNDRX XfinRX finRX LE Data Clock 50 Ω 1000 pF Controller (devide ratio setting) 1000 pF VpRX 0.1 µF VCCRX 0.1 µF Note : The terminal number shows that of TSSOP-20 14 50 Ω S.G. S.G. MB15F78UL ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity RX-PLL input sensitivity vs. Input frequency 10 PfinRX (dBm) 0 SPEC −10 −20 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC −30 −40 −50 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 finRX (MHz) TX-PLL input sensitivity vs. Input frequency 10 PfinTX (dBm) 0 SPEC −10 −20 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC −30 −40 −50 0 200 400 600 800 1000 1200 1400 finTX (MHz) 15 MB15F78UL 2. OSCIN input sensitivity Input sensitivity vs. Input frequency 10 Input sensitivity VOSC (dBm) SPEC 0 −10 −20 −30 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC −40 −50 −60 0 50 100 150 200 Input frequency fOSC (MHz) 16 250 300 MB15F78UL 3. Do output current (RX PLL) IDO − VDO • 1.5 mA mode Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) 17 MB15F78UL 4. Do output current (TX PLL) • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) 18 MB15F78UL 5. fin input impedance finTX input impedance 4 : 9.6016 Ω −68.832 Ω 1.9269 pF 1 200.000 000 MHz 1 : 317.09 Ω −831.5 Ω 100 MHz 2 : 30.898 Ω −233.42 Ω 400 MHz 3 : 13.227 Ω −112.79 Ω 800 MHz 1 2 4 START 100.000 000 MHz 3 STOP 1 200.000 000 MHz finRX input impedance 4 : 12.588 Ω −3.4751 Ω 17.615 pF 2 600.000 000 MHz 1 : 43.75 Ω −235.95 Ω 400 MHz 2 : 12.82 Ω −88.188 Ω 1 GHz 3 : 9.7227 Ω −25.9 Ω 2 GHz 4 1 3 2 START 400.000 000 MHz STOP 2 600.000 000 MHz 19 MB15F78UL 6. OSCIN input impedance OSCIN input impedance 4 : 28.844 Ω −691.13 Ω 2.3028 pF 100.000 000 MHz 1 : 12.953 kΩ −13.003 kΩ 3 MHz 2 : 478.13 Ω −3.4268 kΩ 20 MHz 4 3 : 118.19 Ω −1.7321 kΩ 40 MHz 1 32 START 3.000 000 MHz 20 STOP 100.000 000 MHz MB15F78UL ■ REFERENCE INFORMATION (for Look-up time, Phase noise and Reference leakage) Test Circuit S.G. OSCIN LPF DO fVCO = 2490 MHz KV = 52 MHz/V fr = 200 kHz fOSC = 19.8 MHz LPF fin Spectrum Analyzer VCC = 3.0 V VVCO = 2.5 V Ta = +25 °C CP : 1.5 mA mode 24 kΩ 82 pF VCO 15 kΩ 22 pF 820 pF • PLL Reference Leakage ATTEN 10 dB RL 0 dBm VAVG 39 10 dB/ ∆MKR −67.50 dB 200 kHz ∗ ∆MKR D 200 kHz S −67.50 dB CENTER 2.490008 GHz ∗ RBW 3.0 kHz VBW 3.0 kHz SPAN 1.000 MHz SWP 280 ms • PLL Phase Noise ATTEN 10 dB RL 0 dBm VAVG 48 10 dB/ ∆MKR −59.33 dB 1.00 kHz ∆MKR D 1.00 kHz S −59.33 dB CENTER 2.49000640 GHz ∗ RBW 100 Hz VBW 100 Hz SPAN 10.00 kHz SWP 802 ms (Continued) 21 MB15F78UL (Continued) • PLL Lock-up time • PLL Lock-up time 2.49 GHz→2.55 GHz within ± 1 kHz Lch→Hch 222 µs 2.550011500 GHz 2.490011500 GHz 2.550007500 GHz 2.490007500 GHz 2.550003500 GHz 2.490003500 GHz −1.911 ms T1 400 µs 22 2.55 GHz→2.49 GHz within ± 1 kHz Hch→Lch 267 µs 3.089 ms 1.000 ms/div T2 622 µs 8.089 ms −1.911 ms ∆222 µs T1 422 µs 3.089 ms 1.000 ms/div T2 689 µs 8.089 ms ∆267 µs MB15F78UL ■ APPLICATION EXAMPLE VCO OUTPUT from controller LPF 2.7 V 1000 pF 2.7 V 1000 pF 0.1 µF 0.1µ F Clock Data LE finRX XfinRX GNDRX VCCRX PSRX VpRX DoRX 20 19 18 17 16 15 14 13 12 11 MB15F78UL 1 2 3 4 5 6 7 8 9 10 OSCIN GND finTX XfinTX GNDTX VCCTX PSTX VpTX DoTX LD/fout Lock Det. 1000 pF 1000 pF 2.7 V 2.7 V 1000 pF 0.1 µF 0.1 µF TCXO OUTPUT VCO LPF Notes : •Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . •The terminal number shows that of TSSOP-20. 23 MB15F78UL ■ USAGE PRECAUTIONS (1) VCCRX, VpRX, VCCTX and VpTX must be equal voltage. Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device. ■ ORDERING INFORMATION Part number 24 Package MB15F78ULPFT 20-pin, plastic TSSOP (FPT-20P-M06) MB15F78ULPVA 20-pad, plastic BCC (LCC-20P-M05) Remarks MB15F78UL ■ PACKAGE DIMENSIONS 20-pin plastic TSSOP (FPT-20P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. * 6.50±0.10(.256±.004) 0.17±0.05 (.007±.002) 11 20 * 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8° +0.03 (0.50(.020)) 0.10(.004) C 0.45/0.75 (.018/.030) +.001 0.07 –0.07 .003 –.003 (Stand off) 0.25(.010) 1999 FUJITSU LIMITED F20026S-2C-2 Dimensions in mm (inches) (Continued) 25 MB15F78UL (Continued) 20-pad plastic BCC (LCC-20P-M05) 3.00(.118)TYP 3.60±0.10(.142±.004) 16 0.55±0.05 (.022±.002) (Mounting height) 11 11 0.25±0.10 (.010±.004) 16 0.50(.020) TYP 0.25±0.10 (.010±.004) INDEX AREA 3.40±0.10 (.134±.004) 2.70(.106) TYP "D" "A" 1 6 "C" 6 Details of "A" part 0.50±0.10 (.020±.004) 1 0.50(.020) TYP 2.80(.110)REF 0.075±0.025 (.003±.001) (Stand off) 0.05(.002) "B" Details of "B" part 0.50±0.10 (.020±.004) Details of "C" part Details of "D" part 0.30±0.10 (.012±.004) 0.50±0.10 (.020±.004) C0.20(.008) 0.60±0.10 (.024±.004) C 0.30±0.10 (.012±.004) 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) 2001 FUJITSU LIMITED C20056S-c-2-1 Dimensions in mm (inches) 26 MB15F78UL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0106 FUJITSU LIMITED Printed in Japan