FUJITSU SEMICONDUCTOR DATA SHEET DS04-27203-8E ASSP BIPOLAR Switching Regulator Controller MB3778 ■ DESCRIPTION The MB3778 is a dual switching regulator control IC. It has a two-channel basic circuit that controls PWM system switching regulator power. Complete synchronization is achieved by using the same oscillator output wave. This IC can accept any two of the following types of output voltage: step-down, step-up, or voltage inversion (inverting voltage can be output to only one circuit). The MB3778’s low power consumption makes it ideal for use in portable equipment. ■ FEATURES • • • • • • • • • Wide input voltage range : 3.6 V to 18 V Low current consumption : 1.7 mA Typ operation, 10 µA Max stand-by Wide oscillation frequency range:1 kHz to 500 kHz Built-in timer latch short-circuit protection circuit Built-in under-voltage lockout circuit Built-in 2.46 V reference voltage circuit : 1.23 V output can be obtained from RT terminal Variable dead-time provides control over total range Built-in stand-by function: power on/off function Two types of packages (SOP-16pin :1 type, SSOP-16pin :1 type) ■ APPLICATIONS • LCD monitor/panel • Surveillance camera etc. Copyright©1994-2006 FUJITSU LIMITED All rights reserved MB3778 ■ PIN ASSIGNMENT (TOP VIEW) CT 1 16 VREF RT 2 15 SCP +IN1 3 14 CTL −IN1 4 13 −IN2 FB1 5 12 FB2 DTC1 6 11 DTC2 OUT1 7 10 OUT2 E/GND 8 9 (FPT-16P-M05) (FPT-16P-M06) 2 VCC MB3778 ■ PIN DESCRIPTION No. Pin Function 1 CT Oscillator timing capacitor terminal (150 pF to 15,000 pF) . 2 RT Oscillator timing resistor terminal (5.1 kΩ to 100 kΩ) . VREF × 1/2 voltage is also available at this pin for error amplifier reference input. 3 +IN1 Error amplifier 1 non-inverted input terminal. 4 −IN1 Error amplifier 1 inverted input terminal. 5 FB1 Error amplifier 1 output terminal. A resistor and a capacitor are connected between this terminal and the −IN1 terminal to adjust gain and frequency. 6 DTC1 OUT1 dead-time control terminal. Dead-time control is adjusted by an external resistive divider connected to the VREF pin. A capacitor connected between this terminal and GND enables soft-start operation. 7 OUT1 Open collector output terminal. Output transistor has common ground independent of signal ground. This output can source or sink up to 50 mA. 8 E/GND Ground terminal. 9 VCC 10 OUT2 Open collector output terminal. Output transistor has common ground independent of signal ground. This output can source or sink up to 50 mA. 11 DTC2 Sets the dead-time of OUT2. The use of this terminal is the same as that of DTC1. Power supply terminal (3.6 V to 18 V) 12 FB2 Error amplifier 2 output terminal. Sets the gain and adjusts the frequency when a resistor and a capacitor are connected between this terminal and the −IN2 terminal. Voltage of VREF × 1/2 voltage is internally connected to the non-inverted input of error amplifier 2. Uses error amplifier 2 for positive voltage output. 13 −IN2 Error amplifier 2 inverted input terminal. CTL Power control terminal. The IC is set in the stand-by state when this terminal is set “Low.” Current consumption is 10 µA or lower in the stand-by state. The input can be driven by TTL or CMOS. 15 SCP The time constant setting capacitor connection terminal of the timer latch short-circuit protection circuit. Connects a capacitor between this pin and GND. For details, see “■ HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”. 16 VREF 2.46 V reference voltage output terminal which can be obtained up to 1 mA. This pin is used to set the reference input and idle period of the error amplifiers. 14 3 MB3778 ■ BLOCK DIAGRAM 9 14 2 1 1.23 V 2.46 V 16 Reference Voltage 1.9 V Power Supply Control Triangular Oscillator 1.3 V 13 Error Amp 1 + − 7 − + + 2.46 V 3 4 5 12 OUT1 PWM Comp.1 − − + S.C.P. Comp. − + + OUT2 10 PWM Comp.2 2.1 V Error Amp 2 − + 1.23 V 2.46 V 1 µA 15 R S Latch R U. V. L. O. D.T.C. Comp. − − + 8 1.1 V 6 4 11 MB3778 ■ OPERATION DESCRIPTION 1. Reference voltage circuit The reference voltage circuit generates a temperature-compensated reference voltage ( =: 2.46 V) from VCC terminal (pin 9) . The reference voltage is used as an operation power supply for internal circuit. The reference is obtained from the VREF terminal (pin 16). 2. Triangular wave oscillator Triangular waveforms can be generated at any frequency by connecting a timing capacitor and resistor to the CT terminal (pin 1) and to the RT terminal (pin 2) . The amplitude of this waveform is from 1.3 V to 1.9 V. These waveforms are connected to the non-inverting inputs of the PWM comparator and can be output through the CT terminal (pin 1) . 3. Error amplifiers (Error Amp) The error amplifier detects the output voltage of the switching regulator and outputs PWM control signals.The in-phase input voltage range is from 1.05 V to 1.45 V.The reference voltage obtained by dividing the reference voltage output (recommended value : VREF/2) or the RT terminal (pin 2) voltage (1.23 V) is supplied to the noninverting input. The VREF/2 voltage is internally connected to non-inverting input of the other error amplifier. Any loop gain can be chosen by connecting the feedback resistor and capacitor to the inverting input terminal from the output terminal of the error amplifier.Stable phase compensation is possible. 4. Timer latch short circuit protection circuit This circuit detects the output levels of each error amplifier. If the output level of one or both of the error amplifiers is 2.1 V or higher, the timer circuit begins charging the externally connected protection enable-capacitor. If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage reaches the transistor base-emitter voltage, VBE( =: 0.65 V), the latch circuit turns the output drive transistor off and sets the idle period to 100%. 5. Under voltage lock-out circuit The transition state at power-on or a momentary drops in supply voltage may cause the control IC to malfunction, which may adversely affect or even destroy the system. The under voltage lockout circuit monitors VCC with reference to the internal reference voltage and resets the latch circuit to turn the output drive transistor off. The idle period is set to 100%. It also pulls the SCP terminal (pin 15) “Low”. 6. PWM comparator unit Each PWM comparator has one inverting input and two non-inverting inputs. This voltage-to-pulse-width converter controls the turning on time of the output pulse according to the input voltage. The PWM comparator turns the output drive transistor on while triangular waveforms from the oscillator are lower than the error amplifier output and the DTC terminal voltage. 7. Output drive transistor The output drive transistors have open collector outputs with common source supply and common grounds independent of VCC and signal ground. The output drive transistors for switching can sink or source up to 50 mA. 8. Power control unit The CTL terminal (pin 14) controls power on/off modes(the power supply current in stand-by mode is 10 µA or lower). 5 MB3778 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Power Supply Voltage VCC Error Amp Input Voltage Rating Unit Min Max ⎯ ⎯ 20 V VIN ⎯ −0.3 +10 V Control Input Voltage VCTL ⎯ −0.3 +20 V Collector Output Voltage VOUT ⎯ ⎯ 20 V Collector Output Current IOUT ⎯ ⎯ 75 Ta ≤ +25 °C (SOP) ⎯ Ta ≤ +25 °C (SSOP) mA 620* 1 mW ⎯ 444* 2 mW Power Dissipation PD Operating Ambient Temperature Ta ⎯ −30 +85 °C Tstg ⎯ −55 +125 °C Storage Temperature *1: The packages are mounted on the epoxy board (4 cm × 4 cm) *2: The packages are mounted on the epoxy board (10 cm × 10 cm) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Typ Max Unit Power Supply Voltage VCC 3.6 6.0 18 V Error Amp Input Voltage VIN 1.05 ⎯ 1.45 V Control Input Voltage VCTL 0 ⎯ 18 V Collector Output Voltage VOUT ⎯ ⎯ 18 V Collector Output Current IOUT 0.3 ⎯ 50 mA Timing Capacitor CT 150 ⎯ 15000 pF Timing Resistor RT 5.1 ⎯ 100 kΩ Oscillator Frequency fOSC 1 ⎯ 500 kHz Operating Ambient Temperature Ta −30 +25 +85 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB3778 ■ ELECTRICAL CHARACTERISTICS (Ta = +25 °C, VCC = 6 V) Parameter Symbol Condition Value Unit Min Typ Max 2.41 2.46 2.51 V Reference Block Output Voltage VREF IOR = −1 mA Output Temp. Stability VRTC Ta = −30 °C to +85 °C −2 ±0.2 +2 % Input Stability Line VCC = 3.6 V to 18 V ⎯ 2 10 mV Load Stability Load IOR = −0.1 mA to −1 mA ⎯ 1 7.5 mV −30 −10 −3 mA Short Circuit Output Current IOS VREF = 2 V Under Voltage Lockout Protection Block VtH IOR = −0.1 mA ⎯ 2.72 ⎯ V VtL IOR = −0.1 mA ⎯ 2.60 ⎯ V VHYS IOR = −0.1 mA 80 120 ⎯ mV VR ⎯ 1.5 1.9 ⎯ V Input Threshold Voltage VtPC ⎯ 0.60 0.65 0.70 V Input Stand by Voltage VSTB No pull up ⎯ 50 100 mV Input Latch Voltage VIN No pull up ⎯ 50 100 mV Input Source Current Ibpc ⎯ −1.4 −1.0 −0.6 µA Comparator Threshold Voltage VtC Pin 5, Pin 12 ⎯ 2.1 ⎯ V Oscillator Frequency fOSC CT = 330 pF, RT = 15 kΩ 160 200 240 kHz Frequency Deviation fdev CT = 330 pF, RT = 15 kΩ ⎯ ±5 ⎯ % Frequency Stability (VCC) fdV VCC = 3.6 V to 18 V ⎯ ±1 ⎯ % Frequency Stability (Ta) fdT Ta = −30 °C to +85 °C −4 ⎯ +4 % ⎯ 0.2 1 µA Threshold Voltage Hysteresis Width Reset Voltage (VCC) Protection Circuit Block (S.C.P.) Triangular Waveform Oscillator Block Dead-Time Control Block (D.T.C.) ⎯ Input Bias Current Ibdt Latch Mode Sink Current Idt Vdt = 2.5 V 150 500 ⎯ µA Latch Input Voltage Vdt Idt = 100 µA ⎯ ⎯ 0.3 V (Continued) 7 MB3778 (Continued) (Ta = +25 °C, VCC = 6 V) Parameter Symbol Condition Value Min Typ Max Unit Error Amp Block Input Offset Voltage VIO VO = 1.6 V −6 ⎯ +6 mV Input Offset Current IIO VO = 1.6 V −100 ⎯ +100 nA Input Bias Current IB VO = 1.6 V −500 −100 ⎯ nA VCC = 3.6 V to 18 V 1.05 ⎯ 1.45 V Common Mode Input Voltage Range VICR Voltage Gain AV RNF = 200 kΩ 70 80 ⎯ dB Frequency Band Width BW AV = 0 dB ⎯ 1.0 ⎯ MHz Common Mode Rejection Ratio Max Output Voltage Width CMRR ⎯ 60 80 ⎯ dB VOM+ ⎯ VREF − 0.3 ⎯ ⎯ V VOM− ⎯ ⎯ 0.7 0.9 V Output Sink Current IOM+ VO = 1.6 ⎯ 1.0 ⎯ mA Output Source Current IOM− VO = 1.6 ⎯ −60 ⎯ µA Vt100 Duty Cycle = 100% ⎯ 1.9 2.25 V 1.05 1.3 ⎯ V PWM Comparator Block Input Threshold Voltage (fOSC = 10 kHz) Vt0 Duty Cycle = 0% On duty Cycle Dtr Vdt = VREF/1.45 55 65 75 % Input Sink Current IIN+ Pin 5, Pin 12 = 1.6 V ⎯ 1.0 ⎯ mA Input Source Current IIN− Pin 5, Pin 12 = 1.6 V ⎯ −60 ⎯ µA Control Block Input Off Condition VOFF ⎯ ⎯ ⎯ 0.7 V Input On Condition VON ⎯ 2.1 ⎯ ⎯ V Control Terminal Current ICTL VCTL = 10 V ⎯ 200 400 µA Output Block Output Leak Current Leak VO = 18 V ⎯ ⎯ 10 µA Output Saturation Voltage VSAT IO = 50 mA ⎯ 1.1 1.4 V Stand-by Current ICCS VCTL = 0 V ⎯ ⎯ 10 µA Average Supply Current ICCa VCTL = VCC, No Output Load ⎯ 1.7 2.4 mA All Device Block 8 MB3778 ■ TEST CIRCUIT CTL VCC = 6 V INPUT TEST SW 4.7 kΩ CPE OUTPUT 1 4.7 kΩ OUTPUT 2 16 15 14 13 12 11 10 9 6 7 8 MB3778 1 330 pF 2 3 4 5 15 kΩ TEST INPUT ■ TIMING CHART (Internal Waveform) Triangular waveform oscillator output Short circuit protection comparator Reference 2.1 V 1.9 V input 1.6 V Dead Time, PWM input voltage 1.3 V Error Amp output PWM comparator output "High" Output Transistor collector waveform "High" S.C.P. Terminal waveform 0.65 V Short circuit protection comparator output "High" "Low" DEAD TIME 100% "Low" 0.05 V tPE "Low" Power “ON” Control Input voltage Power “OFF” 2.1 V (VCTL : Min Value) 0V Power supply voltage 3.6 V (VCC : Min Value) 0V Protection Enable Time tPE 0.6 × 106 × CPE (µs) 9 MB3778 ■ APPLICATION CIRCUIT • Chopper Type Step Down/inverting VIN (10 V) CTL 820 pF 1 16 2 15 3 14 0.1 µF 8.2 kΩ 56 µH 1.8 kΩ 4.7 kΩ 4.7 kΩ 0.033 µF 4.7 kΩ 150 kΩ 1.8 kΩ 4 13 MB3778 5 12 0.033 µF 220 µF − + 10 kΩ 10 kΩ 6 11 − + 1 µF 150 kΩ + − 7 10 8 9 1 µF 5.6 kΩ 2.4 kΩ 330 Ω 330 Ω 330 Ω 330 Ω 120 µH 120 µH − + − + 220 µF 9.1 kΩ VO− ( −5 V) 10 220 µF GND V O+ ( 5 V) MB3778 • Chopper Type Step Up/Inverting VIN (5 V) CTL 820 pF 1 16 2 15 3 14 0.1 µF 8.2 kΩ 56 µH 1.8 kΩ 4.7 kΩ 4.7 kΩ 0.033 µF 4.7 kΩ 150 kΩ 1.8 kΩ 4 13 MB3778 5 12 0.033 µF 220 µF − + 10 kΩ 10 kΩ 6 11 − + 1 µF 150 kΩ + − 7 10 8 9 1 µF 16 kΩ 4.7 kΩ 330 Ω 3.9 kΩ 330 Ω 120 µH 100 Ω 120 µH 220 µF − + 220 µF + − 9.1 kΩ VO− ( −5 V) GND V O+ ( 5 V) 11 MB3778 • Multi Output Type (Apply Transformer) VIN (10 V) CTL 820 pF 1 16 2 15 3 14 0.1 µF 8.2 kΩ 56 µH 1.8 kΩ 4 13 MB3778 5 12 6 11 7 10 8 9 150 kΩ 220 µF − + 0.033 µF 10 kΩ 1.8 kΩ 220 Ω 4.7 kΩ 1000 pF 5.6 kΩ VO2− ( −12 V) 12 − + − + − + − + 220 µF 220 µF 220 µF 220 µF VO1− ( −5 V) GND VO2+ ( 5 V) VO1+ ( 12 V) MB3778 ■ HOW TO SET THE OUTPUT VOLTAGE The output voltage is set using the connections shown in “Connection of error Amp Output Voltage V0 ≥ 0” and “Connection of Error Amp Output Voltage V0 < 0”. The error amplifier power is supplied by the reference voltage circuit as is that of the other internal circuits. The common mode input voltage range is from 1.05 V to 1.45 V. Set 1.23 V (VREF/2) as the reference input voltage that is connected to either inverting or non-inverting input terminals. • Connection of Error Amp Output Voltage V0 ≥ 0 VREF R VO+ VO + = R1 VREF 2 × R2 (R1 + R2) + PIN 5 or PIN 12 − R R2 RNF • Connection of Error Amp Output Voltage V0 < 0 VREF R VO− = − VREF 2 × R1 (R1 + R2) + VREF R1 + PIN 5 − R R2 RNF VO− 13 MB3778 ■ HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT PROTECTION CIRCUIT Below Figure shows the configuration of the protection latch circuit. Each error amplifier output is connected to the inverting inputs of the short-circuit protection comparator and is always compared with the reference voltage (2.1 V) connected to the non-inverting input. When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus, short-circuit protection control is also kept in balance, and the SCP terminal (pin 15) voltage is held at about 50 mV. If the load changes drastically due to a load short-circuit and if the inverting inputs of the short-circuit protection comparator go above 2.1 V, the short-circuit protection comparator output goes “Low” to turn off transistor Q1. The SCP terminal voltage is discharged, and then the short-circuit protection comparator charges the protection enable capacitor CPE according to the following formula : VPE = 50 mV + tPE × 10 − 6 / CPE 0.65 = 50 mV + tPE × 10 − 6 / CPE CPE = tPE / 0.6 (µF) When the protection enable capacitor is charged to about 0.65 V, the protection latch is set to enable the under voltage lockout circuit and the output drive transistor is turned off. The idle period is also set to 100% at the same time. Once the under voltage lockout circuit is enabled, the protection enable is released; however, the protection latch is not reset if the power is not turned off. The inverting inputs (pin 6 or 11) of the D.T.C. comparator are compared to the reference voltage (about 1.1 V) connected to the non-inverting input. To prevent malfunction of the short-circuit protection-circuit when the soft-start operation is done by using the DTC terminal (pin 6 or 11) , the D.T.C. comparator outputs a “High” level while the DTC terminal (pin 6 or 11) goes up to about 1.1 V, and then closes the SCP terminal (pin 15) by turning transistor Q2 on. • Protection Latch Circuit 2.46 V 1 µA S.C.P. Comp. SCP 15 R1 Error Amp1 Error Amp2 2.1 V − − + CPE Q1 Q2 Q3 S R Latch − − + D.T.C. Comp. 14 1.1 V U.V.L.O. 6 DTC1 11 DTC2 MB3778 ■ SETTING THE IDLE PERIOD When voltage step-up, fly-back step-up or inverted output are set, the voltage at the FB terminal may go higher than the triangular wave voltage due to load fluctuation, etc. In this case the output transistor will be in full-on state(ON duty 100%). This can be prevented by setting the maximum duty for the output transistor. This is done by setting the DTC1 terminal (pin 6) voltage using resistance division of the VREF voltage as illustrated below. When the DTC1 terminal voltage is higher than the triangular waveform voltage, the output transistor is turned on. If the triangular waveform amplitude specified by the maximum duty calculation formula is 0.6 V, and the lower voltage limit of the triangular waveform is 1.3 V, the formula would be as follows (other channels are similar) : Duty (ON) max (%) =: (Vdt − 1.3 V) / 0.6 V × 100, Vdt (V) = Rb / (Ra + Rb) × VREF Also, if no output duty setting is required, the voltage should be set greater than the upper limit voltage of the triangular waveform, which is 1.9 V. • Setting the idle time at DTC1 (DTC2 is similar) VREF 16 Ra DTC1 6 Rb Vdt 15 MB3778 ■ SETTING THE SOFT START TIME When power is switched on, the current begins charging the capacitor (CDTC1) connected the DTC1 terminal (pin 6). The soft start process operates by comparing the soft start setting voltage, which is proportional to the DTC1 terminal voltage, with the triangular waveform, and varying the ON-duty of the OUT terminal (pin 7). The soft start time until the ON duty reaches 50% is determined by the following equation: Soft start time (time until output ON duty = 50%) . ts (s) =: − CDTC1 × Ra × Rb / (Ra + Rb) × ln (1 − 1.6 (Ra + Rb) / (2.46 Rb) ) For example, if Ra = 4.7 kΩ and Rb = 10 kΩ, the result is: ts (s) =: 0.01 × CDTC1 (µF) • Soft Start on DCT1 terminal (DTC2 is similar) VREF 16 Ra DTC1 6 Rb 16 CDTC1 MB3778 ■ USING THE RT TERMINAL The triangular waves, as shown in Figure “No VREF/2 connection to external circuits from RT terminal”, act to set the oscillator frequency by charging and discharging the capacitor connected to the CT terminal using the current value of the resistor connected to the RT terminal. In addition, when voltage level VREF/2 is output to external circuits from the RT terminal (pin 2) , care must be taken in making the external circuit connections to adjust for the fact that I1 is increased by the value of the current I2 to the external circuits in determining the oscillator frequency (see Figure “VREF/2 connection to external circuits from RT terminal”). • No VREF/2 connection to external circuits from RT terminal Triangular wave oscillator ICT = IRT = VREF 2RT ( V2 ) REF 2 1 IRT ICT RT CT • VREF/2 connection to external circuits from RT terminal Triangular wave oscillator ICT = IRT = I1 + I2 VREF = + I2 2RT ( V2 ) REF 2 1 IRT ICT To external circuits I2 I1 RT CT 17 MB3778 ■ SYNCHRONIZATION OF ICs A fixed condenser and resistor are inserted in the CT and RT terminals of IC which becomes a master when synchronizing by using plurality of MB3778. As a result, the slave ICs oscillate automatically. The RT terminals (pin 2) of the slave ICs are connected to the VREF terminal (pin 16) to disable the charge/discharge circuit for triangular wave oscillation. The CT terminals of the master and slave ICs are connected together. • Connection of Master, Slave MB3778 (MASTER) CT RT MB3778 (SLAVE) MB3778 (SLAVE) 18 VCC MB3778 ■ TYPICAL CHARACTERISTICS Reference voltage vs. Power supply voltage Average supply current ICCa (mA) Ta = +25 °C 5.0 Reference voltage VREF (V) Average supply current vs. Power supply voltage 2.5 0 0 4 8 12 16 1.0 0 0 20 Power supply voltage VCC (V) VCC = VCTL = 6 V IOR = −1 mA Reference voltage VREF (V) 2.45 2.44 2.43 2.42 2.41 −20 0 +20 +40 +60 +80 +100 Triangular waveform Upper / Lower Limit voltage (V) 2.47 2.40 −40 4 8 12 16 20 Power supply voltage VCC (V) Reference voltage vs. Operating ambient temperature 2.46 Ta = +25 °C 2.0 Triangular waveform Upper/Lower Limit voltage vs. Timing capacitor 2.2 2.0 Upper limit 1.8 1.6 1.4 1.2 VCC = 6 V RT = 15 kΩ Ta = +25 °C Lower limit 1.0 0.8 102 103 Timing capacitor CT (pF) 104 Operating ambient temperature Ta (°C) Collector saturation voltage vs. Sink Current Error Amp Max output voltage vs. Frequency VCC = 6 V Ta = +25 °C 4.0 3.0 2.0 1.0 Error Amp Max output voltage (V) Collector saturation voltage (V) 5.0 3.0 VCC = 6 V Ta = +25 °C 2.0 1.0 0 100 500 1 k 5 k 10 k 50 k 100 k 500 k Frequency (Hz) 0 0 100 200 300 400 Sink current (mA) 500 (Continued) 19 MB3778 Oscillation frequency vs.Timing resistor Triangular waveform cycle vs. Timing capacitor VCC = 6 V Ta = +25 °C 1M 100 k CT = 150 pF Triangular waveform cycle (µs) Oscillation frequency fOSC (Hz) 100 VCC = 6 V RT = 15 kΩ Ta = +25 °C 10 CT = 1500 pF 10 k 1 102 103 104 Timing capacitor CT (pF) CT = 15000 pF 1k 1k 5 k 10 k 50 k100 k Timing resistor RT (Ω) 500 k Frequency stability vs. Operating ambient temperature ON duty cycle vs. Oscillation frequency VCC = 6 V CT = 330 pF RT = 15 kΩ 0 −40 −20 0 +20 +40 +60 100 ON duty cycle Dtr (%) Frequency stability fdT (%) 10 −10 VCC = 6 V CT = 330 pF RT = 15 kΩ Ta = +25 °C 80 60 40 20 0 +80 +100 +120 5k Operating ambient temperature Ta (°C) 1 2 3 Control voltage VCTL (V) 4 5 Control terminal current ICTL (µA) Reference voltage VREF (V) VCC = 6 V Ta = +25 °C 0 50 k 100 k 500 k 1 M Control terminal current vs. Control input voltage 2.5 0 10 k Oscillation frequency fOSC (Hz) Reference voltage vs. Control voltage 5.0 105 VCC = 6 V Ta = +25 °C 500 250 0 0 4 8 12 16 Control input voltage VCTL (V) 20 (Continued) 20 MB3778 Voltage gain/Phase vs. Frequency 90 0 φ −20 −90 −40 −180 10 100 1k 10 k 100 k AV 20 90 0 0 φ −20 1M −180 10 Voltage gain/Phase vs. Frequency (Actual Data) 100 AV 0 90 0 −20 −90 φ −40 −180 10 100 1k 10 k Frequency f (Hz) 100 k 100 k 1M CNF = 4700 pF 40 180 Voltage gain AV (dB) Voltage gain AV (dB) 20 1k 10 k Frequency f (Hz) Voltage gain/Phase vs. Frequency (Actual Data) Phase φ (deg) CNF = 470 pF −90 −40 Frequency f (Hz) 40 180 AV 20 90 0 0 φ −20 −90 −40 10 1M 180 Phase φ (deg) 0 CNF = 0.047 µF 40 Voltage gain AV (dB) 20 Phase φ (deg) 180 Phase φ (deg) CNF = OPEN AV 40 Voltage gain AV (dB) Voltage gain/Phase vs. Frequency (Actual Data) −180 100 1k 10 k Frequency f (Hz) 100 k 1M Actual Circuit VREF VREF CNF 4.7 kΩ 240 kΩ 4.7 kΩ − IN OUT 10 µF − + + Error Amp 4.7 kΩ 4.7 kΩ (Continued) 21 MB3778 (Continued) 700 500 620 600 444 400 500 400 300 200 100 0 −40 −20 0 +20 +40 +60 +80 Operating ambient temperature Ta (°C) 22 Power Dissipation vs. Operating ambient temperature (SSOP) Power dissipation PD (mW) Power dissipation PD (mW) Power Dissipation vs. Operating ambient temperature (SOP) +100 300 200 100 0 −40 −20 0 +20 +40 +60 +80 Operating ambient temperature Ta (°C) +100 MB3778 ■ EQUIVALENT SERIES RESISTOR AND STABILITY OF SMOOTHING CAPACITOR The equivalent series resistor (ESR) of the smoothing capacitor in the DC/DC converter greatly affects the loop phase characteristic. The stability of the system is improved so that the phase characteristic may advance the phase to the ideal capacitor by ESR in the high frequency region (see “Voltage gain vs. Frequency” and “Phase vs. Frequency”). A smoothing capacitor with a low ESR reduces system stability. Use care when using low ESR electrolytic capacitors (OS-CONTM) and tantalum capacitors. Note: OS-CON is a trademark of Sanyo Electric Co., Ltd. DC/DC Converter Basic Circuit L Tr RC VIN D RL C Voltage gain vs. Frequency Phase vs. Frequency 0 0 −20 −40 −60 10 (2) (1) : RC = 0 Ω (2) : RC = 31 mΩ 100 (1) 1k 10 k Frequency f (Hz) Phase φ (deg) Voltage gain AV (dB) 20 (2) −90 −180 100 k 10 (1) : RC = 0 Ω (2) : RC = 31 mΩ 100 1k 10 k Frequency f (Hz) (1) 100 k 23 MB3778 • Reference data If an aluminum electrolytic smoothing capacitor (RC ≅ 1.0 Ω) is replaced with a low ESR electrolytic capacitor (OS-CONTM : RC ≅ 0.2 Ω), the phase margin is reduced by half(see Fig.1 and Fig.2). DC/DC Converter AV vs. φ characteristic Test Circuit VOUT V O+ CNF AV vs. φ characteristic Between these points −IN − FB VIN +IN + R2 R1 VREF/2 Error Amp Figure 1 DC/DC Converter +5 V output Voltage gain/Phase vs. Frequency VCC = 10 V RL = 25 Ω CP = 0.1 µF 40 AV 180 φ 20 90 62 ° 0 0 VO+ + − AI Capacitor 220 µF (16 V) RC ≅ 1.0 Ω : fOSC = 1 kHz −90 −20 −40 10 Phase φ (deg) Voltage gain AV (dB) 60 100 1k Frequency f (Hz) GND −180 100 k 10 k Figure 2 DC/DC Converter +5 V output Voltage gain/Phase vs. Frequency 60 Voltage gain AV (dB) 40 90 20 φ 0 27 ° 0 −90 −20 −40 10 24 180 Phase φ (deg) VCC = 10 V RL = 25 Ω CP = 0.1 µF AV 100 1k Frequency f (Hz) 10 k −180 100 k VO+ + − OS-CONTM 22 µF (16 V) RC ≅ 0.2 Ω : fOSC = 1 kHz GND MB3778 ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage - Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. ■ ORDERING INFORMATION Part number MB3778PFV-❏❏❏ MB3778PF-❏❏❏ MB3778PFV-❏❏❏E1 MB3778PF-❏❏❏E1 Package Remarks 16-pin plastic SSOP (FPT-16P-M05) Conventional version 16-pin plastic SOP (FPT-16P-M06) Conventional version 16-pin plastic SSOP (FPT-16P-M05) Lead Free version 16-pin plastic SOP (FPT-16P-M06) Lead Free version ■ RoHS Compliance Information of Lead (Pb) Free version The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added “E1” at the end of the part number. 25 MB3778 ■ MARKING FORMAT (Lead Free version) MB3778 XXXX XXX E1 SOP-16 (FPT-16P-M06) INDEX Lead Free version Lead Free version 3778 E1XXXX XXX INDEX 26 SSOP-16 (FPT-16P-M05) MB3778 ■ LABELING SAMPLE (Lead free version) lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 Lead Free version 27 MB3778 ■ MB3778PF-❏❏❏E1, MB3778PFV-❏❏❏E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL Item Condition Mounting Method IR (infrared reflow) , Manual soldering (partial heating method) Mounting times 2 times Storage period Before opening Please use it within two years after Manufacture. From opening to the 2nd reflow Less than 8 days When the storage period after opening was exceeded Please processes within 8 days after baking (125 °C, 24H) 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) Storage conditions [Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) H rank : 260 °C Max 260 °C 255 °C 170 °C to 190 °C (b) RT (a) (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling (d) (e) (d') : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60s to 180s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10s or less : Temperature 230 °C or more, 40s or less or Temperature 225 °C or more, 60s or less or Temperature 220 °C or more, 80s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 °C Max Times : 5 s max/pin 28 (c) MB3778 ■ PACKAGE DIMENSIONS 16-pin plastic SOP (FPT-16P-M06) 16-pin plastic SOP (FPT-16P-M06) Lead pitch 1.27 mm Package width × package length 5.3 × 10.15 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 2.25 mm MAX Weight 0.20 g Code (Reference) P-SOP16-5.3×10.15-1.27 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +0.25 +.010 +0.03 *110.15 –0.20 .400 –.008 0.17 –0.04 +.001 16 .007 –.002 9 *2 5.30±0.30 7.80±0.40 (.209±.012) (.307±.016) INDEX Details of "A" part +0.25 2.00 –0.15 +.010 .079 –.006 1 "A" 8 1.27(.050) 0.47±0.08 (.019±.003) 0.13(.005) (Mounting height) 0.25(.010) 0~8˚ M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) +0.10 0.10 –0.05 +.004 .004 –.002 (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F16015S-c-4-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued) 29 MB3778 (Continued) 16-pin plastic SSOP (FPT-16P-M05) 16-pin plastic SSOP (FPT-16P-M05) Lead pitch 0.65 mm Package width × package length 4.40 × 5.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.45mm MAX Weight 0.07g Code (Reference) P-SSOP16-4.4×5.0-0.65 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 5.00±0.10(.197±.004) 0.17±0.03 (.007±.001) 9 16 *2 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 LEAD No. 1 8 0.65(.026) 0.10(.004) C 30 (Mounting height) 2003 FUJITSU LIMITED F16013S-c-4-6 "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (Stand off) (.004±.004) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. MB3778 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0605