FUJITSU MB39A102

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27232-3E
ASSP For Power Management Applications
(DC/DC Converter for DSC/Camcorder)
4-ch DC/DC Converter IC
MB39A102
■ DESCRIPTION
The MB39A102 is a 4-channel DC/DC converter IC using pulse width modulation (PWM). This IC is ideal for up
conversion, down conversion, and up/down conversion.
4ch is built in TSSOP-30P/BCC-32P package. Each channel can be controlled, and soft-start.
This is an ideal power supply for high-performance portable devices such as digital still cameras.
■ FEATURES
•
•
•
•
•
•
•
•
•
Supports for down-conversion and up/down Zeta conversion (CH1 to CH3)
Supports for up-conversion and up/down Sepic conversion (CH4)
Power supply voltage range : 2.5 V to 11 V
Reference voltage : 2.0 V ± 1 %
Error amplifier threshold voltage : 1.24 V ± 1.5 %
Built-in totem-pole type output for MOS FET
Built-in soft-start circuit without load dependence
High-frequency operation capability : 1.5 MHz (Max)
External short-circuit detection capability by −INS terminal
■ PACKAGES
30-pin plastic TSSOP
32-pad plastic BCC
(FPT-30P-M04)
(LCC-32P-M15)
MB39A102
■ PIN ASSIGNMENTS
(TOP VIEW)
CS2
1
30
CS1
−INE2
2
29
−INE1
FB2
3
28
FB1
DTC2
4
27
DTC1
VCC
5
26
VCCO
CTL
6
25
OUT1
VREF
7
24
OUT2
RT
8
23
OUT3
CT
9
22
OUT4
GND
10
21
GNDO
CSCP
11
20
−INS
DTC3
12
19
DTC4
FB3
13
18
FB4
−INE3
14
17
−INE4
CS3
15
16
CS4
(FPT-30P-M04)
(Continued)
2
MB39A102
(Continued)
CS2
CS1
−INE1
FB1
VCC
−INE2
1
FB2
N.C.
DTC2
(TOP VIEW)
(Penetration diagram from surface)
32
31
30
29
28
27
26
23
OUT1
VREF
4
22
OUT2
RT
5
21
OUT3
CT
6
20
OUT4
GND
7
19
GNDO
CSCP
8
18
−INS
N.C.
9
17
DTC4
10
11
12
13
14
15
16
FB4
3
−INE4
CTL
CS4
VCCO
CS3
24
−INE3
2
FB3
DTC1
DTC3
25
(LCC-32P-M15)
3
MB39A102
■ PIN DESCRIPTION
Block
CH1
CH2
CH3
CH4
Pin No.
Symbol
I/O
25
DTC1
I
Dead time control terminal
28
26
FB1
O
Error amplifier output terminal
29
27
−INE1
I
Error amplifier inverted input terminal
30
28
CS1
⎯
Soft-start capacitor connection terminal
25
23
OUT1
O
Output terminal
4
32
DTC2
I
Dead time control terminal
3
31
FB2
O
Error amplifier output terminal
2
30
−INE2
I
Error amplifier inverted input terminal
1
29
CS2
⎯
Soft-start capacitor connection terminal
24
22
OUT2
O
Output terminal
12
10
DTC3
I
Dead time control terminal
13
11
FB3
O
Error amplifier output terminal
14
12
−INE3
I
Error amplifier inverted input terminal
15
13
CS3
⎯
Soft-start capacitor connection terminal
23
21
OUT3
O
Output terminal
19
17
DTC4
I
Dead time control terminal
18
16
FB4
O
Error amplifier output terminal
17
15
−INE4
I
Error amplifier inverted input terminal
16
14
CS4
⎯
Soft-start capacitor connection terminal
22
20
OUT4
O
Output terminal
9
6
CT
⎯
Triangular wave frequency setting capacitor
connection terminal
8
5
RT
⎯
Triangular wave frequency setting resistor
connection terminal
6
3
CTL
I
11
8
CSCP
⎯
20
18
−INS
I
26
24
VCCO
⎯
Output block power supply terminal
5
2
VCC
⎯
Power supply terminal
7
4
VREF
O
Reference voltage output terminal
21
19
GNDO
⎯
Output block ground terminal
10
7
GND
⎯
Ground terminal
TSSOP
BCC
27
OSC
Control
Power
4
Descriptions
Power supply and control terminal
Short-circuit detection circuit capacitor connection
terminal
Short-circuit detection comparator inverted input
terminal
MB39A102
■ BLOCK DIAGRAM
Threshold voltage
accuracy ±1.5%
29
−INE1
Error
VREF
12 µA
Amp1
−
+
CS1 30
+
1.24 V
L priority
PWM
+Comp.1
+
−
CH1
26 VCCO
Drive1
Pch
25 OUT1
L priority
FB1 28
IO = 130 mA
at VCCO = 4 V
DTC1 27
Threshold voltage
accuracy ±1.5%
−INE2 2
Error
VREF
12 µA
Amp2
−
+
CS2 1
+
1.24 V
CH2
L priority
PWM
+Comp.2
+
−
Drive2
Pch
24 OUT2
L priority
FB2 3
IO = 130 mA
at VCCO = 4 V
DTC2 4
Threshold voltage
accuracy ±1.5%
−INE3 14
Error
VREF
12 µA
Amp3
−
+
CS3 15
+
1.24 V
CH3
L priority
PWM
+Comp.3
+
−
Drive3
Pch
23 OUT3
L priority
FB3 13
DTC3 12
IO = 130 mA
at VCCO = 4 V
Threshold voltage
accuracy ±1.5%
17
−INE4
Error
VREF
12 µA
Amp4
−
+
CS4 16
+
1.24 V
CH4
L priority
PWM
+Comp.4
+
−
Drive4
Nch
L priority
22 OUT4
21 GNDO
FB4 18
DTC4 19
IO = 130 mA
at VCCO = 4 V
VREF
83 kΩ
−INS 20
1V
SCP
Comp.
−
+
H:
at SCP
SCP
Error Amp Power Supply
SCP Comp. Power Supply
H:UVLO
release
CSCP 11
UVLO
OSC
Error Amp Reference
bias
1.24 V
Power
0.9 V Accuracy
0.4 V ±1%
VREF
VR1 ON/OFF
CTL
2.0 V
8 9
RT CT
5 VCC
7
VREF
10
GND
6 CTL
H : ON (Power/ ON)
L : OFF (Standby mode)
VTH = 1.4 V
5
MB39A102
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power supply voltage
VCC
Rating
Condition
Unit
Min
Max
VCC, VCCO terminals
⎯
12
V
Output current
IO
OUT1 to OUT4 terminals
⎯
20
mA
Output peak current
IOP
OUT1 to OUT4 terminals
Duty ≤ 5% (t = 1/fOSC×Duty)
⎯
400
mA
Power dissipation
PD
Ta ≤ +25 °C (TSSOP-30P)
⎯
1390*
mW
Ta ≤ +25 °C (BCC-32P)
⎯
980*
mW
−55
+125
°C
Storage temperature
⎯
TSTG
* : The packages are mounted on the epoxy board (10 cm × 10 cm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Power supply voltage
VCC
VCC, VCCO terminals
2.5
4
11
V
Reference voltage output current
IREF
VREF terminal
−1
⎯
0
mA
−INE1 to −INE4 terminals
0
⎯
VCC − 0.9
V
−INS terminal
0
⎯
VREF
V
VDTC
DTC1 to DTC4 terminals
0
⎯
VREF
V
VCTL
CTL terminal
0
⎯
11
V
OUT1 to OUT4 terminals
−15
⎯
+15
mA
*
100
500
1500
kHz
Input voltage
Control input voltage
Output current
VINE
IO
Oscillation frequency
fOSC
Timing capacitor
CT
⎯
39
100
560
pF
Timing resistor
RT
⎯
11
24
130
kΩ
Soft-start capacitor
CS
⎯
0.1
1.0
µF
CS1 to CS4 terminals
Short detection capacitor
CSCP
⎯
⎯
0.1
1.0
µF
Reference voltage output
capacitor
CREF
⎯
⎯
0.1
1.0
µF
Ta
⎯
−30
+25
+85
°C
Operating ambient temperature
* : See “■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY”.
Note : Pin numbers referred after this part are present on TSSOP-30P PKG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB39A102
■ ELECTRICAL CHARACTERISTICS
(VCC = VCCO = 4 V, Ta = +25 °C)
Symbol
Pin No
Conditions
Output voltage
VREF
7
⎯
Output voltage
temperature
variation
∆VREF/
VREF
7
Ta = −30 °C to +85 °C
Input stability
Line
7
Load stability
Load
Threshold
voltage
Error amplifier block
[Error Amp1 to Error Amp4]
SoftUnder
Triangular
Short comparator
start
voltage lockout
wave oscillator detection block
block
protection circuit
block [OSC]
[SCP]
[CS]
block [UVLO]
Reference
voltage
block [Ref]
Parameter
Value
Unit
Min
Typ
Max
1.98
2.00
2.02
V
⎯
0.5*
⎯
%
VCC = 2.5 V to 11 V
−10
⎯
+10
mV
7
VREF = 0 mA to −1 mA
−10
⎯
+10
mV
VTH
25
VCC =
1.7
1.8
1.95
V
Hysteresis
width
VH
25
⎯
0.05
0.1
0.2
V
Threshold
voltage
VTH
11
⎯
0.65
0.70
0.75
V
Input source
current
ICSCP
11
⎯
−1.4
−1.0
−0.6
µA
Reset voltage
VRST
25
VREF =
1.5
1.7
1.9
V
Oscillation
frequency
fOSC
22, 23, 24, 25
CT = 100 pF, RT = 24 kΩ
450
500
550
kHz
∆fOSC/
fOSC
22, 23, 24, 25
Ta = −30 °C to +85 °C
⎯
1*
⎯
%
Charge current
ICS
1, 15, 16, 30
CS1 to CS4 = 0 V
−16
−12
−8
µA
Threshold
voltage
VTH
3, 13, 18, 28
FB1 to FB4 = 0.65 V
1.222 1.240 1.258
V
Input bias
current
IB
2, 14, 17, 29
−INE1 to −INE4 = 0 V
−120
−30
⎯
nA
Voltage gain
AV
3, 13, 18, 28
DC
⎯
100*
⎯
dB
Frequency
bandwidth
BW
3, 13, 18, 28
AV = 0 dB
⎯
1.6*
⎯
MHz
VOH
3, 13, 18, 28
⎯
1.7
1.9
⎯
V
VOL
3, 13, 18, 28
⎯
⎯
40
200
mV
ISOURCE
3, 13, 18, 28
FB1 to FB4 = 0.65 V
⎯
−2
−1
mA
ISINK
3, 13, 18, 28
FB1 to FB4 = 0.65 V
150
200
⎯
µA
Frequency
temperature
variation
Output voltage
Output source
current
Output sink
current
(Continued)
7
MB39A102
(Continued)
(VCC = VCCO = 4 V, Ta = +25 °C)
General
Control block
[CTL]
Short detection
comparator
block
[SCP Comp.]
Output block
[Drive1 to Drive4]
PWM comparator
block
[PWM Comp.1 to
PWM Comp.4]
Parameter
Pin No.
VT0
22, 23, 24, 25
VT100
Conditions
Value
Unit
Min
Typ
Max
Duty cycle = 0 %
0.3
0.4
⎯
V
22, 23, 24, 25
Duty cycle = 100 %
⎯
0.9
1.0
V
IDTC
4, 12, 19, 27
DTC1 to DTC4 = 0.4 V
−2.0
−0.6
⎯
µA
ISOURCE
22, 23, 24, 25
Duty ≤ 5 %
(t = 1/fOSC×Duty)
OUT1 to OUT4 = 0 V
⎯
−130
−75
mA
Output sink current
ISINK
22, 23, 24, 25
Duty ≤ 5 %
(t = 1/fOSC×Duty)
OUT1 to OUT4 = 4 V
75
120
⎯
mA
Output ON
resistance
ROH
22, 23, 24, 25
OUT1 to OUT4 = −15 mA
⎯
18
27
Ω
ROL
22, 23, 24, 25
OUT1 to OUT4 = 15 mA
⎯
18
27
Ω
Threshold voltage
VTH
25
⎯
0.97
1.00
1.03
V
Input bias current
IB
20
−INS = 0 V
−29
−24
−21
µA
VIH
6
IC Active mode
1.7
⎯
11
V
VIL
6
IC Standby mode
0
⎯
0.8
V
ICTLH
6
CTL = 3 V
5
30
60
µA
ICTLL
6
CTL = 0 V
⎯
⎯
1
µA
ICCS
5
CTL = 0 V
⎯
0
2
µA
ICCSO
26
CTL = 0 V
⎯
0
2
µA
ICC
5
CTL = 3 V
⎯
2.1
4.5
mA
Threshold voltage
Input current
Output source
current
CTL input voltage
Input current
Standby current
Power supply
current
*: Standard design value.
8
Symbol
MB39A102
■ TYPICAL CHARACTERISTICS
Power Supply Current vs. Power Supply Voltage
Reference Voltage vs. Power Supply Voltage
5
Ta = +25 °C
CTL = 3 V
Reference voltage VREF (V)
Power supply current ICC (mA)
5
4
3
2
1
0
Ta = +25 °C
CTL = 3 V
VREF= 0 mA
4
3
2
1
0
0
2
4
6
8
10
12
0
2
Power supply voltage VCC (V)
4
6
8
10
12
Power supply voltage VCC (V)
Reference Voltage vs. Operating Ambient Temperature
2.05
VCC = 4 V
CTL = 3 V
VREF= 0 mA
Reference voltage VREF (V)
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta (°C)
CTL terminal Current vs. CTL terminal Voltage
Reference Voltage vs. CTL terminal Voltage
Ta = +25 °C
VCC = 4 V
VREF= 0 mA
CTL = 3 V
4
3
2
1
0
0
2
4
6
8
10
CTL terminal voltage VCTL (V)
12
200
CTL terminal current ICTL (µA)
Reference voltage VREF (V)
5
Ta = +25 °C
VCC = 4 V
180
160
140
120
100
80
60
40
20
0
0
2
4
6
8
10
12
CTL terminal voltage VCTL (V)
(Continued)
9
MB39A102
Triangular Wave Oscillation Frequency
vs. Timing Resistor
Ta = +25 °C
VCC = 4 V
CTL = 3 V
1000
100
CT = 560 pF
CT = 39 pF
CT = 100 pF
CT = 220 pF
10000
Triangular wave oscillation
frequency fOSC (kHz)
Triangular wave oscillation
frequency fOSC (kHz)
10000
Triangular Wave Oscillation Frequency
vs. Timing Capacitor
1000
100
10
RT = 130 kΩ
RT = 11 kΩ
RT = 24 kΩ
RT = 56 kΩ
10
1
10
100
1000
Timing resistor RT (kΩ)
1.00
Upper
0.90
0.80
0.70
0.60
0.50
Lower
0.40
0.30
0.20
0
200
400
1000
10000
1.20
Ta = +25 °C
VCC = 4 V
CTL = 3 V
RT = 24 kΩ
1.10
100
Triangular Wave Upper and Lower Limit Voltage
vs. Operating Ambient Temperature
Triangular wave upper and
lower limit voltage VCT (V)
1.20
10
Timing capacitor CT (pF)
Triangular Wave Upper and Lower Limit Voltage
vs. Triangular Wave Oscillation Frequency
Triangular wave upper and
lower limit voltage VCT (V)
Ta = +25 °C
VCC = 4 V
CTL = 3 V
600
800 1000 1200 1400 1600
Triangular wave oscillation frequency fOSC (kHz)
VCC = 4 V
1.10 CTL = 3 V
1.00 RT = 24 kΩ
CT = 100 pF
0.90
Upper
0.80
0.70
0.60
0.50
Lower
0.40
0.30
0.20
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
Triangular wave oscillation
frequency fOSC (kHz)
Triangular Wave Oscillation Frequency
vs. Operating ambient Temperature
560
VCC = 4 V
CTL = 3 V
RT = 24 kΩ
CT = 100 pF
540
520
500
480
460
440
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
(Continued)
10
MB39A102
(Continued)
Ta = +25 °C
180
VCC = 4 V
40
240 kΩ
AV
30
ϕ
20
90
10
0
0
−10
−20
−90
−30
−40
Phase φ (deg)
Error amplifier voltage gain AV (dB)
Error Amplifier Voltage Gain, Phase vs. Frequency
10 kΩ
1 µF
+
2.4 kΩ
IN
−INE1
29
−
30
CS1
10 kΩ
1.5 V
1k
10 k
100 k
1M
OUT
1.24 V
Error Amp1
the same as other channels
−180
100
28
+
+
10 M
Frequency f (Hz)
Power Dissipation vs.
Operating Ambient Temperature
(BCC-32P)
Power Dissipation vs.
Operating Ambient Temperature
(TSSOP-30P)
Power dissipation PD (mW)
Power dissipation PD (mW)
1600
1400
1390
1200
1000
800
600
400
200
0
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
1000
980
800
600
400
200
0
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
11
MB39A102
■ FUNCTIONS
1. DC/DC Converter Functions
(1) Reference voltage block (Ref)
The reference voltage circuit generates a temperature-compensated reference voltage (2.0 V Typ) from the
voltage supplied from the VCC terminal (pin 5). The voltage is used as the reference voltage for the IC’s internal
circuitry.
The reference voltage can supply a load current of up to 1 mA to an external device through the VREF terminal
(pin 7).
(2) Triangular-wave oscillator block (OSC)
The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to
the CT terminal (pin 9) and RT terminal (pin 8) to generate triangular oscillation waveform amplitude of 0.4 V to
0.9 V.
The triangular waveforms are input to the PWM comparator in the IC.
(3) Error amplifier block (Error Amp1 to Error Amp4)
The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition,
an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to
inverted input terminal of the error amplifier, enabling stable phase compensation to the system.
Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the
CS1 terminal (pin 30) to CS4 terminal (pin 16) while are the non-inverted input terminal for Error Amp. The use
of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is
independent of the output load on the DC/DC converter.
(4) PWM comparator block (PWM Comp.1 to PWM Comp.4)
The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/
output voltage.
The output transistor turns on while the error amplifier output voltage and DTC voltage remain higher than the
triangular wave voltage.
(5) Output block (Drive1 to Drive4)
The output block is in the totem pole configuration, capable of driving an external P-channel MOS FET (channels
1 to 3), and N-channel MOS FET (channel 4).
12
MB39A102
2. Channel Control Function
The main or each channel is turned on and off depending on the voltage levels at the CTL terminal (pin 6), CS1
terminal (pin 30), CS2 terminal (pin 1), CS3 terminal (pin 15), and CS4 terminal (pin 16).
Channel On/Off Setting Conditions
CTL
CS1
CS2
CS3
CS4
Power
CH1
CH2
CH3
CH4
L
⎯*
⎯*
⎯*
⎯*
OFF
OFF
OFF
OFF
OFF
H
H
H
H
H
H
GND
High-Z
GND
GND
GND
High-Z
GND
GND
High-Z
GND
GND
High-Z
GND
GND
GND
High-Z
GND
High-Z
GND
GND
GND
GND
High-Z
High-Z
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
*: Undefined
3. Protective Functions
(1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.)
The short-circuit detection comparator in each channel detects the output voltage level of Error Amp, and if any
channel output voltage of Error Amp reaches the short-circuit detection voltage, the timer circuits are actuated
to start charging the external capacitor CSCP connected to the CSCP terminal (pin 11).
When the capacitor (CSCP) voltage reaches about 0.7 V, the circuit is turned off the output transistor and sets the
dead time to 100 %.
In addition, the short-circuit detection from external input is capable by using −INS terminal (pin 20) on shortcircuit detection comparator (SCP Comp.) .
To release the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 7) voltage to 1.5 V (Min) or less. (See “■SETTING TIME
CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”.)
(2) Under voltage lockout protection circuit (UVLO)
The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned
on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent such
malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage with respect
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the
CSCP terminal (pin 11) at the “L” level.
The circuit restores the output transistor to normal when the supply voltage reaches the threshold voltage of the
under voltage lockout protection circuit.
■ PROTECTION CIRCUIT OPERATING FUNCTION TABLE
This table refers to output condition when protection circuit is operating.
Operating circuit
OUT1
OUT2
OUT3
OUT4
Short-circuit protection circuit
H
H
H
L
Under voltage lockout protection circuit
H
H
H
L
13
MB39A102
■ SETTING THE OUTPUT VOLTAGE
• CH1 to CH4
VO
R1
−
R2
−INEx
Error
Amp
+
+
VO (V) =
1.24
R2
(R1 + R2)
1.24 V
CSx
x : Each channel No.
■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY
The triangular oscillation frequency is determined by the timing capacitor (CT) connected to the CT terminal (pin
9), and the timing resistor (RT) connected to the RT terminal (pin 8).
Moreover, it shifts more greatly than the calculated values according to the constant of timing resistor (RT) when
the triangular wave oscillation frequency exceeds 1 MHz. Therefore, set it referring to “Triangular Wave Oscillation
Frequency vs. Timing Resistor” and “Triangular Wave Oscillation Frequency vs. Timing Capacitor” in “■ TYPICAL
CHARACTERISTICS”.
Triangular oscillation frequency : fOSC
fOSC (kHz) =:
14
1200000
CT (pF) × RT (kΩ)
MB39A102
■ SETTING THE SOFT-START TIME
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 to CS4 ) to the CS1 terminal (pin 30) to the CS4 terminal (pin 16), respectively.
Setting each CTLx from “H” to “L” switches to charge the external soft-start capacitors (CS1 to CS4) connected
to the CS1 terminal (pin 30) to CS4 terminal (pin 16) at 12 µA.
The error amplifier output (FB1 to FB4) is determined by comparison between the lower one of the potentials
at two non-inverted input terminals (1.24 V, CS terminal voltages) and the inverted input terminal voltage (−INE1
to−INE4).
The FB terminal voltage during the soft-start period (CS terminal voltage < 1.24 V) is therefore determined by
comparison between the −INE terminal and CS terminal voltages. The DC/DC converter output voltage rises in
proportion to the CS terminal voltage as the soft-start capacitor connected to the CS terminal is charged.
The soft-start time is obtained from the following formula:
Soft-start time: ts (time to output 100%)
ts (s) =: 0.103 × CSX (µF)
• Soft-Start Circuit
VO
VREF
12 µA
R1
−INEx
R2
L priority
Error Amp
CH ON/OFF signal
L : ON, H : OFF
−
CSx
+
+
1.24 V
CTLx
CSx
FBx
UVLO
x : Each channel No.
15
MB39A102
■ TREATMENT WITHOUT USING CS TERMINAL
When not using the soft-start function, open the CS1 terminal (pin 30) , the CS2 terminal (pin 1) , the CS3
terminal (pin 15) , the CS4 terminal (pin 16) .
• Without Setting Soft-Start Time
“OPEN”
“OPEN”
1
CS2
CS1
30
“OPEN”
“OPEN”
15
16
CS3
CS4
16
MB39A102
■ SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT
Each channel uses the short-circuit detection comparator (SCP) to always compare the error amplifier′s output
level to the reference voltage.
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output
remains at “L” level, and the CSCP terminal (pin 11) is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to “H” level. This causes the
external short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 11) to be charged at 1 µA.
Short-circuit detection time (tCSCP)
tCSCP (s) =: 0.70 × CSCP (µF)
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.70 V), the latch is set and the external
FET is turned off (dead time is set to 100%). At this point, the latch input is closed and the CSCP terminal (pin
11) is held at “L” level.
In addition, the short-circuit detection from external input is capable by using −INS terminal (pin 20) on the shortcircuit detection comparator (SCP Comp.) . The short-circuit detection operation starts when −INS terminal
voltage is less than threshold voltage (VTH =: 1 V) .
When the power supply is turn on back or VREF terminal (pin 7) voltage is less than 1.5 V (Min) by setting CTL
terminal (pin 6) to “L” level, the latch is released.
• Timer-latch short-circuit protection circuit
VO
FBx
R1
−
−INEx
Error
Amp
+
R2
1.24 V
VREF
83 kΩ
−INS
−
20
SCP
Comp.
+
SCP
1V
+
+
+
+
−
1.15 V
1 µA
To each channel
Drive
CTL
CSCP
11
CSCP
VREF
S
R
Latch
UVLO
x : Each channel No.
17
MB39A102
■ TREATMENT WITHOUT USING CSCP TERMINAL
When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 11) to GND (pin
10) with the shortest distance.
• Treatment without using CSCP
18
10
GND
11
CSCP
MB39A102
■ SETTING THE DEAD TIME
When the device is set for step-up inverted output based on the step-up or step-up/down Zeta conversion, stepup/down Sepic conversion or flyback conversion, the FB terminal voltage may reach and exceed the triangular
wave voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state
(ON duty = 100 %). To prevent this, set the maximum duty of the output transistor. To set it, set the voltage at
the DTC terminal by applying a resistive voltage divider to the VREF voltage as shown below.
When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.
The maximum duty calculation formula assuming that triangular wave amplitude =: 0.5 V and triangular wave
lower voltage =: 0.4 V is given below.
DUTY (ON) Max=:
Vdt − 0.4 V
× 100 (%) , Vdt =
0.5 V
Rb
Ra + Rb
× VREF
When the DTC terminal is not used, connect it directly to the VREF terminal (pin 7) as shown below (when no
dead time is set).
• When using DTC to set dead time
Ra
DTCx
Rb
7
VREF
Vdt
x : Each channel No.
• When no dead time is set
DTCx
7
VREF
x : Each channel No.
19
MB39A102
■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds threshold
voltage (VTH) of UVLO (under voltage lockout protection circuit), UVLO are released, and the operation of output
Drive circuit of each channel becomes possible.
When CTL is off, VR and VREF fall. When VREF decreases and UVLO fall below each reset voltage (VRST),
UVLO operates and output Drive circuit of each channel is forcibly done the operation stop, and makes the output
off state.
When period to reaching to 2.0 V by VREF voltage after UVLO are released by turning on CTL (refer to a in
“• Timing Chart”), and VREF decreases from 2.0 V after turning off CTL and the period until do the operation
of UVLO (refer to a’ in “• Timing Chart”), the bias voltage and the bias current in IC do not reach a prescribed
value because VREF which is the reference voltage does not reach 2.0 V, and the speed of response for IC has
decreased.
Note : Moreover, when it does the turning on and off of the input sudden change, the load sudden change, IC
cannot conform and the output might overshoot.
Therefore, impress the voltage to CTL terminal by which the VREF terminal voltage never stays in the abovementioned period.
• CTL Block Equivalent Circuit
H : at SCP
To CH1 to CH4 output Drive circuit
H : Possible to operate
L : Forcibly stop
SCP
To CS1 to CS4 charge/
discharge circuit
H : Possible to charge
L : Forcibly discharge
UVLO
H : UVLO release
ErrorAmp Reference
1.24 V
bias
5
VREF
7
VREF
20
VR
Power
ON/OFF
CTL
6
VCC
CTL
MB39A102
• Timing Chart
Error Amp
Reference
voltage VR
VR = 1.24 V (Typ)
VTH
VREF = 2.00 V (Typ)
Reference
voltage VREF
a
UVLO
UVLO release
VRST
a'
Valid UVLO
CH1 to CH4
output Drive
circuit control
CTL terminal
voltage
Possible operate
Fixed full-off
Fixed full-off
1.5 V ± 0.2 V (Typ)
21
MB39A102
■ I/O EQUIVALENT CIRCUIT
〈〈Reference voltage block〉〉
〈〈Control block〉〉
〈〈Soft-start block〉〉
VREF
(2.0 V)
VCC 5
1.24 V
ESD
protection
element
+
−
CTL 6
67
kΩ
7 VREF
ESD
protection
element
CSx
77.3
kΩ
104
kΩ
ESD
protection
element
124
kΩ
GND
GND 10
GND
〈〈Triangular wave oscillator
block (CT) 〉〉
〈〈Triangular wave oscillator
block (RT) 〉〉
〈〈Short detection block〉〉
VREF
(2.0 V)
VREF
(2.0 V)
VREF
(2.0 V)
0.7 V
2 kΩ
+
−
11 CSCP
CT 9
8 RT
GND
GND
GND
〈〈Short detection comparator block〉〉
〈〈Error amplifier block (CH1 to CH4) 〉〉
VCC
VCC
VREF
(2.0 V)
−INEx
VREF
(2.0 V)
−INS 20
CSx
83 kΩ
(1 V)
FBx
1.24 V
GND
GND
〈〈PWM comparator block (CH1 to CH4) 〉〉
VCC
FBx
〈〈Output block (CH1 to CH4) 〉〉
VCCO 26
OUTx
CT
DTCx
GNDO 21
GND
x : Each channel No.
22
MB39A102
■ APPLICATION EXAMPLE
VIN
(2.5 V to 6 V)
R13R14 −INE1
29
A
3.3 kΩ12 kΩ 15 kΩ
R15
CS1
30
C20
R16
0.1 µF
2 kΩ
C21
28
0.047 µF
FB1
27
DTC1
−INE2
R19R20
2
B
2.4 kΩ43 kΩ 15 kΩ
R21
CS2
1
C22
R22
0.1 µF
2 kΩ
C23
0.047 µF FB2 3
R23 33 kΩ
4
DTC2
R24 20 kΩ
−INE3
R25R26
14
C
2.4 kΩ43 kΩ 15 kΩ
R27
CS3
15
C24
R28
0.1 µF
2 kΩ
C25
0.047 µF FB3 13
R29 33 kΩ
12
DTC3
R30 20 kΩ
R31R32 −INE4
17
D
3 kΩ22 kΩ 15 kΩ
R33
CS4
16
C26
R34
0.1 µF
1 kΩ
C27
0.1 µF FB4 18
R35
19
30 kΩ
DTC4
R36
−INS
18 kΩ
20
VCCO
26
VD
C1
0.1 µF
25
OUT1
CH1
L2
22 µH
C4
1 µF
C6
4.7 µF
D1
VG
VO2-1
15 V, 10 mA
B
D2
Q2
T1
C9
VO2-2
2.2 µF
5 V, 50 mA
D3
C10
2.2 µF
OUT2
24
CH2
VO1
2.5 V,
250 mA
A
Q1
C8
1 µF
D4
VO2-3
−7.5 V, −5 mA
C11
2.2 µF
OUT3
23
CH3
VO3-1
15 V, 10 mA
C
D5
Q4
C14
2.2 µF
D6
C13
1 µF
OUT4
22
GNDO
21
CH4
T2
VC
D
L3
C18
10 µH
R12
180 Ω
C16
C17
4700 pF 1 µF
Short detection signal
(L : at short)
CSCP
11
VCC
5
C28
0.01 µF
C15
2.2
µF
4.7
µF
D7
VO3-2
5 V, 50 mA
VO4
3.3 V, 500 mA
C19
10 µF
L4
15 µH
VB
C2
0.1 µF
6
CTL
8
RT
R37
24 kΩ
9
CT
7
fOSC
Accuracy ±10%
C29
100 pF
10
VREF
C30
0.1 µF
GND
H : ON (Power ON)
L : OFF (Standby mode)
VTH = 1.4 V
23
MB39A102
■ PARTS LIST
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS NO.
Q1, Q2, Q4
Q5
Pch FET
NPN Tr
VDS = −20 V, ID = −1.5 A
VCEO = 15 V, IC = 3 A
SANYO
SANYO
MCH3309
CPH3206
D1, D7
D2 to D6
Diode
Diode
VF = 0.4 V (Max) , at IF = 1 A
VF = 0.55 V (Max) , at IF = 0.5 A
SANYO
SANYO
SBS004
SB05-05CP
L2
L3
L4
Inductor
Inductor
Inductor
22 µH
10 µH
15 µH
0.63 A, 160 mΩ
0.94 A, 67 mΩ
0.76 A, 120 mΩ
TDK
TDK
TDK
RLF5018T-220MR63
RLF5018T-100MR94
RLF5018T-150MR76
T1, T2
Transformer
⎯
⎯
SUMIDA
CLQ52 5388-T095
C1, C2
C4, C8, C13
C6
C9 to C11
C14, C15
C16
C17
C18
C19
C20, C22, C24
C21, C23, C25
C26, C27, C30
C28
C29
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
0.1 µF
1 µF
4.7 µF
2.2 µF
2.2 µF
4700 pF
1 µF
4.7 µF
10 µF
0.1 µF
0.047 µF
0.1 µF
0.01 µF
100 pF
50 V
25 V
10 V
16 V
16 V
50 V
25 V
10 V
6.3 V
50 V
50 V
50 V
50 V
50 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C1608JB1H104K
C3216JB1E105K
C3216JB1A475M
C3216JB1C225K
C3216JB1C225K
C1608JB1H472K
C3216JB1E105K
3216JB1A475M
C3216JB0J106M
C1608JB1H104K
C1608JB1H473K
C1608JB1H104K
C1608JB1H103K
C1608CH1H101J
R12
R13
R14
R15, R21, R27
R16, R22, R28
R19, R25
R20, R26
R23, R29
R24, R30
R31
R32
R33
R34
R35
R36
R37
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
180 Ω
3.3 kΩ
12 kΩ
15 kΩ
2 kΩ
2.4 kΩ
43 kΩ
33 kΩ
20 kΩ
3 kΩ
22 kΩ
15 kΩ
1 kΩ
30 kΩ
18 kΩ
24 kΩ
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
RR0816P-181-D
RR0816P-332-D
RR0816P-123-D
RR0816P-153-D
RR0816P-202-D
RR0816P-242-D
RR0816P-433-D
RR0816P-333-D
RR0816P-203-D
RR0816P-302-D
RR0816P-223-D
RR0816P-153-D
RR0816P-102-D
RR0816P-303-D
RR0816P-183-D
RR0816P-243-D
Note : SANYO : SANYO Electric Co., Ltd.
TDK : TDK Corporation
SUMIDA : SUMIDA Electric Co., Ltd.
ssm : SUSUMU Co., Ltd.
24
MB39A102
■ REFERENCE DATA
TOTAL Efficiency vs. Input Voltage
100
TOTAL efficiency η (%)
Ta = +25 °C
VO1 = 2.5 V, 250 mA
VO2-1 = 15 V, 10 mA
VO2-2 = 5 V, 50 mA
VO2-3 = −7.5 V, −5 mA
VO3-1 = 15 V, 10 mA
VO3-2 = 5 V, 50 mA
VO4 = 3.3 V, 500 mA
fOSC = 500 kHz
At VIN =: 2.59 V
CH1stops by short-circuit
detection operation
95
90
85
80
75
70
65
60
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Input voltage VIN (V)
Each CH Efficiency vs. Input Voltage
100
Each CH efficiency η (%)
Ta = +25 °C
CH1
95
90
85
80
CH4
CH2
CH3
75
Note : Only concerned CH is ON
Include external SW Tr operating current
CH2 and CH3 are discontinuance.
70
65
60
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Input voltage VIN (V)
(Continued)
25
MB39A102
Conversion Efficiency vs. Load Current (CH1)
100
Conversion efficiency η (%)
CH2 to CH4 : OFF
95
90
IO1 ≤ 20 mA : discontinuance mode
85
80
75
70
Ta = +25 °C
VIN = 3.6 V
65
60
0
50
100
150
200
250
300
Load current IO1 (mA)
Conversion Efficiency vs. Load Current (CH2, CH3)
Conversion efficiency η (%)
100
Ta = +25 °C
VIN = 3.6 V
VO2-1 = 10 mA
VO2-3 = −5 mA
VO3-1 = 10 mA
95
90
85
CH2
CH1, 3, 4 : OFF
80
CH3
75
CH1, 2, 4 : OFF
70
65
Note : CH2 and CH3 are discontinuance mode.
60
0
10
20
30
40
50
Load current lO2-2, IO3-2 (mA)
(Continued)
26
MB39A102
Conversion Efficiency vs. Load Current (CH4)
Conversion efficiency η (%)
100
Ta = +25 °C
VIN = 3.6 V
95
90
CH1 to CH3 : OFF
85
80
IO4 ≤ 175 mA : discontinuance mode
75
70
65
60
0
100
200
300
400
500
600
Load current IO4 (mA)
(Continued)
27
MB39A102
(Continued)
Switching Wave Form (CH1)
Ta = +25 °C
VIN = 4 V
CTL = 5 V
VG (V)
4
2
0
VD (V)
4
2
0
0
1
2
3
4
5
6
7
8
9
10
t (µs)
Switching Wave Form (CH4)
VB (V)
2
Ta = +25 °C
VIN = 4 V
CTL = 5 V
1
0
−1
VC (V)
10
5
0
0
28
1
2
3
4
5
6
7
8
9
10
t (µs)
MB39A102
■ USAGE PRECAUTION
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
The use of negative voltages below –0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ ORDERING INFORMATION
Part number
Package
MB39A102PFT
30-pin plastic TSSOP
(FPT-30P-M04)
MB39A102PV3
32-pad plastic BCC
(LCC-32P-M15)
Remarks
29
MB39A102
■ PACKAGE DIMENSIONS
30-pin plastic TSSOP
(FPT-30P-M04)
7.80±0.10(.307±.004)
"A"
Details of "A" part
0~8°
1.10(.043)
MAX
0.60±0.10
(.024±.004)
+0.20
4.40 –0.10
6.40±0.10
+.008
.173 –.004 (.252±.004)
INDEX
0.25(.010)
0.10±0.05
(.004±.002)
0.50(.020)
0.20±0.03
(.008±.001)
0.10(.004)
7.00(.276)
C
0.3865(.0152)
0.127±0.03
(.005±.001)
0.90±0.05
(.035±.002)
0.3865(.0152)
2001 FUJITSU LIMITED F30007SC-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
30
MB39A102
(Continued)
32-pad plastic BCC
(LCC-32P-M15)
4.25(.167)TYP
0.50(.020)TYP
5.00±0.10(.197±.004)
25
0.80(.031)MAX
(Mount height)
17
INDEX AREA
1
4.25(.167)
TYP 0.50(.020)
TYP
0.50±0.10
(.020±.004)
5.00±0.10
(.197±.004)
0.075±0.025
(.003±.001)
(Stand off)
9
9
Details of "A" part
0.05(.002)
0.14(.006)
MIN
0.55±0.06
(.022±.002)
C0.2(.008)
25
3.00(.118)
REF
"C"
"A"
"B"
3.00(.118)REF
Details of "B" part
0.30±0.06
(.012±.002)
C
0.50±0.10
(.020±.004)
17
1
Details of "C" part
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
2005 FUJITSU LIMITED C32067S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
31
MB39A102
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0511
© 2005 FUJITSU LIMITED Printed in Japan