FUJITSU MB89PV490

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12560-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89498/F499/PV490
■ DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit single-chip microcontrollers.
In addition to a compact instruction set, the general-purpose, single-chip microcontroller contains a variety of
peripheral functions such as 21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote
receiver circuit, LCD controller/driver, external interrupt 0 (edge) , external interrupt 1 (level) , 10-bit A/D converter,
UART/SIO, SIO, I2C and watchdog timer reset.
The MB89490 series is designed suitable for compact disc/radio receiver controller as well as in a wide range of
applications for consumer product.
* : “F2MC”, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.
■ FEATURES
• Package
QFP, LQFP package for MB89F499, MB89498
MQFP package for MB89PV490
(Continued)
■ PACKAGES
100-pin Plastic QFP
100-pin Plastic LQFP
100-pin Ceramic MQFP
(FTP-100P-M06)
(FTP-100P-M05)
(MQP-100C-P01)
MB89490 Series
(Continued)
• High speed operating capability at low voltage
• Minimum execution time : 0.32 µs/12.5 MHz
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Branch instructions by test bit
Bit manipulation instructions, etc.
• PLL circuit for sub-clock
• Embedded for PLL clock multiplication circuit for sub-clock
• Operating clock (PLL for sub-clock) can be selected from no multiplication or 4 times of the sub-clock
oscillation frequency.
• 6 timers
PWM timer × 2
8/16-bit timer/counter × 2
21-bit timebase timer
Watch prescaler
• External interrupt
Edge detection (selectable edge) : 8 channels
Low level interrupt (wake-up function) : 8 channels
• 10-bit A/D converter (8 channels)
10-bit successive approximation type
• UART/SIO
Synchronous/asynchronous data transfer capability
• SIO
Switching of synchronous data transfer capability
• LCD controller/driver
Max 32 segments output × 4 commons
• I2C interface circuit
• Remote receiver circuit
• Low-power consumption mode
Stop mode (oscillation stops so as to minimize the current consumption.)
Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.)
Watch mode (operation except the watch prescaler stops so as to reduce the power comsumption to an
extremely low level.)
Sub-clock mode
• Watchdog timer reset
• I/O ports : Max 66 channels
2
MB89490 Series
■ PRODUCT LINEUP
Part number
Parameter
MB89498
MB89F499
MB89PV490
Mass production products
(mask ROM product)
FLASH
Piggy-back
(For evaluation or
development)
ROM size
48 K × 8-bit
(internal ROM)
60 K × 8-bit
(internal FLASH)
60 K × 8-bit
(external ROM) *1
RAM size
2 K × 8-bit
2 K × 8-bit
2 K × 8-bit
Classification
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Minimum interrupt processing time
: 136
: 8-bit
: 1 to 3 bytes
: 1-bit, 8-bit, 16-bit
: 0.32 µs/12.5 MHz
: 2.88 µs/12.5 MHz
Ports
General-purpose I/O ports (CMOS)
Input ports (CMOS)
N-channel open drain I/O ports
Total
: 56 pins
: 2 pins
: 8 pins
: 66 pins
21-bit timebase
timer
Interrupt generation cycle (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz
Watchdog timer
Reset generation cycle (167.8 ms to 335.5 ms) at 12.5 MHz
PWM timer 0, 1
8-bit reload timer operation (supports square wave output and operating clock period :
1 tinst, 8 tinst, 16 tinst, 64 tinst )
8-bit accuracy PWM operation
8/16-bit timer/counter
00, 01
Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each
with its own independent operating clock) , or as one 16-bit timer/counter.
In timer 00 or 16-bit timer/counter operation, event counter operation by external clock
input and square wave output capability
8/16-bit timer/counter
10, 11
Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each
with its own independent operating clock) , or as one 16-bit timer/counter.
In timer 10-bit or 16-bit timer/counter operation, event counter operation by external clock
input and square wave output capability
External interrupt 0
(edge)
8 independent channels (selectable edge, interrupt vector, request flag)
External interrupt 1
(level)
8 channels (low level interrupt)
A/D converter
10-bit accuracy × 8 channels
A/D conversion function (conversion time : 30 tinst )
Supports repeated activation by internal clock
LCD controller/driver
Common output
Segment output
LCD driving power (bias) pins
LCD display RAM size
: 4 (Max)
: 32 (Max)
:3
: 32 × 4 bits
(Continued)
3
MB89490 Series
(Continued)
Part number
Parameter
MB89498
MB89PV490
UART/SIO
Synchronous/asynchronous data transfer capability
(Max baud rate : 97.656 Kbps at 12.5 MHz)
(7-bit and 8-bit with parity bit; 8-bit and 9-bit without parity bit)
SIO
8-bit serial I/O with LSB first/MSB first selectability
1 clock selectable from 4 operation clock (1 external shift clock and 3 internal shift clock :
0.64 µs, 2.56 µs, 10.24 µs at 12.5 MHz)
I2C*2
1 channel
(Use a 2-wire protocol to communicate with other device)
Remote receiver
circuit
Selectable maximum noise width removal
Reversible input polarity
Standby mode
Sleep mode, stop mode, watch mode and sub-clock mode
Process
CMOS
Operating voltage
2.2 V to 3.6 V
*1 : Use MBM27C512 as the external ROM.
*2 : I2C is complied to Philips I2C specification.
4
MB89F499
2.7 V to 3.6 V
2.7 V to 3.6 V
MB89490 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Part number
MB89498
MB89F499
MB89PV490
FPT-100P-M06
O
O
×
FPT-100P-M05
O
O
×
MQP-100C-P01
×
×
O
Parameter
O : Availabe
× : Not available
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggy-back product, verify its differences from the product that will be actually used.
Take particular care on the following point : The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV490, add the current consumed by the EPROM mounted in the piggy-back socket.
• When operating at low speed, the current consumed by the FLASH product is greater than that for the mask
ROM product. However, the current consumption is roughly the same in sleep and stop mode.
• For more information, see “■ ELECTRICAL CHARACTERISTICS.”
3. Oscillation Stabilization Wait Time after Power-on Reset
• For MB89PV490 and MB89F499, the power-on stabilization wait time cannot be selected after power-on reset.
• For MB89498, the power-on stabilization wait time can be selected after power-on reset.
• For more information, please refer to “■ MASK OPTIONS”.
5
MB89490 Series
■ PIN ASSIGNMENTS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VSS
X0
X1
MOD0
RST
P84
P83
P82/SCK1
P81/SO1
P80/SI1
P77/SEG31
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
VCC
AVSS
P30/AN0/INT10
P31/AN1/INT11
P32/AN2/INT12
P33/AN3/INT13
P34/AN4/INT14
P35/AN5/INT15
P36/AN6/INT16
P37/AN7/INT17
*P40
*P41
*P42
*P43
*P44
*P45
*P46/SCL
*P47/SDA
X1A
X0A
VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
AVCC
(FPT-100P-M06)
* : High current pins
(Continued)
6
MB89490 Series
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
*P01
*P00
VCC
VSS
X0
X1
MOD0
RST
P84
P83
P82/SCK1
P81/SO1
P80/SI1
P77/SEG31
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
P65/SEG21
P64/SEG20
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
AVR
AVCC
AVSS
P30/AN0/INT10
P31/AN1/INT11
P32/AN2/INT12
P33/AN3/INT13
P34/AN4/INT14
P35/AN5/INT15
P36/AN6/INT16
P37/AN7/INT17
*P40
*P41
*P42
*P43
*P44
*P45
*P46/SCL
*P47/SDA
X1A
X0A
VSS
VCC
V3
V2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
*P02
*P03
*P04
*P05
*P06
*P07
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
(FPT-100P-M05)
* : High current pins
(Continued)
7
MB89490 Series
(Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VSS
X0
X1
MOD0
RST
P84
P83
P82/SCK1
P81/SO1
P80/SI1
P77/SEG31
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
(TOP VIEW)
113
112
111
110
109
108
107
106
105
130
131
132
101
102
103
104
121
122
123
124
125
126
127
128
129
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
120
119
118
117
116
115
114
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AVSS
P30/AN0/INT10
P31/AN1/INT11
P32/AN2/INT12
P33/AN3/INT13
P34/AN4/INT14
P35/AN5/INT15
P36/AN6/INT16
P37/AN7/INT17
*P40
*P41
*P42
*P43
*P44
*P45
*P46/SCL
*P47/SDA
X1A
X0A
VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
AVCC
* : High current pins
(MQP-100C-P01)
Pin assignment on package top (MB89PV490 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
101
N.C.
108
A3
115
O3
122
O8
129
A8
102
A15
109
A2
116
VSS
123
CE
130
A13
103
A12
110
A1
117
N.C.
124
A10
131
A14
104
A7
111
A0
118
O4
125
OE
132
VCC
105
A6
112
N.C.
119
O5
126
N.C.
106
A5
113
O1
120
O6
127
A11
107
A4
114
O2
121
O7
128
A9
N.C. : As connected internally, do not use.
8
MB89490 Series
■ PIN DESCRIPTION
Pin number
MQFP*1/
LQFP*3
QFP*2
99
96
Pin name
I/O circuit
type
Function
A
Connection pins for a crystal or other oscillator circuit.
An external clock can be connected to X0. In this case, leave
X1 open.
A
Connection pins for a crystal or other oscillator circuit.
An external clock can be connected to X0A. In this case, leave
X1A open.
X0
98
95
X1
49
46
X0A
48
45
X1A
97
94
MOD0
B
Input pin for setting the memory access mode.
Connect directly to VSS.
95, 94
92, 91
P84, P83
J
General-purpose CMOS input port.
96
93
RST
C
Reset I/O pin. The pin is an N-ch open-drain type with pull-up
resistor and hysteresis input. The pin outputs an “L” level when
an internal reset request is present. Inputting an “L” level initializes internal circuits.
2 to 9
99 to 6
P00 to P07
D
General-purpose CMOS I/O port.
10 to 17 7 to 14
P10/INT00
to
P17/INT07
E
General-purpose CMOS I/O port.
The pin is shared with external interrupt 0 input.
18
15
P20/TO0
F
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00 and 01 output.
19
16
P21/RMC
E
General-purpose CMOS I/O port.
The pin is shared with remote receiver input.
20
17
P22/EC0
E
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00 and 01 input.
21
18
P23
F
General-purpose CMOS I/O port.
22
19
P24/TO1
F
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10 and 11 output.
23
20
P25/EC1
E
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10 and 11 input.
24
21
P26/PWM0
F
General-purpose CMOS I/O port.
The pin is shared with PWM0 output.
25
22
P27/PWM1
F
General-purpose CMOS I/O port.
The pin is shared with PWM1 output.
32 to 39 29 to 36
P30/AN0/INT10
to
P37/AN7/INT17
G
General-purpose CMOS I/O port.
The pin is shared with external interrupt 1 input and A/D
converter input.
40 to 45 37 to 42
P40 to P45
H
General-purpose N-ch open-drain I/O port.
P46/SCL
H
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C clock I/O.
46
43
(Continued)
9
MB89490 Series
(Continued)
Pin number
MQFP*1/
LQFP*3
QFP*2
I/O circuit
type
Function
47
44
P47/SDA
H
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C data I/O.
26
23
P50/SI0
E
General-purpose CMOS I/O port.
The pin is shared with SIO data input.
27
24
P51/SO0
F
General-purpose CMOS I/O port.
The pin is shared with SIO data output.
28
25
P52/SCK0
E
General-purpose CMOS I/O port.
The pin is shared with SIO clock I/O.
57
54
P53/COM2
F/I
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
58
55
P54/COM3
F/I
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
75 to 82 72 to 79
P60/SEG16
to
P67/SEG23
F/I
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
83 to 90 80 to 87
P70/SEG24
to
P77/SEG31
F/I
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
91
88
P80/SI1
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data input.
92
89
P81/SO1
F
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data output.
93
90
P82/SCK1
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO clock I/O.
SEG0 to
SEG15
I
LCD segment output-only pin.
59 to 74 56 to 71
55, 56
52, 53
COM0,
COM1
I
LCD common output-only pin.
54, 53,
52
51, 50,
49
V1 to V3

LCD driving power supply pin.
1, 51
98, 48
VCC

Power supply pin.
50, 100
47, 97
VSS

Power supply pin (GND) .
30
27
AVCC

A/D converter power supply pin.
29
26
AVR

A/D converter reference voltage input pin.
31
28
AVSS

A/D converter power supply pin.
Use at the same voltage level as VSS.
*1 : MQP-100C-P01
*2 : FPT-100P-M06
*3 : FPT-100P-M05
10
Pin name
MB89490 Series
• External EPROM Socket (MB89PV490 only)
Pin number
Pin name
I/O
MQFP*
Function
102
131
130
103
127
124
128
129
104
105
106
107
108
109
110
111
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins.
122
121
120
119
118
115
114
113
O8
O7
O6
O5
O4
O3
O2
O1
I
Data input pins.
101
112
117
126
N.C.

Internally connected pins. Always leave open.
116
VSS
O
Power supply pin (GND) .
123
CE
O
Chip enable pin for the EPROM. Outputs “H” in standby mode.
125
OE
O
Output enable pin for the EPROM. Always outputs “L”.
132
VCC
O
Power supply pin for the EPROM.
* : MQP-100C-P01
11
MB89490 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Main/Sub-clock circuit
X1 (X1A)
N-ch P-ch
A
P-ch
X0 (X0A)
N-ch
N-ch
Stop mode control signal
B
• Hysteresis input
(CMOS input in MB89F499)
• The pull-down resistor
(not available in MB89F499)
Approx. 50 kΩ
R
• The pull-up resistor (P-channel)
Approx. 50 kΩ
• Hysteresis input
R
P-ch
C
N-ch
pull-up
resistor register
R
P-ch
P-ch
•
•
•
•
CMOS output
IOH = − 4 mA, IOL = 12 mA
CMOS input
Selectable pull-up resistor
Approx. 50 kΩ
•
•
•
•
•
CMOS output
IOH = − 2 mA, IOL = 4 mA
CMOS port input
Hysteresis resource input
Selectable pull-up resistor
Approx. 50 kΩ
D
N-ch
port
pull-up
resistor register
R
P-ch
E
P-ch
N-ch
port
resource
(Continued)
12
MB89490 Series
(Continued)
Type
Circuit
pull-up
resistor register
R
P-ch
Remarks
P-ch
•
•
•
•
CMOS output
IOH = − 2 mA, IOL = 4 mA
CMOS input
Selectable pull-up resistor
Approx. 50 kΩ
•
•
•
•
•
•
CMOS output
IOH = − 2 mA, IOL = 4 mA
CMOS port input
VIH = 0.85 VCC, VIL = 0.5 VCC resource input
Analog input
Selectable pull-up resistor
Approx. 50 kΩ
•
•
•
•
•
N-ch open-drain output
IOL = 15 mA
CMOS port input
CMOS resource input
5 V tolerance
F
N-ch
port
pull-up
resistor register
R
P-ch
G
P-ch
N-ch
port
resource
analog
H
N-ch
port/resource
• LCD segment output
P-ch
N-ch
I
P-ch
N-ch
• CMOS input
J
13
MB89490 Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Stabilization
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. As stabilization guidelines, it is recommended
to control voltage fluctuation so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC
value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms
at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
14
MB89490 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the internal CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
•
•
•
•
•
•
•
•
60K bytes × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
Automatic algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
Includes an erase pause and erase restart function
Data polling and toggle bit for detection of program/erase completion
Detection of program/erase completion via CPU interrupt
Compatible with JEDEC-standard commands
Sector Protection (sectors can be combined in any combination)
No. of program/erase cycles : 10,000 (Min)
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase data to the flash memory, the program must first be copied from flash memory to RAM so that programming
can be performed without program access from flash memory.
4. Flash Memory Register
• Flash memory control status register (FMCS)
Address
007AH
Bit 7
Bit 6
Bit 5
Bit 4
INTE
RDYINT
WE
RDY
R/W
R/W
R/W
R
Bit 3
Bit 2
Reserved Reserved
R/W
R/W
Bit 1
Bit 0

Reserved

R/W
Initial value
000X00-0B
15
MB89490 Series
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector during
CPU access and a flash memory programming.
• Sector configuration of flash memory
Flash Memory
CPU Address
Programmer Address*
16 K bytes
FFFFH to C000H
1FFFFH to 1C000H
8 K bytes
BFFFH to A000H
1BFFFH to 1A000H
8 K bytes
9FFFH to 8000H
19FFFH to 18000H
28 K bytes
7FFFH to 1000H
17FFFH to 11000H
* : The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Applicable adapter model
Recommended writer
Sunhayato Corp.
Ando Electric Co. Ltd.
FPT-100P-M06
FLASH-100QF-32DP-8LF2
FPT-100P-M05
FLASH-100SQF-32DP-8LF
AF9708 (ver 1.60 or later) *
AF9709 (ver 1.60 or later) *
Package
* : For the programmer and the version of the programmer,contact the Flash Support Group, Inc.
Inquirues : Sunhayato Corp. : TEL : 81-(3)-3984-7791
FAX : 81-(3)-3971-0535
E-mail : [email protected]
Flash Support Group, Inc. : FAX : 81-(53)-428-8377
E-mail : [email protected]
16
MB89490 Series
■ PROGRAMMING TO THE EPROM WITH PIGGY-BACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sunhayato
Corp.) .
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry : Sunhayato Corp. : TEL : 81-3-3984-7791
FAX : 81-3-3971-0535
E-mail : [email protected]
3. Memory Space
Memory space corresponding to EPROM writer is shown in the diagram below.
Address Normal operating mode
Corresponding addresses
on the EPROM programmer
0000H
I/O
0080H
RAM
0880H
Not available
1000H
1000H
PROM
60 KB
EPROM
60 KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 1000H to FFFFH.
(3) Program to 1000H to FFFFH with the EPROM programmer.
■ ICE PROBE POD ADAPTOR OF PIGGY-BACK/EVA CHIP
The following conversion adapter is required to achieve the same pin layout as the FPT-100P-M05.
Adaptor part number: 100QF-100SQF-8L
Inquiry : Sunhayato Corp. : TEL
: 81-3-3984-7791
FAX
: 81-3-3971-0535
E-mail : [email protected]
17
MB89490 Series
■ BLOCK DIAGRAM
X0
X1
Main clock
oscillator circuit
21-bit timebase
timer
AVCC
AVSS
AVR
Clock controller
Sub-clock
oscillator circuit
RST
Reset circuit
(Watchdog timer)
CMOS I/O port
8/16-bit
timer/counter 10, 11
8
Port1
8 External interrupt 0
(edge)
UART/SIO
P52/SCK0
P51/SO0
P50/SI0
CMOS I/O port
LCD controller/driver
32 × 4-bit display
RAM (16 bytes)
3
16
ROM 48 K bytes/FLASH 60 K bytes
Other pins
VCC × 2, VSS × 2, MOD0
* : High current I/O port.
CMOS I/O port
Port6, 7
F2MC-8L
CPU
18
2 P54/COM3,
P53/COM2
16 SEG0
to SEG15
2 COM0,
COM1
8
RAM (2 K bytes)
P82/SCK1
P81/SO1
P80/SI1
SIO
2
CMOS I/O port
P45 to P40
P84
P83
CMOS I/O port
CMOS I/O port
Port0*
6
N-ch open-drain I/O port
Port8
8/16-bit
timer/counter 00, 01
P22/EC0
P20/TO0
P25/EC1
P24/TO1
P47/SDA
P46/SCL
Port5
Remote receiver circuit
Internal data bus
Port2
8-bit PWM timer 1
P21/RMC
P07 to P00
I2C
8-bit PWM timer 0
P27/PWM1
Port4*
CMOS I/O port
P26/PWM0
P17/INT07 to
P10/INT00
P37/AN7/INT17
8 to
P30/AN0/INT10
8
External interrupt 1
(level)
Watch prescaler
P23
8
10-bit
A/D converter
Port3
X0A
X1A
V1 to V3
8 P67/SEG23
to P60/SEG16
8 P77/SEG31
to P70/SEG24
MB89490 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64K bytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt/reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89490 series is structured as illustrated below.
Memory Space
MB89498
0000H
MB89F499
0000H
I/O
0080H
RAM
0200H
0880H
0000H
I/O
0080H
0100H
I/O
0080H
RAM
0100H
Generalpurpose
registers
MB89PV490
0200H
0880H
1000H
RAM
0100H
Generalpurpose
registers
Vacant
0200H
0880H
1000H
Generalpurpose
registers
Vacant
Vacant
FLASH
(60 K)
External
ROM
(60 K)
4000H
FFC0H
FFFFH
ROM
FFC0H
FFFFH
FFC0H
FFFFH
Vector table (reset, interrupt, vector call instruction)
19
MB89490 Series
2. Registers
The F2MC-8L family has 2 types of registers; dedicated registers in the CPU and general-purpose registers in
the memory. The following registers are provided :
Program counter (PC)
: A 16-bit register for indicating instruction storage positions.
Accumulator (A)
: A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register for performing arithmetic operations with the accumulator.
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX)
: A 16-bit register for index modification.
Extra pointer (EP)
: A 16-bit pointer for indicating a memory address.
Stack pointer (SP)
: A 16-bit register for indicating a stack area.
Program status (PS)
: A 16-bit register for storing a register pointer and condition code.
Initial value
16-bit
: Program counter
PC
FFFDH
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8-bit for use as a register bank pointer (RP) and the lower 8-bit for
use as a condition code register (CCR) . (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
10
9
8
Va- Va- Vacancy cancy cancy
RP
RP
20
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Conversion rule for Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
Generated addresses
b1
b0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for controlling the CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag : Interrupt is allowed when this flag is set to “1”. Interrupt is prohibited when the flag is set to “0”. Clear to
“0” at reset.
IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request is higher
than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
N-flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Clear to “0” otherwise.
Z-flag : Set to “1” when an arithmetic operation results in “0”. Clear to “0” otherwise.
V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Clear to “0” if the
overflow does not occur.
C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to “0”
otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB89490 Series
The following general-purpose registers are provided :
General-purpose registers : An 8-bit register for storing data
The general-purpose registers are 8-bit and located in the register banks of the memory.
1 bank contains 8 registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently
in use is indicated by the register bank pointer (RP) .
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
22
MB89490 Series
■ I/O MAP
Address
Register name
Register description
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 direction register
04H
PDR2
Port 2 data register
05H
Read/Write
Initial value
R/W
XXXXXXXXB
W*
00000000B
R/W
XXXXXXXXB
W*
00000000B
R/W
00000000B
(Reserved)
06H
DDR2
Port 2 direction register
R/W
00000000B
07H
SYCC
System clock control register
R/W
X-1MM100B
08H
STBC
Standby control register
R/W
00010XXXB
09H
WDTC
Watchdog timer control register
W*
0---XXXXB
0AH
TBTC
Timebase timer control register
R/W
00---000B
0BH
WPCR
Watch prescaler control register
R/W
00--0000B
0CH
PDR3
Port 3 data register
R/W
XXXXXXXXB
0DH
DDR3
Port 3 direction register
R/W
11111111B
0EH
RSFR
Reset flag register
R
XXXX----B
0FH
PDR4
Port 4 data register
R/W
11111111B
10H
PDR5
Port 5 data register
R/W
---XXXXXB
11H
DDR5
Port 5 direction register
R/W
---00000B
12H
PDR6
Port 6 data register
R/W
XXXXXXXXB
13H
DDR6
Port 6 direction register
R/W
00000000B
14H
PDR7
Port 7 data register
R/W
XXXXXXXXB
15H
DDR7
Port 7 direction register
R/W
00000000B
16H
PDR8
Port 8 data register
R/W
---XXXXXB
17H
DDR8
Port 8 direction register
R/W
---00000B
18H
EIC0
External interrupt 0 control register 0
R/W
00000000B
19H
EIC1
External interrupt 0 control register 1
R/W
00000000B
1AH
EIC2
External interrupt 0 control register 2
R/W
00000000B
1BH
EIC3
External interrupt 0 control register 3
R/W
00000000B
1CH
EIE1
External interrupt 1 enable register
R/W
00000000B
1DH
EIF1
External interrupt 1 flag register
R/W
-------0B
1EH
SMR
Serial mode register
R/W
00000000B
1FH
SDR
Serial data register
R/W
XXXXXXXXB
20H
T01CR
Timer 01 control register
R/W
000000X0B
21H
T00CR
Timer 00 control register
R/W
000000X0B
22H
T01DR
Timer 01 data register
R/W
XXXXXXXXB
(Continued)
23
MB89490 Series
Address
Register name
23H
T00DR
24H
Read/Write
Initial value
Timer 00 data register
R/W
XXXXXXXXB
T11CR
Timer 11 control register
R/W
000000X0B
25H
T10CR
Timer 10 control register
R/W
000000X0B
26H
T11DR
Timer 11 data register
R/W
XXXXXXXXB
27H
T10DR
Timer 10 data register
R/W
XXXXXXXXB
28H
ADER
A/D input enable register
R/W
11111111B
29H
ADC0
A/D control register 0
R/W
-00000X0B
2AH
ADC1
A/D control register 1
R/W
-0000001B
2BH
ADDH
A/D data register (Upper byte)
R
------XXB
2CH
ADDL
A/D data register (Lower byte)
R
XXXXXXXXB
2DH
CNTR0
PWM 0 timer control register
R/W
0-000000B
2EH
COMR0
PWM 0 timer compare register
W*
XXXXXXXXB
2FH
SMC0
UART/SIO serial mode control register
R/W
00000000B
30H
SMC1
UART/SIO serial mode control register
R/W
00000000B
31H
SSD
UART/SIO serial status/data register
R/W
00001---B
32H
SIDR/SODR
UART/SIO serial data register
R/W
XXXXXXXXB
33H
SRC
UART/SIO serial rate control register
R/W
XXXXXXXXB
34H
CNTR1
PWM 1 timer control register
R/W
0-000000B
35H
COMR1
PWM 1 timer compare register
36H
IBSR
Register description
W*
XXXXXXXXB
2
R
00000000B
2
I C bus status register
37H
IBCR
I C bus control register
R/W
00000000B
38H
ICCR
I2C clock control register
R/W
000XXXXXB
39H
IADR
I2C address register
R/W
-XXXXXXXB
I C data register
R/W
XXXXXXXXB
Sub PLL control register
R/W
----0000B
3AH
IDAR
3BH
PLLCR
3CH to 3FH
2
(Reserved)
40H
RMN
Remote control counter register
R
XXXXXXXXB
41H
RMC
Remote control control register
R/W
00000000B
42H
RMS
Remote control status register
R/W
0X000001B
43H
RMD
Remote control FIFO data register
R
X----XXXB
44H
RMCD0
Remote control compare register 0
R/W
11111111B
45H
RMCD1
Remote control compare register 1
R/W
11111111B
46H
RMCD2
Remote control compare register 2
R/W
11111111B
47H
RMCD3
Remote control compare register 3
R/W
11111111B
48H
RMCD4
Remote control compare register 4
R/W
11111111B
(Continued)
24
MB89490 Series
(Continued)
Address
Register name
49H
RMCD5
4AH
RMCI
Register description
Read/Write
Initial value
Remote control compare register 5
R/W
11111111B
Remote interrupt register
R/W
0000-000B
LCD controller output control register
R/W
-0000000B
LCD controller control register
R/W
00010000B
4BH to 5DH
(Reserved)
5EH
LOCR
5FH
LCR
60H to 6FH
VRAM
LCD data RAM
R/W
XXXXXXXXB
70H
PUCR0
Port 0 pull up resistor control register
R/W
11111111B
71H
PUCR1
Port 1 pull up resistor control register
R/W
11111111B
72H
PUCR2
Port 2 pull up resistor control register
R/W
11111111B
73H
PUCR3
Port 3 pull up resistor control register
R/W
11111111B
74H
PUCR5
Port 5 pull up resistor control register
R/W
---11111B
75H
PUCR6
Port 6 pull up resistor control register
R/W
11111111B
76H
PUCR7
Port 7 pull up resistor control register
R/W
11111111B
77H
PUCR8
Port 8 pull up resistor control register
R/W
-----111B
R/W
000X00-0B
78H to 79H
(Reserved)
7AH
FMCS
7BH
ILR1
Interrupt level setting register 1
W*
11111111B
7CH
ILR2
Interrupt level setting register 2
W*
11111111B
7DH
ILR3
Interrupt level setting register 3
W*
11111111B
7EH
ILR4
Interrupt level setting register 4
W*
11111111B
Flash memory control status registger
7FH
(Reserved)
* : Bit manipulation instruction cannot be used.
• Read/write access symbols
R/W : Readable and writable
R:
Read-only
W : Write-only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
- : Unused bit.
M : The initial value of this bit is determined by mask option.
25
MB89490 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
AVCC
VSS − 0.3
VSS + 4.0
V
AVR
VSS − 0.3
VSS + 4.0
V
V1 to V3
VSS − 0.3
VCC
V
VSS − 0.3
VCC + 0.3
V
Except P40 to P47
VSS − 0.3
VSS + 6.0
V
P40 to P47 in MB89PV490 and
MB89498
VSS − 0.3
VSS + 5.5
V
P40 to P47 in MB89F499
VSS − 0.3
VCC + 0.3
V
− 2.0
+ 2.0
mA
*2

20
mA
*2
“L” level maximum output current IOL

15
mA
“L” level average output current
IOLAV

4
mA
“L” level total maximum output
current
ΣIOL

100
mA
“L” level total average output
current
ΣIOLAV

40
mA
“H” level maximum output current IOH

− 15
mA
“H” level average output current
IOHAV

−4
mA
“H” level total maximum output
current
ΣIOH

− 50
mA
“H” level total average output
current
ΣIOHAV

− 20
mA
Power consumption
PD

300
mW
Operating temperature
TA
− 40
+ 85
°C
Storage temperature
Tstg
− 55
+ 150
°C
Power supply voltage*1
LCD power supply voltage
Input voltage *1
Output voltage*
VI
1
VO
Maximum clamp current
ICLAMP
Total maximum clamp current
Σ|ICLAMP|
AVCC must be equal to VCC
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : •
•
•
•
Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P52, P80 to P82
Use within recommended operating conditions.
Use at DC voltage (current) .
The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
(Continued)
26
MB89490 Series
(Continued)
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Symbol
Parameter
Value
Unit
Remarks
Min
Max
2.7*
3.6
V
Normal operation
assurance range
MB89PV490 and
MB89F499
2.2*
3.6
V
Normal operation
assurance range
MB89498
1.5
3.6
V
Retains the RAM state in stop mode
AVR
2.7
3.6
V
LCD power supply voltage
V1 to V3
Vss
Vcc
V
Operating temperature
TA
−40
+85
°C
VCC
AVCC
Power supply voltage
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and
“5. A/D Converter Electrical Characteristics.”
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Operating
voltage (V)
3.6
Analog accuracy
assurance range :
VCC = AVCC = 2.7 V to 3.6 V
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
10.0 11.0 12.0 12.5
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89F499
Figure1 Operating Voltage vs. Main Clock Operating Frequency (MB89F499/498)
28
MB89490 Series
Operating
voltage (V)
3.6
3.5
Analog accuracy
assurance range :
VCC = AVCC = 2.7 V to 3.6 V
3.0
2.7
Main clock
operating freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
10.0 11.0 12.0 12.5
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Figure2 Operating Voltage vs. Main Clock Operating Frequency (MB89PV490)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see figure 1 and 2 if the operating speed
is switched using a gear.
29
MB89490 Series
3. DC Characteristics
Parameter Symbol
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Pin
Value
Unit
Remarks
Min
Typ
Max

0.7 VCC

VCC + 0.3
V

0.7 VCC

VSS + 6.0
V
MB89498

0.7 VCC

VSS + 5.5
V
MB89F499
VIHS
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 to INT07

0.8 VCC

VCC + 0.3
V
VIHA
INT10 to INT17

0.85 VCC

VCC + 0.3
V
VIL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84,
SCL, SDA,

VSS − 0.3

0.3 VCC
V
VILS
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 to INT07

VSS − 0.3

0.2 VCC
V
VILA
INT10 to INT17

VSS − 0.3

0.5 VCC
V

VSS − 0.3

VSS + 6.0
V
MB89498

VSS − 0.3

VSS + 5.5
V
MB89F499
VIH
“H” level
input voltage
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84,
SCL, SDA,
P40 to P47
“L” level
input voltage
Open-drain
output pin
application
voltage
Condition
VD
P40 to P47
(Continued)
30
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
“H” level
VOH
output voltage
“L” level
VOL
output voltage
Pin
Condition
Value
Min
Typ
Max
Unit
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P82
IOH = −2.0 mA
2.2


V
P00 to P07
IOH = −4.0 mA
2.2


V


0.4
V
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
IOL = 4.0 mA
P60 to P67,
P70 to P77,
P80 to P82, RST
Remarks
P00 to P07
IOL = 12.0 mA


0.4
V
P40 to P47
IOL = 15.0 mA


0.4
V
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P84
0.45 V < VI < VCC
−5

+5
µA
Open-drain
output leakage ILOD
current
P40 to P47
0.0 V < VI < VCC
−5

+5
µA
Pull-down
resistance
RDOWN
MOD0
VI = VCC
25
50
100
kΩ
Except
MB89F499
Pull-up
resistance
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P54,
P60 to P67,
P70 to P77,
P80 to P82,
RST
VI = 0.0 V
25
50
100
kΩ
When pull-up
resistor is
selected
(except RST)
Common
output
impedance
RVCOM
COM0 to COM3
V1 to V3 = +3.0 V


2.5
kΩ
Input leakage
current
ILI
Without
pull-up
resistor
(Continued)
31
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Typ
Max


15
kΩ
300
500
750
kΩ

−1

+1
µA
FCH = 12.5 MHz
tinst = 0.33 µs
Main clock run mode

8.0
12
mA MB89F499
ICC1

7.0
12.0
mA MB89498
ICC2
FCH = 12.5 MHz
tinst = 5.33 µs
Main clock run mode

1.0
3.0
mA
MB89F499
MB89498
ICCS1
FCH = 12.5 MHz
tinst = 0.33 µs
Main clock sleep
mode

3.0
5.0
mA
MB89F499
MB89498
ICCS2
FCH = 12.5 MHz
tinst = 5.33 µs
Main clock sleep
mode

0.6
2.0
mA
MB89F499
MB89498
FCL = 32.768 kHz
Sub-clock mode
TA = +25 °C

40.0
60.0
µA
MB89F499
MB89498
ICCLPLL
FCL = 32.768 kHz
Sub-clock mode
TA = +25 °C
sub PLL × 4

180.0
250.0
µA
MB89F499
MB89498
ICCLS
FCL = 32.768 kHz
Sub-clock sleep
mode
TA = +25 °C

14.0
30.0
µA
MB89F499
MB89498
ICCT
FCL = 32.768 kHz
Watch mode
Main clock stop
mode
TA = +25 °C

1.5
13.0
µA
MB89F499
MB89498
Segment
output
impedance
RVSEG
LCD divided
resistance
RLCD

LCD
controller/
driver
leakage
current
ILCDL
V1 to V3,
COM0 to COM3,
SEG0 to SEG31
Power supply
current
ICCL
SEG0 to SEG31 V1 to V3 = +3.0 V
VCC
Between VCC and
VSS
(Continued)
32
MB89490 Series
(Continued)
Parameter
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
ICCH
Power supply
IA
current
IAH
Input
capacitance
CIN
Pin
VCC
AVCC
Condition
Value
Unit
Remarks
Min
Typ
Max
TA = +25 °C
Sub-clock stop mode

0.8
4.0
µA
MB89F499
MB89498
AVCC = 3.0 V,
TA = +25 °C

1.2
4.4
mA
A/D
converting
TA = +25 °C

0.8
4.0
µA A/D stop

10.0

pF
Except
VCC, VSS, AVCC, f = 1 MHz
AVSS, AVR
33
MB89490 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Parameter
RST “L” pulse width
Value
Condition

tZLZH
Min
Max
48 tHCYL

Unit
Remarks
ns
Note : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
The MCU operation is not guaranteed when the “L” pulse width is shorter than tZLZH.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition

Value
Unit
Min
Max

50
ms
1

ms
Remarks
Due to repeated operations
Note : Make sure that power supply rises within the selected oscillation stabilization time.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
1.5 V
VCC
34
0.2 V
0.2 V
0.2 V
MB89490 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Value
Pin
Min
Typ
Max
Unit
FCH
X0, X1
1

12.5
MHz
FCL
X0A, X1A

32.768
75
kHz
tHCYL
X0, X1
80

1000
ns
tLCYL
X0A, X1A
13.3
30.5

µs
PWH
PWL
X0
20


ns
PWHL
PWLL
X0A

15.2

µs
tCR
tCF
X0, X0A


10
ns
Remarks
External clock
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X0
X1
X1
open
FCH
C1
C2
FCH
35
MB89490 Series
Sub-clock Timing and Conditions
tLCYL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCR
tCF
Sub-clock Conditions
When a crystal
or
ceramic resonator is used
X0A
X0A
X1A
FCL
When an external clock is used
X1A
Rd
FCL
C0
When an subclock is not used
X0A
X1A
Open
Open
C1
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
36
Symbol
Value (typical)
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 0.32 µs when operating
at FCH = 12.5 MHz
2/FCL, 1/2FCL
µs
(2/FCL) tinst = 61.036 µs when
operating at FCL = 32.768 kHz
tinst
MB89490 Series
• PLL operation guarantee range (sub PLL × 4)
Relationship between internal operating clock frequency and power supply voltage
Operating
voltage (V)
subPLL operating guarantee range
3.6
3.0
2.7
2.5
2.0
Internal operating clock freq. (kHz)
131.072
300
15.625
6.67
Min execution
time (inst. cycle) (µs)
Not assured for MB89F499 and MB89PV490.
Instruction cycle, tinst (min. exec. time)
(µs)
Relationship between sub-clock oscillating frequency and instruction cycle when
sub PLL is enabled
15.625
Multiplied
by 4
6.67
75
32.768
Oscillation clock FCL (kHz)
37
MB89490 Series
(5) Serial I/O Timing
Parameter
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin
Condition
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SO time
tSLOV
SCK0, SCK1, SO0, SO1
Valid SI → SCK ↑
tIVSH
SI0, SI1, SCK0, SCK1
SCK ↑ → valid SI hold time
tSHIX
SCK0, SCK1, SI0, SI1
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO time
tSLOV
SCK0, SCK1, SO0, SO1
Valid SI → SCK ↑
tIVSH
SI0, SI1, SCK0, SCK1
SCK ↑ → valid SI hold time
tSHIX
SCK0, SCK1, SI0, SI1
Internal
shift clock
mode
SCK0, SCK1
External
shift clock
mode
Value
Max
2 tinst*

µs
−200
200
ns
1/2 tinst*

µs
1/2 tinst*

µs
1 tinst*

µs
1 tinst*

µs
0
200
ns
1/2 tinst*

µs
1/2 tinst*

µs
* : For information on tinst, see “ (4) Instruction Cycle.”
Internal Clock Operation
tSCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
SI0, SI1
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Clock Operation
tSLSH
tSHSL
SCK0, SCK1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
SI0, SI1
38
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Unit
Min
MB89490 Series
(6) I2C Timing
Parameter
(VCC = 3.0V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin
Value
Min
Max
Unit
Remarks
Start condition output
tSTA
SCL
SDA
1/4 tinst*1 ×
M × N − 20
1/4 tinst ×
M × N + 20
ns
At master mode
Stop condition output
tSTO
SCL
SDA
1/4 tinst ×
(M × N + 8) − 20
1/4 tinst ×
(M*2 × N*3 + 8) + 20
ns
At master mode
Start condition detect
tSTA
SCL
SDA
1/4 tinst × 6 + 40

ns
Stop condition detect
tSTO
SCL
SDA
1/4 tinst × 6 + 40

ns
Re-start condition
output
tSTASU
SCL
SDA
1/4 tinst ×
(M × N + 8) − 20
1/4 tinst ×
(M × N + 8) + 20
ns
Re-start condition
detect
tSTASU
SCL
SDA
1/4 tinst × 4 + 40

ns
SCL output LOW width
tLOW
SCL
1/4 tinst ×
M × N − 20
1/4 tinst ×
M × N + 20
ns
At master mode
SCL output HIGH width
tHIGH
SCL
1/4 tinst ×
(M × N + 8) − 20
1/4 tinst ×
(M × N + 8) + 20
ns
At master mode
SDA output delay
tDO
SDA
1/4 tinst × 4 − 20
1/4 tinst × 4 + 20
ns
SDA output setup
time after interrupt
tDOSU
SDA
1/4 tinst × 4 − 20

ns
SCL input LOW
pulse width
tLOW
SCL
1/4 tinst × 6 + 40

ns
SCL input HIGH
pulse width
tHIGH
SCL
1/4 tinst × 2 + 40

ns
SDA input setup time
tSU
SDA
40

ns
SDA hold time
tHO
SDA
0

ns
At master mode
*4
*1 : For information in tinst, see “ (4) Instruction Cycle”.
*2 : M is defined in the I2C clock control register ICCR bit 4 and bit 3 (CS4 and CS3). For details, please refer to
the H/W manual register explanation.
*3 : N is defined in the I2C clock control register ICCR bit 2 to bit 0 (CS2 to CS0).
*4 : When the interrupt period is greater than SCL “L” width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
39
MB89490 Series
Data transmit (master/slave)
tDO
tSU
tDO
SDA
tHO
tDOSU
ACK
tSTASU
tSTA
tLOW
tHO
1
SCL
9
Data receive (master/slave)
tHO
tSU
tDO
SDA
40
tDOSU
ACK
tHIGH
SCL
tDO
6
7
tLOW
tSTO
8
9
MB89490 Series
(7) Peripheral Input Timing
Parameter
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Value
Pin
EC0, EC1, INT00 to
INT07, INT10 to INT17
Unit
Min
Max
2 tinst*

µs
2 tinst*

µs
Remarks
* : For information on tinst, see “ (4) Instruction Cycle.”
tIHIL1
EC0, EC1,
INT00 to INT07
tILIH1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIHIL1
tILIH1
INT10 to INT17
0.85 VCC
0.5 VCC
0.85 VCC
0.5 VCC
41
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 3.6 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
Resolution
Total error
Linearity error

Differential linearity error

Value
Typ
Max

10

bit


±3.0
LSB


±2.5
LSB


±1.9
LSB
Remarks
Zero transition voltage
VOT
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
mV
Full-scale transition
voltage
VFST
AVCC −
3.5 LSB
AVCC −
1.5 LSB
AVCC −
0.5 LSB
mV
A/D mode conversion time

30 tinst*


µs
Analog port input current
IAIN


10
µA
Analog input voltage
VAIN
AVSS

AVR
V
AVSS + 2.7

AVCC
V

95.0
170.0
µA
A/D is
activated


4.0
µA
A/D is
stopped
Reference voltage
Reference voltage supply
current
AN0 to
AN7

IR
IRH
AVR
* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics”.
42
Unit
Min
MB89490 Series
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics.
• Differential linearity error (unit : LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
• Total error (unit : LSB)
The difference between theoretical and actual conversion values.
Total error
Theoretical I/O characteristics
3FFH
3FFH
VFST
3FEH
3FEH
3FDH
1.5 LSB
Digital output
Digital output
3FDH
004H
003H
VOT
002H
Actual conversion
characteristics
{1 LSB × N + VOT}
004H
VNT
003H
Actual conversion
characteristics
002H
1 LSB
Ideal characteristics
001H
001H
0.5 LSB
AVCC
AVSS
Analog input
1 LSB =
VFST − VOT
1022
Analog input
Total error = VNT − {1 LSB × N + 0.5 LSB}
1 LSB
(V)
Full-scale transition error
Zero transition error
004H
Theoretical characteristics
Actual conversion
characteristics
3FFH
Actual conversion
characteristics
Digital output
003H
Digital output
AVCC
AVSS
002H
Actual conversion
characteristics
3FEH
VFST
(Actual
measurement
value)
3FDH
001H
Actual conversion
characteristics
VOT (Actual measurement
value)
3FCH
AVCC
AVSS
Analog input
Analog input
(Continued)
43
MB89490 Series
(Continued)
Differential linearity error
Linearity error
3FFH
Ideal value
Actual conversion
characteristics
3FEH
N+1
{1 LSB × N + VOT}
Actual conversion
characteristics
VFST
(Actual
VNT measurement
value)
004H
003H
Digital output
Digital output
3FDH
N
N–1
VNT
Actual conversion
characteristics
002H
Actual conversion
characteristics
Ideal value
001H
V(N + 1)T
N–2
VOT (Actual measurement value)
AVSS
AVCC
Analog input
Linearity error =
44
VNT − {1 LSB × N + VOT}
1 LSB
AVSS
AVCC
Analog input
Differential linearity error =
V(N + 1)T − VNT
1 LSB
−1
MB89490 Series
(3) Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
MB89498
MB89F499
Note : The values are reference values.
R
2.4 kΩ (Max)
2.4 kΩ (Max)
C
44.0 pF (Max)
28.6 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB89498
MB89F499
20
90
18
External impedance [kΩ]
External impedance [kΩ]
MB89F499
100
80
70
60
50
40
30
20
10
0
MB89498
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
Minimum sampling time [µs]
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
45
MB89490 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” level output voltage
VOL vs IOL (MB89F499)
VOL vs IOL (MB89498)
VCC = 2.0 V VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.30
0.25
TA = + 25˚C
TA = + 25˚C
VCC = 2.0 V
0.25
VOL [V]
0.15
0.20
VOL [V]
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.20
0.15
0.10
0.10
0.05
0.05
0.00
0.00
0
2
4
6
8
0
10
2
Port 0
IOL [mA]
4
6
8
VOL vs IOL (MB89498)
10
Port 0
IOL [mA]
VOL vs IOL (MB89F499)
0.20
0.20
TA = + 25˚C
TA = + 25˚C
0.16
0.16
VCC = 2.0 V
0.12
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
VOL [V]
0.12
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.08
0.02
VOL [V]
VCC = 2.0 V
0.08
0.04
0.00
0.00
0
2
4
6
IOL [mA]
8
10
Port 4
0
2
4
6
IOL [mA]
8
10
Port 4
(Continued)
46
MB89490 Series
(Continued)
VOL vs IOL (MB89F499)
VOL vs IOL (MB89498)
TA = + 25˚C
VCC = 2.0 V
TA = + 25˚C
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.6
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.4
VOL [V]
0.6
VOL [V]
VCC = 2.0 V
0.8
0.8
0.4
0.2
0.2
0.0
0.0
0
2
4
6
8
0
10
2
4
6
8
10
IOL [mA] Other than port 0, port 4
IOL [mA] Other than port 0, port 4
(2) “H” level output voltage
VCC − VOH vs IOH (MB89F499)
VCC - VOH vs IOH (MB89498)
0.7
TA = + 25˚C
VCC = 2.0 V
1.0
VCC = 2.0 V
TA = + 25˚C
0.6
VCC - VOH [V]
0.5
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.4
0.3
VCC - VOH [V]
0.8
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.6
0.4
0.2
0.2
0.1
0.0
0.0
0
−2
−4
−6
IOH [mA]
−8
−10
Port 0
0
−2
−4
−6
IOH [mA]
−8
−10
Port 0
(Continued)
47
MB89490 Series
(Continued)
VCC - VOH vs IOH (MB89F499)
VCC - VOH vs IOH (MB89498)
VCC = 2.0 V
1.4
VCC = 2.0 V VCC = 2.5 V VCC = 2.7 V
1.4
TA = + 25˚C
VCC = 3.0 V
TA = + 25˚C
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
1.2
1.2
VCC = 2.5 V
1.0
VCC - VOH [V]
VCC = 2.7 V
0.8
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4.0 V
0.6
VCC - VOH [V]
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
−2
0
−4
−6
IOH [mA]
−8
−10
−2
0
−4
−6
IOH [mA]
Other than port 0
−8
−10
Other than port 0
(3) Power supply current (External clock)
ICC1 vs VCC (MB89F499)
ICC1 vs VCC (MB89498)
12.0
10.0
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
10.0
8.0
FCH = 10.0 MHz
FCH = 10.0 MHz
ICC1 [mA]
6.0
FCH = 8.0 MHz
4.0
ICC1 [mA]
8.0
FCH = 8.0 MHz
6.0
4.0
FCH = 4.0 MHz
FCH = 4.0 MHz
2.0
FCH = 2.0 MHz
2.0
FCH = 2.0 MHz
FCH = 1.0 MHz
FCH = 1.0 MHz
0.0
0.0
1
2
3
VCC [V]
4
5
1
2
3
4
5
VCC [V]
(Continued)
48
MB89490 Series
ICCS1 vs VCC (MB89F499)
ICCS1 vs VCC (MB89498)
4.5
4.0
4.0
FCH = 12.5 MHz
3.5
3.5
2.0
ICCS1 [mA]
ICCS1 [mA]
FCH = 8.0 MHz
2.5
1.5
2.5
FCH = 8.0 MHz
2.0
1.5
FCH = 4.0 MHz
FCH = 4.0 MHz
1.0
1.0
FCH = 2.0 MHz
FCH = 2.0 MHz
0.5
FCH = 10.0 MHz
3.0
FCH = 10.0 MHz
3.0
0.5
FCH = 1.0 MHz
FCH = 1.0 MHz
0.0
0.0
1
2
3
4
1
5
2
3
4
5
VCC [V]
VCC [V]
ICC2 vs VCC (MB89F499)
ICC2 vs VCC (MB89498)
1.4
1.4
TA = + 25˚C
TA = + 25˚C
1.2
FCH = 12.5 MHz
1.2
1.0
FCH = 10.0 MHz
1.0
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 8.0 MHz
0.8
ICC2 [mA]
ICC2 [mA]
FCH = 12.5 MHz
TA = + 25˚C
TA = + 25˚C
0.6
FCH = 8.0 MHz
0.8
0.6
FCH = 4.0 MHz
0.4
FCH = 4.0 MHz
0.4
FCH = 2.0 MHz
0.2
FCH = 1.0 MHz
0.0
FCH = 2.0 MHz
0.2
FCH = 1.0 MHz
0.0
1
2
3
VCC [V]
4
5
1
2
3
4
5
VCC [V]
(Continued)
49
MB89490 Series
ICCS2 vs VCC (MB89F499)
ICCS2 vs VCC (MB89498)
1.0
1.0
TA = + 25˚C
TA = + 25˚C
FCH = 12.5 MHz
FCH = 12.5 MHz
0.8
0.8
0.6
FCH = 8.0 MHz
0.4
FCH = 10.0 MHz
ICCS2 [mA]
ICCS2 [mA]
FCH = 10.0 MHz
0.6
FCH = 8.0 MHz
0.4
FCH = 4.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
0.2
FCH = 2.0 MHz
0.2
FCH = 1.0 MHz
FCH = 1.0 MHz
0.0
0.0
1
2
3
4
1
5
2
3
4
5
VCC [V]
VCC [V]
ICCLPLL vs VCC (MB89F499)
ICCLPLL vs VCC (MB89498)
0.30
0.30
TA = + 25˚C
TA = + 25˚C
0.25
0.25
FCH = 12.5 MHz
FCH = 12.5 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz
0.15
FCH = 2.0 MHz
FCH = 1.0 MHz
ICCLPLL [mA]
ICCLPLL [mA]
FCH = 10.0 MHz
0.20
0.20
FCH = 8.0 MHz
0.15
0.10
0.10
0.05
0.05
0.00
FCH = 10.0 MHz
FCH = 4.0 MHz
FCH = 2.0 MHz
FCH = 1.0 MHz
0.00
1
2
3
VCC [V]
4
5
1
2
3
4
5
VCC [V]
(Continued)
50
MB89490 Series
ICCL vs VCC (MB89F499)
ICCL vs VCC (MB89498)
60.0
60.0
TA = + 25˚C
TA = + 25˚C
50.0
50.0
FCL = 32.768 kHz
FCL = 32.768 kHz
40.0
ICCL [µA]
ICCL [µA]
40.0
30.0
30.0
20.0
20.0
10.0
10.0
0.0
0.0
1
2
3
4
1
5
2
VCC [V]
ICCLS vs VCC (MB89498)
4
5
ICCLS vs VCC (MB89F499)
20.0
20.0
TA = + 25˚C
TA = + 25˚C
16.0
16.0
FCL = 32.768 kHz
FCL = 32.768 kHz
ICCLS [µA]
ICCLS [µA]
3
VCC [V]
12.0
8.0
4.0
12.0
8.0
4.0
0.0
0.0
1
2
3
VCC [V]
4
5
1
2
3
4
5
VCC [V]
(Continued)
51
MB89490 Series
(Continued)
ICCT vs VCC (MB89498)
ICCT vs VCC (MB89F499)
2.0
2.0
TA = + 25˚C
TA = + 25˚C
1.6
1.6
FCL = 32.768 kHz
ICCT [µA]
ICCT [µA]
FCL = 32.768 kHz
1.2
0.8
0.4
1.2
0.8
0.4
0.0
0.0
1
2
3
4
5
1
2
3
VCC [V]
4
5
VCC [V]
(4) Pull-up resistance
RPULL vs VCC (MB89F499)
RPULL vs VCC (MB89498)
120
200
TA = + 25˚C
TA = + 25˚C
100
160
RPULL [kΩ]
RPULL [kΩ]
80
120
80
60
TA = + 110 ˚C
40
TA = + 110 ˚C
TA = + 25 ˚C
TA = - 40 ˚C
45
20
0
0
1.5
2.0
2.5
3.0
VCC [V]
52
TA = + 25 ˚C
TA = - 40 ˚C
3.5
4.0
4.5
2.0
2.5
3.0
3.5
VCC [V]
4.0
4.5
MB89490 Series
■ MASK OPTIONS
Part number
MB89498
MB89F499
MB89PV490
Specifying procedure
Specify when
ordering mask
Setting not possible
Main clock oscillation stabilizationtime selection
210/FCH
214/FCH
218/FCH
Selectable
Fixed to oscillation stabilization wait
time of 218/FCH
■ ORDERING INFORMATION
Part number
Package
MB89498PF
MB89F499PF
100-pin Plastic QFP
(FPT-100P-M06)
MB89498PFV
MB89F499PFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB89PV490CF
100-pin Ceramic MQFP
(MQP-100C-P01)
Remarks
53
MB89490 Series
■ PACKAGE DIMENSIONS
100-pin Ceramic MQFP
(MQP-100C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.35(.486)TYP
+0.40
1.20 –0.20
.047
0.65±0.15
(.0256±.0060)
+.016
–.008
0.65±0.15
(.0256±.0060)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30±0.08
(.012±.003)
0.30(.012)TYP
7.62(.300)TYP
18.85(.742)
TYP
0.30±0.08
(.012±.003)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
10.82(.426)
0.15±0.05 MAX
(.006±.002)
C
1994 FUJITSU LIMITED M100001SC-1-2
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
54
MB89490 Series
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
55
MB89490 Series
(Continued)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin Plastic LQFP
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
56
MB89490 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0410
 2004 FUJITSU LIMITED Printed in Japan