FUJITSU MB89PV890

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12524-4E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8L MB89890 Series
MB89898/899/P899/PV890
■ OUTLINE
The MB89890 series is a line of single-chip microcontrollers containing a great variety of peripheral functions
such as dual clock control systems, 4-stage operating speed controller, DTMF signal generator, timer, PWM timer,
serial interface, modem, A/D converter and external interrupt, as well as compact instruction set.
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
F2MC-8L family CPU core
Dual clock control system
Maximum memory size: 64 Kbytes
Minimum execution time: 0.5 µs at 8 MHz
Interrupt processing time: 4.5 µs at 8 MHz
I/O ports: Max 85 ports
21-bit time-base counter
8-bit PWM timer
DTMF generator
8/16-bit timer
8-bit serial I/O
Serial I/O with 1-byte buffer
(Continued)
■ PACKAGES
100-pin Plastic QFP
100-pin Ceramic MQFP
(FPT-100P-M06)
(MQP-100C-P01)
MB89890 Series
(Continued)
• A/D converter
• Modem timer (pulse-width counter)
• Modem signal output
• External interrupt: 16 channels
• Power-on reset function
• Low-power consumption modes (subclock mode, watch mode, sleep mode, stop mode)
• CMOS technology
■ PRODUCT LINEUP
Part number
Item
Classification
ROM size
RAM size
Instruction bit
length
MB89898
MB89899
MB89P899
MB89PV890
Mass-produced products
(mask ROM products)
One-time product
OTPROM product
Piggyback/
evaluation product
(for development)
48 K × 8 bits
60 K × 8 bits
(internal mask ROM) (internal mask ROM)
60 K × 8 bits
(internal OTPROM)
60 K × 8 bits
(external ROM)
1.5 K × 8 bits
2.0 K × 8 bits
8 bits
Instruction length
1 to 3 bytes
Data bit length
1, 8, 16 bits
The number of
instructions
136
Clock generator
Internal
Minimum
execution time
0.5 µs at 8 MHz to 8 µs at 8 MHz, 61 µs at 32.768 kHz
Interrupt
processing time
4.5 µs at 8 MHz to 72 µs at 8 MHz, 549.3 µs at 32.768 kHz
Ports
( ) indicate shared
function ports.
PWM timer
Timer/counter
Serial I/O
A/D converter
DTMF generator
Soft modem
receiving timer
General-purpose output ports (N-ch open-drain): 21 (8)
General-purpose output ports (CMOS): 8 (0)
General-purpose I/O ports (N-ch open-drain): 8 (6)
General-purpose I/O ports (CMOS): 48 (29)
Total: 85 (43)
8 bits × 1 channel
8 bits × 2 channels or 16 bits × 1 channel
8-bit serial I/O (with 1-byte buffer) × 1
8 bits × 8 channels
CCITT all-tone output capable (1 to 0(10), *, #, A to D)
Single-tone output capable
5-bit noise reduction circuit + pulse-width measurement timer
(Continued)
2
MB89890 Series
(Continued)
Part number
Item
MB89898
Soft modem
transmitting
circuit
MB89899
MB89P899
MB89PV890
approximately 1208 bps, approximately 2415 bps modem output
External interrupt
16
Time-base timer
21 bits
Watch prescaler
15 bits
Standby mode
Watch mode, subclock mode, sleep mode, stop mode
Process
CMOS
Operating
voltage*
2.2 V to 6.0 V
2.7 V to 6.0 V
EPROM for use
MBM27C512-20TV
*: Varies with conditions such as operating frequencies.
■ PACKAGE AND CORRESPONDING MODELS
Package
MB89898
MB89899
MB89P899
MB89PV890
×
FPT-100P-M06
MQP-100C-P01
: Available
×
× : Not available
Note: For more information about each package, see “■ PACKAGE DIMENSIONS”.
■ DIFFERENCES AMONG MODELS
1. Memory Size
Before evaluating using the piggyback model, verify its difference from the model that will actually be used.
2. Current Consumption
• In the case of the MB89PV890, added is the current consumed by the EPROM which is connected to the top
socket.
• When operated at low speed the product with an OTPROM (EPROM) will consume more current than the
product with a mask ROM. However, the same is current consumption in sleep/stop mode.
3. Mask Options
Functions that can be selected as options and how to designate these options vary with product. Before using
options, check “■ MASK OPTIONS”. Take particular care on the following points:
• Options are fixed on the MB89PV890.
• Pull-up resistor options on the MB89P899 are in 2-bit units for P00 to P07, P10 to P17, P60 to P67, P90 to
P97, and PA0 to PA7. Options are in 1-bit units for P40 to P44, P70 to P77, P80 to P87.
3
MB89890 Series
■ PIN ASSIGNMENTS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PA7/INT3
PA6/INT2
PA5/INT1
PA4/INT0
PA3/INTB
DTMF
AVR
(AVCC) VCC
P57/AN07
P56/AN06
P55/AN05
P54/AN04
P53/AN03
P52/AN02
P51/AN01
P50/AN00
(AVSS) VSS
PA2/INTA
PA1/INT29
PA0/INT28
(Top view)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P97/INT27
P96/INT26
P95/INT25
P94/INT24
P93/INT23
P92/INT22
P91/INT21
P90/INT20
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75/BSO2
P74/BSI2
P73/BSK2
VSS
P72/SO2
P71/SI2
P70/SK2
P67/BSO1
P66/BSI1
P65/BSK1
P64
P63/MSKO
P25
P26
P27
P40
P41
P42
P43
P44
P30/PWM
P31/BUZR
P32/MSKI
P33
P34
P35/SK1
P36/SI1
P37/SO1
P60/TMO1
P61/TMO2
P62/TCLK
VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
X1A
X0A
MOD0
MOD1
X0
X1
VSS
RST
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
(FPT-100P-M06)
(Continued)
4
MB89890 Series
(Continued)
O2
O3
VSS
N.C.
O4
O5
OE
A2
N.C.
A3
A11
A4
A9
A5
A8
A6
A7
A1
A12
A10
A15
A0
N.C.
CE
101
N.C.
VCC
O8
132
01
A14
O7
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P97/INT27
P96/INT26
P95/INT25
P94/INT24
P93/INT23
P92/INT22
P91/INT21
P90/INT20
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75/BSO2
P74/BSI2
P73/BSK2
VSS
P72/SO2
P71/SI2
P70/SK2
P67/BSO1
P66/BSI1
P65/BSK1
P64
P63/MSKO
P25
P26
P27
P40
P41
P42
P43
P44
P30/PWM
P31/BUZR
P32/MSKI
P33
P34
P35/SK1
P36/SI1
P37/SO1
P60/TMO1
P61/TMO2
P62/TCLK
VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
X1A
X0A
MOD0
MOD1
X0
X1
VSS
RST
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
O6
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PA7/INT3
PA6/INT2
PA5/INT1
PA4/INT0
PA3/INTB
DTMF
AVR
(AVCC) VCC
P57/AN07
P56/AN06
P55/AN05
P54/AN04
P53/AN03
P52/AN02
P51/AN01
P50/AN00
(AVSS) VSS
PA2/INTA
PA1/INT29
PA0/INT28
(Top view)
(MQP-100C-P01)
• Pin assignment on package top (MB89PV890 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
101
N.C.
109
A2
117
N.C.
125
OE
102
A15
110
A1
118
O4
126
N.C.
103
A12
111
A0
119
O5
127
A11
104
A7
112
N.C.
120
O6
128
A9
105
A6
113
O1
121
O7
129
A8
106
A5
114
O2
122
O8
130
A13
107
A4
115
O3
123
CE
131
A14
108
A3
116
VSS
124
A10
132
VCC
N.C.: Internally connected. Do not use.
5
MB89890 Series
■ PIN DESCRIPTION
Pin no.
QFP*1, MQP*2
Pin name
6
X0
7
X1
3
X0A
2
X1A
4
MOD0
5
MOD1
9
Circuit type
Function
A
Crystal oscillator pins (8 MHz)
B
Crystal oscillator pins (32.768 kHz)
C
Operation mode select pins
Connect to VSS (GND) when using.
RST
D
Reset input pin
10 to 17
P00 to P07
E
General-purpose I/O ports
18 to 25
P10 to P17
E
General-purpose I/O ports
26 to 33
P20 to P27
G
General-purpose I/O ports
39
P30/PWM
F
General-purpose I/O port
Also serves as an 8-bit PWM.
40
P31/BUZR
F
General-purpose I/O port
Also serves as a buzzer output.
41
P32/MSKI
F
General-purpose I/O port
Also serves as a modem timer.
42,
43
P33,
P34
F
General-purpose I/O ports
44,
45,
46
P35/SK1,
P36/SI1,
P37/SO1
F
General-purpose I/O ports
Also serve as an 8-bit serial I/O output 1.
34 to 38
P40 to P44
J
General-purpose I/O ports
85 to 92
P50/AN00 to
P57/AN07
H
General-purpose output ports
Also serve as an analog input.
47,
48,
49
P60/TMO1,
P61/TMO2,
P62/TCLK
F
General-purpose I/O ports
Also serve as an 8/16-bit timer.
51
P63/MSKO
F
General-purpose I/O port
Also serves as a modem output.
52
P64
F
General-purpose I/O port
53,
54,
55
P65/BSK1,
P66/BSI1,
P67/BSO1
F
General-purpose I/O ports
Also serve as a serial I/O output 1 with 1-byte buffer.
56,
57,
58
P70/SK2,
P71/SI2,
P72/SO2
I
General-purpose I/O ports
Also serve as an 8-bit serial I/O output 2.
(Continued)
*1: FPT-100P-M06
*2: MQP-100C-P01
6
MB89890 Series
(Continued)
Pin no.
QFP*1, MQP*2
Pin name
Circuit type
Function
60,
61,
62
P73/BSK2,
P74/BSI2,
P75/BSO2
I
General-purpose I/O ports
Also serve as a serial I/O output 2 with 1-byte buffer.
63,
64
P76,
P77
I
General-purpose I/O ports
65 to 72
P80 to P87
J
General-purpose output ports
73 to 80
P90/INT20 to
P97/INT27
F
General-purpose I/O ports
External interrupt input is hysteresis input.
81,
82,
83
PA0/INT28,
PA1/INT29,
PA2/INTA
F
General-purpose I/O ports
External interrupt input is hysteresis input.
96,
97 to 100
PA3/INTB,
PA4/INT0 to
PA7/INT3
F
General-purpose I/O ports
External interrupt input is hysteresis input.
DTMF
K
DTMF signal output pin
1, 50
VCC
–
Power supply pin
8, 59
VSS
–
Power supply (GND) pin
93
VCC (AVCC)
–
Power supply pin
84
VSS (AVSS)
–
Power supply GND pin
94
AVR
–
A/D converter reference input pin
95
*1: FPT-100P-M06
*2: MQP-100C-P01
7
MB89890 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Main clock
• Oscillator feedback resistor: approximately
1 MΩ at 5 V
X1
N-ch
A
Remarks
P-ch
X0
P-ch
N-ch
Main clock control signal
Subclock
• Oscillator feedback resistor: approximately
4.5 MΩ at 5 V
X1A
N-ch
B
P-ch
X0A
P-ch
N-ch
Subclock control signal
C
• Output pull-up resistor (P-ch)
At approximately 50 kΩ/5 V
• Hysteresis input
R
P-ch
D
N-ch
• CMOS output
• CMOS input
• Pull-up resistor optional
R
P-ch
E
P-ch
N-ch
(Continued)
8
MB89890 Series
Type
Circuit
Remarks
• CMOS output
• Hysteresis input
• Pull-up resistor optional
R
P-ch
P-ch
F
N-ch
• CMOS output
P-ch
G
N-ch
• N-ch open-drain output
• Analog input
P-ch
H
N-ch
Analog input
• N-ch open-drain output
• Hysteresis input
• Pull-up resistor optional
R
P-ch
I
N-ch
(Continued)
9
MB89890 Series
(Continued)
Type
Circuit
Remarks
• N-ch open-drain output
• Pull-up resistor optional
R
P-ch
J
N-ch
• DTMF analog output
K
OPAMP
10
MB89890 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the
voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC
is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz)
and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when
power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required for even power-on reset (optional) and
release from stop mode.
11
MB89890 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P899
The MB89P899 is a one-time PROM version of the MB89890 series.
1. Features
• 60-Kbyte PROM on chip
• Option can be set using the EPROM programmer.
• Equivalency to the MBM27C1001, in EPROM mode (when programmed with the EPROM programmer),
supports 4-byte programming mode.
2. Memory Space
Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below.
Single chip
Address
00000H
EPROM mode
(Corresponding addresses
on the EPROM programmer)
00000H
I/O
00080H
RAM
2 KB
Not available
00880H
Not available
00FE4H
00FE4H
Option area
Option area
00FFCH
00FFCH
01000H
01000H
PROM
60 KB
PROM
60 KB
0FFFFH
0FFFFH
Not available
1FFFFH
3. Programming to the EPROM
In EPROM mode the MB89P899 functions equivalent to the MBM27C1001. This allows the EPROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 60 Kbytes (01000H to 0FFFFH ) the EPROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to MBM27C1001.
(2) Load program data into the EPROM programmer at 01000H to 0FFFFH.
Load option data into addresses 00FE4H to 00FFCH. (For information about each corresponding options,
see “7. Setting OTPROM Options.”)
(3) Program to 00FE4H to 00FFCH, and 01000H to 0FFFFH with the EPROM programmer.
12
MB89890 Series
4. Recommended Screening Conditions
High-Temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150˚C, 48 h
Data verification
Assembly
5. Programming Yield
Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming
yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Part number
MB89P899
Package
QFP-100
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-100QF-32DP-8LA
Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
13
MB89890 Series
7. Setting OTPROM Options
The programming procedure is the same as that for the program data. Options can be set by programming
values at the addresses shown on the memory map. The relationship between bits and options is shown on
the following bit map.
• PROM Option Bitmap
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Single/
double
clock
1:2 clock
systems
0:1 clock
system
Reset
output
1: Yes
0: No
Power-on
reset
1: Yes
0: No
Oscillation stabilization
time
11 218/FCH10 216/FCH
01 212/FCH00 23/FCH
P13, P12
Pull-up
1: No
0: Yes
P11, P10
Pull-up
1: No
0: Yes
P07, P06
Pull-up
1: No
0: Yes
P05, P04
Pull-up
1: No
0: Yes
P03, P02
Pull-up
1: No
0: Yes
P01, P00
Pull-up
1: No
0: Yes
P65, P64
Pull-up
1: No
0: Yes
P63, P62
Pull-up
1: No
0: Yes
P61, P60
Pull-up
1: No
0: Yes
P37, P36
Pull-up
1: No
0: Yes
P35, P34
Pull-up
1: No
0: Yes
P33, P32
Pull-up
1: No
0: Yes
P31, P30
Pull-up
1: No
0: Yes
PA7, PA6
Pull-up
1: No
0: Yes
PA5, PA4
Pull-up
1: No
0: Yes
PA3, PA2
Pull-up
1: No
0: Yes
PA1, PA0
Pull-up
1: No
0: Yes
P97, P96
Pull-up
1: No
0: Yes
P95, P94
Pull-up
1: No
0: Yes
P93, P92
Pull-up
1: No
0: Yes
P91, P90
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Readable
and writable
Readable
and writable
Readable
and writable
P44
Pull-up
1: No
0: Yes
P43
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
00FF8H
P77
Pull-up
1: No
0: Yes
P76
Pull-up
1: No
0: Yes
P75
Pull-up
1: No
0: Yes
P74
Pull-up
1: No
0: Yes
P73
Pull-up
1: No
0: Yes
P72
Pull-up
1: No
0: Yes
P71
Pull-up
1: No
0: Yes
P70
Pull-up
1: No
0: Yes
00FFCH
P87
Pull-up
1: No
0: Yes
P86
Pull-up
1: No
0: Yes
P85
Pull-up
1: No
0: Yes
P84
Pull-up
1: No
0: Yes
P83
Pull-up
1: No
0: Yes
P82
Pull-up
1: No
0: Yes
P81
Pull-up
1: No
0: Yes
P80
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Readable
and writable
Readable
and writable
Readable
and writable
00FE8H
P17, P16
Pull-up
1: No
1: Yes
P15, P14
Pull-up
1: No
1: Yes
00FECH
P67, P66
Pull-up
1: No
0: Yes
00FF0H
00FE4H
00FF4H
Notes: • Note that option area address values are equivalent to every fourth address to accommodate 4-byte
programming mode.
• Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.
14
MB89890 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
3. Memory Space
MB89PV890
MBM27C512-20TV
0000H
I/O
0080H
0100H
Register
0200H
RAM
2 KB
0880H
1000H
1000H
External ROM
60 KB
FFFFH
EPROM
60 KB
FFFFH
4. Programming Procedure
(1) Set the EPROM programmer to MBM27C512-20TV.
(2) Load program data into the EPROM programmer at 1000H to FFFFH.
(3) Program to 1000H to FFFFH with the EPROM programmer.
15
MB89890 Series
■ BLOCK DIAGRAM
CMOS I/O port 3
Timebase timer
RST
Reset circuit
(watchdog)
X0
X1
Oscillator
(Max 8 MHz)
Oscillator
(32.768 kHz)
Modem timer
P32/MSKI
P33
P34
P35/SK1
P36/SI1
P37/SO1
P40 to P44
N-ch open-drain output port 5
8-bit
A/D converter
8
8
8
P50/AN00
to P57/AN07
8
CMOS output port 2
Internal bus
CMOS I/O port 1
Internal bus
P2 0 to P27
P31/BUZR
5
CMOS I/O port 0
P1 0 to P17
Buzzer output
N-ch open-drain output port 4
8
P0 0 to P07
P30/PWM
8-bit
serial I/O
Clock control
X0A
X1A
8-bit
PWM timer
CMOS I/O port 6
P60/TMO1
P61/TMO2
P62/TCLK
8/16-bit timer
Modem output
P63/MSKO
P64
P65/BSK1
P66/BSI1
P67/BSO1
8-bit serial I/O
with 1-byte buffer
RAM
1.5 Kbytes or 2.0 Kbytes
P70/SK2
P71/SI2
P72/SO2
P73/BSK2
P74/BSI2
P75/BSO2
P76
P77
F 2 M C- 8L
CPU
ROM
48 Kbytes or 60 Kbytes
N-ch open-drain I/O port 7
8
N-ch open-drain output port 8
DTMF
DTMF generator
P80 to P87
8
CMOS I/O pots 9, A
4
The other pins
V CC × Ê2, V SS × Ê2
M O D0, M O D1
AV CC , AVR, AV SS
16
External interrupt 2
External interrupt 1
12
4
4
P90/INT20
to P97/INT27
PA0/INT28
to PA3/INTB
PA4/INT0
to PA7/INT3
MB89890 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89890 series offer 64 Kbytes of memory for storing all of I/O, data, and program
areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/
O area. The data area can be divided into register, stack, and direct areas, according to the application. The
program area is allocated from exactly the opposite end, that is, near the highest address. The tables of interrupt
reset vectors and vector call instructions are allocated from the highest address within the program area. The
memory space of the MB89890 series is structured as illustrated below:
• Memory Space
MB89898
MB89899
0000H
0000H
I/O
MB89P899
0000H
I/O
MB89PV890
0000H
I/O
I/O
007FH
0080H
007FH
0080H
007FH
0080H
007FH
0080H
00FFH
0100H
00FFH
0100H
00FFH
0100H
00FFH
0100H
Register
01FFH
0200H
RAM
1.5 KB
Register
01FFH
0200H
RAM
2.0 KB
Register
01FFH
0200H
RAM
2.0 KB
Register
01FFH
0200H
RAM
2.0 KB
067FH
0680H
3FFFH
4000H
FFFFH
087FH
0880H
087FH
0880H
087FH
0880H
0FFFH
1000H
0FFFH
1000H
0FFFH
1000H
ROM
48 KB
ROM
60 KB
FFFFH
ROM
60 KB
FFFFH
External ROM
60 KB
FFFFH
17
MB89890 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose
memory registers. The following dedicated registers are provided:
Program counter (PC): A 16-bit-long register for indicating the instruction storage positions
Accumulator (A):
A 16-bit-long temporary register for arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit-long register which is used for arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit-long register for index modification
Extra pointer (EP) :
A 16-bit-long pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit-long pointer for indicating a stack area
Program status (PS) :
A 16-bit-long register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
indeterminate
T
: Temporary accumulator
indeterminate
IX
: Index register
indeterminate
EP
: Extra pointer
indeterminate
SP
: Stack pointer
indeterminate
PS
: Program status
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR) (see the diagram below).
• Structure of the Program Status Register
15
PS
14
13
12
10
9
8
Vacancy Vacancy Vacancy
RP
RP
18
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89890 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and
bits for control of CPU operations at the time of an interrupt.
H-flag:Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag:Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
High-low
0
0
0
High
0
1
1
1
0
2
1
1
3
Low
N-flag:Set to ‘1’ if the highest bit becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.
Z-flag:Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.
V-flag:Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag:Set to ‘1’ when a carry or borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’
otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB89890 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit-long register for storing data
The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register
bank pointer (RP).
• Register Bank Configuration
This address = 0100H + 2 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
20
MB89890 Series
■ I/O MAP
Address
Write/read
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
Vacancy
06H
Vacancy
07H
(R/W)
SCC
System clock control register
08H
(R/W)
SMC
Standby control register
09H
(R/W)
WDTC
Watchdog control register
0AH
(R/W)
TBTC
Time-base timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
(R/W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BZCR
Buzzer register
10H
(R/W)
PDR5
Port 5 data register
Vacancy
11H
12H
(R/W)
PDR6
Port 6 data register
13H
(R/W)
DDR6
Port 6 direction register
14H
(R/W)
PDR7
Port 7 data register
15H
16H
Vacancy
(R/W)
PDR8
Port 8 data register
Vacancy
17H
18H
(R/W)
PDR9
Port 9 data register
19H
(R/W)
DDR9
Port 9 data direction register
1AH
(R/W)
PDRA
Port A data register
1BH
(R/W)
DDRA
Port A data direction register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
(R/W)
CNTR
PWM control register
1FH
(W)
COMR
PWM compare register
(Continued)
21
MB89890 Series
Address
Write/read
Register name
20H
(R/W)
DTMC
DTMF control register
21H
(R/W)
DTMD
DTMF data register
22H
(R/W)
SBMR
Serial mode register with1-byte buffer
23H
(R/W)
SBFR
Serial flag register with1-byte buffer
(W)
SBUFW
Serial write register with1-byte buffer
(R)
SBUFR
Serial read register with1-byte buffer
25H
(R)
SBDR
Serial data register with1-byte buffer
26H
(R/W)
T2CR
Timer 2 control register
27H
(R/W)
T1CR
Timer 1 control register
28H
(R/W)
T2DR
Timer 2 data register
29H
(R/W)
T1DR
Timer 1 data register
2AH
(R/W)
MODC
Modem output control register
2BH
(R/W)
MODA
Modem output data register
24H
Register description
Vacancy
2CH
2DH
(R/W)
ADC1
A/D converter control register 1
2EH
(R/W)
ADC2
A/D converter control register 2
2FH
(R/W)
ADCD
A/D converter data register
30H
(R/W)
EIE1
External interrupt 1 enable register
31H
(R/W)
EIF1
External interrupt 1 flag register
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
34H
(R/W)
MDC1
Modem timer control 1 register
35H
(R/W)
MDC2
Modem timer control 2 register
36H
(R/W)
MLDH
Modem timer “H” level data register
37H
(R/W)
MLDL
Modem timer “L” level data register
38H
Vacancy
39H
Vacancy
3AH
Vacancy
3BH
Vacancy
3CH
Vacancy
3DH
(R/W)
SSEL
Serial I/O port switching register
3EH
Vacancy
3FH
Vacancy
(Continued)
22
MB89890 Series
(Continued)
Address
Write/read
Register name
40H to 7BH
Register description
Vacancy
7CH
(W)
ILR1
Interrupt level register 1
7DH
(W)
ILR2
Interrupt level register 2
7EH
(W)
ILR3
Interrupt level register 3
7FH
Vacancy
Note: Do not use vacancies.
23
MB89890 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Input voltage
Symbol
Value
Unit
Remarks
Min
Max
VCC
VSS – 0.3
VSS + 7.0
V
AVCC
VSS – 0.3
VSS + 7.0
V
Set VCC = AVCC*
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed “AVCC +
0.3 V”.
VSS – 0.3
VCC + 0.3
V
Except P40 to P44, P70 to P77,
P80 to P87
VSS – 0.3
VSS + 7.0
V
P40 to P44, P70 to P77,
P80 to P87
VI
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
“L” level maximum output current
IOL

20
mA
Peak value
“L” level average output current
IOLAV

10
mA
Specified by the average value
of 1 hour.
“L” level total maximum output
current
∑IOL

120
mA
Peak value
“L” level total average output current
∑IOLAV

40
mA
Specified by the average value
of 1 hour.
“H” level maximum output current
IOH

–20
mA
Peak value
“H” level average output current
IOHAV

–10
mA
Specified by the average value
of 1 hour.
“H” level total maximum output
current
∑IOH

–60
mA
Peak value
“H” level total average output
current
∑IOHAV

–20
mA
Specified by the average value
of 1 hour.
Power consumption
PD

200
mW
Operating temperature
TA
–20
+85
°C
Storage temperature
Tstg
–55
+150
°C
*: Use AVCC and VCC set to the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
MB89890 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Parameter
Operating temperature
Remarks
Max
2.2*
6.0
V
See Figure 1.
1.5
6.0
V
Retains the RAM state in the
stop mode
AVR
2.0
AVCC
V
TA
–20
+85
°C
VCC
AVCC
Power supply voltage
Unit
Min
*: This value varies with the DTMF generator assurance range.
Figure 1 Operation Assurance Range
6
Operating voltage (V)
5
: Highest gear speed
: Lowest gear speed
Operation assurance range
4
3
2
1
1
2
3
4
5
6
7
8
9
10
Main clock operating frequency (MHz)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MB89890 Series
3. DC Characteristics
Parameter
“H” level input
voltage
“L” level input
voltage
Symbol
Pin
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Condition
Unit Remarks
Min
Typ
Max
VIH
P00 to P07, P10 to P17
—
0.7 VCC
—
VCC + 0.3
V
VIHS
P30 to P37, P60 to P67,
P90 to P97, PA0 to
PA7,
RST, MOD0, MOD1,
X0, X0A
—
0.8 VCC
—
VCC + 0.3
V
VIL
P00 to P07, P10 to P17
—
VSS −
0.3
—
0.3 VCC
V
VILS
P30 to P37, P60 to P67,
P90 to P97, PA0 to
PA7,
RST, MOD0, MOD1,
X0, X0A
—
VSS −
0.3
—
0.2 VCC
V
P40 to P47, P70 to P77,
P80 to P87
—
VSS −
0.3
—
VSS + 7.0
V
N-ch opendrain
P50 to P57
—
VSS −
0.3
—
VCC + 0.3
V
N-ch opendrain
Open-drain
output pin
VD
applied voltage
“H” level output
VOH
voltage
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
IOH = –2.0 mA
P60 to P67, P90 to P97,
PA0 to PA7
2.4
—
—
V
VOL1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
IOL = 4.0 mA
P60 to P67, P90 to P97,
PA0 to PA7
—
—
0.4
V
VOL2
RST
IOL = 4.0 mA
—
—
0.4
V
VOL3
P40 to P44, P70 to P77,
IOL = 8.0 mA
P80 to P87
—
—
0.6
V
ILI
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P44, P50 to P57,
0.45 V < VI <
P60 to P67, P70 to P77,
VCC
P80 to P87, P90 to P97,
PA0 to PA7, MOD0,
MOD1
—
—
±5
µA
RPULL
P00 to P07, P10 to P17,
P30 to P37, P40 to P44
P60 to P67, P70 to P77,
P80 to P87, P90 to P97,
PA0 to PA7, RST
100
With pullup resistor
kΩ
(Except
RST)
“L” level output
voltage
Input leakage
current
(Hi-z output
leakage
current)
Pull-up
resistance
VI = 0.0 V
25
50
Without
pull-up
resistor
(Continued)
26
MB89890 Series
Pin
ICC
ICCS1
Power supply
current
VCC
ICCS2
ICCH1
ICCH2
ICSB
ICCT
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Condition
Unit Remarks
Min
Typ
Max
FCH = 4 MHz
VCC = 5.0 V
Highest
in the main
—
6
9
mA
gear speed
clock
operation
FCH = 4 MHz
VCC = 3.0 V
Lowest
in the main
—
1.2
1.8
mA
gear speed
clock
operation
FCH = 8 MHz
VCC = 5.0 V
Highest
in the main
—
13
26
mA
gear speed
clock
operation
FCH = 8 MHz
VCC = 3.0 V
Lowest
in the main
—
3
5
mA
gear speed
clock
operation
FCH = 4 MHz
Highest
VCC = 5.0 V
—
2.5
4
mA
in the main
gear speed
sleep mode
FCH = 8 MHz
Highest
VCC = 5.0 V
—
4
8
mA
in the main
gear speed
sleep mode
FCL =
32.768 kHz
VCC = 3.0 V
—
15
2.5
µA
in the
subclock
sleep mode
TA = +25°C
VCC = 3.0 V
in the
—
—
1
µA
subclock
stop mode
TA = +85°C
VCC = 3.0 V
in the
—
1
10
µA
subclock
stop mode
FCL =
32.768 kHz
VCC = 3.0 V
—
50
75
µA
in the subclock
operation
FCL =
32.768 kHz
VCC = 3.0 V
—
—
15
µA
in the watch
mode
(Continued)
When DTMF operation is stopped
Parameter
Symbol
27
MB89890 Series
(Continued)
During DTMF operation
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
SymParameter
Pin
Condition
Unit Remarks
bol
Min
Typ
Max
FCH = 4 MHz
VCC = 5.0 V
Highest
in the main
—
8
12
mA
gear speed
clock
operation
FCH = 4 MHz
VCC = 3.0 V
Lowest
in the main
—
2.3
3.4
mA
gear speed
clock
operation
ICCD
VCC
FCH = 8 MHz
VCC = 5.0 V
Highest
in the main
—
17
31
mA
gear speed
clock
Power supply
operation
current
FCH = 8 MHz
VCC = 3.0 V
Lowest
in the main
—
6
11
mA
gear speed
clock
operation
When A/D
—
1.5
3.5
mA conversion
IA
is operating
AVCC
FCH = 8 MHz
When A/D
conversion
IAH
—
1
5
µA
is not
operating
Other than AVCC,
Input capacitance CIN
AVSS, VCC, and
—
—
10
—
pF
VSS
28
MB89890 Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –20°C to +85°C)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Parameter
RST “L” pulse width
tZLZH
RST “H” pulse width
tZHZL
—
48 tXCYL
—
ns
24 tXCYL
—
ns
Note: tXCYL is the oscillation cycle input to the X0.
tZHZL
tZLZH
RST
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = –20°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
50
ms
Power-on reset function only
—
ms
Due to repeated operations
Min
Max
—
1
Note: Make sure that power supply rises within the selected oscillation stabilization time selected.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
29
MB89890 Series
(3) Clock Timing
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling
time
30
Symbol
Pin name
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –20°C to +85°C)
Value
Condition
Unit
Remarks
Min
Typ
Max
FCH
X0, X1
1
—
8
MHz Main clock
FCL
X0A, X1A
—
32.768
—
kHz
tHCYL
X0, X1
125
—
1000
ns
Main clock
tLCYL
X0A, X1A
—
30.5
—
µs
Subclock
PWH
PWL
X0
20
—
—
ns
External clock
PWLH
PWLL
X0A
—
15.2
—
µs
External clock
tCR1
tCF1
X0
—
—
24
ns
tCR2
tCF2
X0A
—
—
200
ns
Subclock
—
External clock
MB89890 Series
• X0 and X1 Timing and Conditions of Applied Voltage
tHCYL
0.8 VCC
X0
0.2Ê VCC
PWH
PWL
tCF1
tCR1
• Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X0
X1
X1
Open
FCH
C0
FCH
C1
• X0A and X1A Timing and Conditions of Applied Voltage
tLCYL
0.8 VCC
X0A
0.2Ê VCC
PWHL
PWLL
tCF2
tCR2
• Subclock Conditions
When a crystal
or
ceramic resonator is used
X0A
When an external clock is used
X0A
X1A
X1A
Open
Rd
FCL
FCL
C0
C1
31
MB89890 Series
(4) Instruction Cycle
Parameter
Symbol
Instruction cycle
tinst
(minimum execution time)
Value
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 0.5 µs when operating
at FCH = 8 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
Notes : • When operating at the main clock, tinst varies with the execution time (gear) setting, within the following
range: Min = 4/FCH, Max = 64/FCH.
• When operating at the subclock, tinst = 2/FCL.
(5) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1
FAR*1
C1*2
C2*2
*1: Fujitsu Media Devices Acoustic Resonator
FAR part number
Frequency (MHz)
(built-in capacitor type)
Temperature
Loading
characteristics of
FAR frequency
capacitors*2
(TA = –20°C to +60°C)
FAR-C4 A-03580- 01
3.58
±0.5%
±0.5%
FAR-C4 G-10000- 05
10.00
±0.5%
±0.5%
Inquiry: FUJITSU MEDIA DEVICES LIMITED
32
Initial deviation of
FAR frequency
(TA = +25°C)
Built-in
MB89890 Series
• Sample Application of Ceramic Resonator
X0
X1
C1
• Mask ROM products
Resonator
manufacturer
Murata Mfg. Co., Ltd.
Resonator
CSA8.00MTZ
CST8.00MTW
C2
Frequency (MHz)
8.00
C1 (pF)
C2 (pF)
R
30
30
Not required
Built-in
Built-in
Not required
Inquiry: Murata Mfg. Co., Ltd
• Murata Electronics North America. Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
33
MB89890 Series
(6) Serial I/O Timing
Parameter
Symbol
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Internal shift
clock mode
SCK
External shift
clock mode
2 tinst*
—
µs
–200
200
ns
200
—
ns
200
—
ns
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
200
—
ns
2 × tXCYL
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
200
—
ns
2 × tXCYL
*: For information on tinst, see “(4) Instruction Cycle.”
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
t SLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
SCK
tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
34
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB89890 Series
(7) Peripheral Input Timing
Parameter
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Pin
Unit Remarks
Min
Max
Symbol
Peripheral input “H” level pulse
width
tILIH
INT20 to INTA
INT0 to INT3
2 tinst*
—
µs
Peripheral input “L” level pulse
width
tIHIL
INT20 to INTA
INT0 to INT3
2 tinst*
—
µs
*: For information on tinst, see “(4) Instruction Cycle.”
tILIH
tIHIL
INT20 to INTA
INT0 to INT3
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
35
MB89890 Series
(8) Electrical Characteristics of DTMF Generator
Parameter
Symbol
Condition
—
—
Operating voltage range
Output load requirements
RO
Min
2.5
(AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Unit
Remarks
Typ
Max
5.0
6.0
V
VCC = 2.5 V to 6.0 V
20
—
—
kΩ
DTMF output offset voltage
VMOF
(at signal output)
VCC = 5.0 V
—
0.4
—
V
DTMF output amplitude
(ROW single tone)
VMFOR
VCC = 5.0 V
–16.3
–14.0
–12.5
dBm
Difference between
COLUMN and ROW levels
RMF
—
1.6
2.0
2.4
dB
—
—
—
7
%
Distortion ratio
—
Defined when
the DTMF pin
is connected to
a pull-down resistor.
When the
DTMF pin is
open.
RO = 200 kΩ
• Output Level Measurement Circuit
VCC
X0
0.1 µF
8 MHz
Lowpass filter
16.0 kHz
DTMF
RO
X1
–48 dB/oct
VSS
36
Audio analizer
Output level
MB89890 Series
5. A/D Converter Electrical Characteristics
Parameter
Symbol
Pin
name
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)
Value
Condition
Unit Remarks
Min
Typ
Max
Resolution
—
—
8
bit
Total error
—
—
±1.5
LSB
—
—
±1.0
LSB
—
Linearity error
Differential linearity
error
Zero transition
voltage
V0T
Full-scale transition
voltage
VFST
—
—
AVR =
AVCC = 5.0 V AVSS – 1.5
LSB
—
±0.9
LSB
AVSS + 0.5
LSB
AVSS + 1.5
LSB
mV
AVR – 1.5
LSB
AVR – 1.5
LSB
AVR + 1.5
LSB
mV
—
—
0.5
LSB
—
44 tinst*
—
µs
—
12 tinst*
—
µs
—
—
10
µA
0.0
—
AVR
V
0.0
—
AVCC
V
—
100
300
µA
When
starting A/D
conversion
—
—
1
µA
When
starting A/D
conversion
Interchannel disparity
A/D mode conversion
time
—
Sense mode
conversion time
Analog port input
current
—
IAIN
Analog input voltage
—
Reference voltage
—
AN0 to
AN7
IR
AVR
Reference voltage
supply current
IRH
AVR =
AVCC = 5.0 V
1 LSB =
AVR/256
*: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable by the A/D converter
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
37
MB89890 Series
Digital output
1111 1111
1111 • 1110
0000
0000
0000
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Theoretical conversion value
Actual conversion value
(1 LSB × N + VOT)
1 LSB =
AVR
256
Linearity error =
Differential linearity error =
Linearity error
Total error =
VNT – (1 LSB × N + VOT)
1 LSB
V( N + 1 ) T – VNT – 1
1 LSB
VNT – (1 LSB × N + 1 LSB)
1 LSB
0010
0001
0000
VOT
VNT
V(N + 1)T
VFST
Analog input
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch analog
input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
.
C =. 33 pF
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 6 kΩ
Close for 8 instruction cycles after starting
A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
• Order of turning on A/D converter and analog input
Make sure to turn on the digital power supply (VCC) before or at the same time with turning on the A/D converter
power supply (AVCC, AVSS) and application of AN00 to AN07.
To turn off the power, turn off the A/D converter power supply (AVCC, AVSS) and stop the analog input (AN00 to
AN07) before or at the same time with turning off the digital power supply (VCC).
38
MB89890 Series
■ EXAMPLE CHARACTERISTICS
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VOL vs. IOL
V CC – VOH vs. IOL
V OL (V)
V CC – V OH (V)
V CC = 2.2 V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V CC = 2.5 V
V CC = 3.0 V
V CC = 4.0 V
V CC = 5.0 V
V CC = 6.0 V
T A = +25°C
0
1
2
3
4
5
6
7
8
9 10
I OL (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
(CMOS Input)
4.0
–2.5 –3.0
I OH (mA)
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
–0
.00
V CC = 4.0 V
V CC = 5.0 V
V CC = 6.0 V
T A = +25°C
4.5
T A = +25°C
V CC = 3.0 V
V IN vs. V CC
V IN (V)
5.0
5.0
V CC = 2.5 V
(4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
V IN vs. V CC
V IN (V)
4.5
V CC = 2.2 V
1.1
T A = +25°C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
–.5
–1.0 –1.5 –2.0
1.00
2.00 3.00
4.00
5.00
6.00 7.00
V CC (V)
–0
.00
V IHS
V ILS
1.00
2.00 3.00
4.00
5.00
6.00 7.00
V CC (V)
V IHS : “H” level input voltage threshold as
hysteresis input
V ILS : “L” level input voltage threshold as
hysteresis input
39
MB89890 Series
(5) Power Supply Current (External Clock)
Characteristics of Current Consumption
in the Main Clock Operation
Characteristics of Current Consumption
in the DTMF and Main Clock Operation
I CC (mA)
I CC vs. V CC
10
9 T A = +25°C
F CH = 8 MHz
8
7
Dividing
-by-4
Dividing
-by-8
6
5
Dividing
-by-16
Dividing
-by-64
4
3
2
1
0
2
3
4
5
6
V CC (V)
I CCD vs. V CC
I CCD (mA)
12
11 T A = +25°C
10 F CH = 8 MHz
9
8
7
6
5
4
3
2
1
0
4
2
3
Characteristics of Current Consumption
in the Main Sleep Mode
Dividing
-by-8
Dividing
-by-16
Dividing
-by-64
5
6
V CC (V)
Characteristics of Current Consumption
in the Subclock Operation
I CCS vs. V CC
I CCS (mA)
10
T A = +25°C
9
F CH = 8 MHz
8
I CCSB vs. V CC
I CCSB (µA)
10
9 T A = +25°C
8 F CL = 32.768 kHz
7
7
Dividing
-by-4
6
6
5
5
4
4
3
3
2
1
2
1
0
2.5
Dividing
-by-4
0
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
V CC (V)
6
V CC (V)
Characteristics of Current Consumption
in the Watch Mode
Characteristics of Current Consumption
in the Subclock Stop
I CCT vs. V CC
I CCT (µA)
30
T A = +25°C
25 F CL = 32.768 kHz
I CCH vs. V CC
I CCH (A)
2.0
1.8 T A = +25°C
F CL = 32.768 kHz
1.6
1.4
20
1.2
15
1.0
0.8
10
0.6
0.4
5
0.2
0
0.0
2
40
2.5
3
3.5
4
4.5
5
5.5 6
V CC (V)
2
2.5
3
3.5
4
4.5
5
5.5 6
V CC (V)
MB89890 Series
(6) Pull-up Resistance
R PULL vs. VCC
R PULL (kΩ)
1000
T A = +25°C
300
100
50
10
0
1
2
3
4
5
6
7
V CC (V)
41
MB89890 Series
■ MASK OPTIONS
Part number
No.
1
Specifying procedure
Pull-up resistors
• P00 to P07
• P10 to P17
• P30 to P37
• P40 to P44
• P60 to P67
• P70 to P77
• P80 to P87
• P90 to P97
• PA0 to PA7
MB89898/9
MB89P899
MB89PV890
Specify when
Specify with EPROM
programmer
Specifying not
ordering masking
Select by single pin
• P00 to P07
• P10 to P17
• P30 to P37
• P40 to P44
• P60 to P67
• P70 to P77
• P80 to P87
• P90 to P97
• PA0 to PA7
possible
Fixed to no
pull-up resistor
Set in the above combinations
Select by 2-pin pair
• P00 to P07
• P10 to P17
• P30 to P37
• P60 to P67
• P90 to P97
• PA0 to PA7
Select by single pin
• P40 to P44
• P70 to P77
• P80 to P87
Set in the above
combinations
Selectable
Selectable
Fixed to
power-on reset
optional
2
Power-on reset (POR)
• Power-on reset provided
• No power-on reset
3
Selectable
Selection of the oscillation stabiliWTM1 WTM0
zation time (OSC)
0
0:
The oscillation stabilization time
0
1:
initial value can be set with WTM1
1
0:
bit and WTM0 bit.
1
1:
4
Reset pin output (RST)
• Reset output provided
• No reset output
Selectable
Selectable
Fixed to reset output optional
5
Selection of clock mode (CLK)
• Double clock mode
• Single clock mode
Selectable
Selectable
Fixed to double
clock mode
23/FCH
212/FCH
216/FCH
218/FCH
Selectable
WTM1 WTM0
0
0:
0
1:
1
0:
1
1:
23/FCH
212/FCH
216/FCH
218/FCH
Fixed to oscillator
stabilization 218/
FCH
■ ORDERING INFORMATION
Part number
MB89898PF
MB89899PF
MB89P899PF
MB89PV890CF
42
Package
100-pin Plastic QFP
(FPT-100P-M06)
100-pin Ceramic MQFP
(MQP-100C-P01)
Remarks
MB89890 Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
2001 FUJITSU LIMITED F100008S-c-4-4
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
(Continued)
43
MB89890 Series
(Continued)
100-pin Ceramic MQFP
(MQP-100C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.35(.486)TYP
+0.40
1.20 –0.20
.047
0.65±0.15
(.0256±.0060)
+.016
–.008
0.65±0.15
(.0256±.0060)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.30±0.08
(.012±.003)
18.85(.742)
TYP
0.30±0.08
(.012±.003)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
10.82(.426)
0.15±0.05 MAX
(.006±.002)
C
44
1994 FUJITSU LIMITED M100001SC-1-2
Dimensions in mm (inches)
MB89890 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0110
 FUJITSU LIMITED Printed in Japan