GSI GS73024AB-12

GS73024AB
Commercial Temp
Industrial Temp
ns
3.3 V VDD
VDD and VSS
Asynchronous SRAM
Features
119-Bump Ball Grid Array Package
• Fast access time: 8, 10, 12 ns
• CMOS low power operation: 250/200/170 mA at minimum
cycle time
• Single 3.3 V ± 0.3V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
B: 14 mm x 22 mm, 119-bump, 1.27mm pitch BGA
Description
The GS73024A is a high speed CMOS Static RAM organized
as 131,072 words by 24 bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply, and all inputs and outputs are
TTL-compatible. The GS73024A is available in a 119-bump
BGA package.
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
A16
Column
Decoder
CE
I/O Buffer
Control
WE
OE
DQ1
DQ24
Pin Descriptions
Symbol
Description
Symbol
A0 to A16
Address input
DQ1 to DQ24
Data input/output
WE
Write enable input
OE
Output enable input
CE
Chip enable input
VSS
Ground
VDD
+3.3 V power supply
Rev: 1.03 12/2005
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Description
© 2003, GSI Technology
GS73024AB
119-Bump, 1.27 mm Pitch BGA Pad Out—Top View (Package B)
Rev: 1.03 12/2005
1
2
3
4
5
6
7
A
NC
A3
A2
A16
A1
A0
NC
B
NC
A7
A6
CE
A5
A4
NC
C
DQ13
NC
NC
NC
NC
NC
DQ12
D
DQ14
VDD
VSS
VSS
VSS
VDD
DQ11
E
DQ15
NC
VDD
VSS
VDD
NC
DQ10
F
DQ16
VDD
VSS
VSS
VSS
VDD
DQ9
G
DQ17
NC
VDD
VSS
VDD
NC
DQ8
H
DQ18
VDD
VSS
VSS
VSS
VDD
DQ7
J
VDD
VSS
VDD
VSS
VDD
VSS
VDD
K
DQ19
VDD
VSS
VSS
VSS
VDD
DQ6
L
DQ20
NC
VDD
VSS
VDD
NC
DQ5
M
DQ21
VDD
VSS
VSS
VSS
VDD
DQ4
N
DQ22
NC
VDD
VSS
VDD
NC
DQ3
P
DQ23
VDD
VSS
VSS
VSS
VDD
DQ2
R
DQ24
NC
NC
NC
NC
NC
DQ1
T
NC
A11
A10
WE
A9
A8
NC
U
NC
A15
A14
OE
A13
A12
NC
2/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Truth Table
CE
OE
WE
Mode
DQ0 to DQ23
VDD Current
H
X
X
Not selected
High Z
ISB1, ISB2
L
L
H
Read
Data Out
L
X
L
Write
Data In
L
H
H
Output disable
High Z
IDD
X: “H” or “L”
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
Input Voltage
VIN
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Output Voltage
VOUT
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Allowable BGA power dissipation
PD
1.5
W
Storage temperature
TSTG
–55 to 150
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.03 12/2005
3/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -10/12
VDD
3.0
3.3
3.6
V
Supply Voltage for -8
VDD
3.135
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VDD+0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Ambient Temperature,
Commercial Range
TAc
0
—
70
o
C
Ambient Temperature,
Industrial Range
TAi
–40
—
85
o
C
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
CIN
VIN = 0 V
5
pF
I/O Capacitance
COUT
VOUT = 0 V
7
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
IIL
VIN = 0 to VDD
–1 uA
1 uA
Output Leakage Current
IOL
Output High Z,
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4 mA
2.4
—
Output Low Voltage
VOL
IOL = +4 mA
—
0.4 V
Rev: 1.03 12/2005
4/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
AC Test Conditions
Output Load 1
Parameter
Conditions
Input high level
VIH = 2.4 V
Input low level
VIL = 0.4 V
Input rise time
t = 1 V/ns
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output Load 2
Output reference level
1.4 V
3.3 V
Output load
Fig. 1& 2
DQ
50Ω
30pF1
VT = 1.4 V
589Ω
DQ
Notes:
1. Includes scope and jig capacitance
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
5pF1
434Ω
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70°C
–40 to 85°C
8 ns
10 ns
12 ns
8 ns
10 ns
12 ns
IDD
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
250 mA
200 mA
170 mA
260 mA
210 mA
180 mA
Standby
Current
ISB1
CE ≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
40 mA
40 mA
30 mA
50 mA
50 mA
40 mA
Standby
Current
ISB2
CE ≥ VDD - 0.2V
All other inputs
≥ VDD - 0.2V or ≤ 0.2V
Operating
Supply
Current
Rev: 1.03 12/2005
10 mA
5/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20 mA
© 2003, GSI Technology
GS73024AB
AC Characteristics
Read Cycle
Parameter
Symbol
-8
-10
-12
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
8
—
10
—
12
—
ns
Address access time
tAA
—
8
—
10
—
12
ns
Chip enable access time (CE)
tAC
—
8
—
10
—
12
ns
MUX control to output valid (V/S)
tAV
—
8
—
10
—
12
ns
Output enable to output valid (OE)
tOE
—
4
—
5
—
6
ns
Output hold from address change
tOH
3
—
3
—
3
—
ns
Output hold from MUX controls change
tOH1
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
tLZ*
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
tOLZ*
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
tHZ*
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
tOHZ*
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = VIL, WE = VIH
tRC
Address
tAA
tOH
Data Out
Rev: 1.03 12/2005
Previous Data
Data valid
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Read Cycle 2: WE = VIH
tRC
Address
tAA
CE
tAC
tHZ
tLZ
OE
Data Out
tOLZ
tOE
tOHZ
Data valid
High impedance
Write Cycle
Parameter
Symbol
-8
-10
-12
Min
Max
Min
Max
Min
Max
Unit
Write cycle time
tWC
8
—
10
—
12
—
ns
Address valid to end of write
tAW
5.5
—
7
—
8
—
ns
Chip enable to end of write (CE)
tCW
5.5
—
7
—
8
—
ns
Data set up time
tDW
4
—
5
—
6
—
ns
Data hold time
tDH
0
—
0
—
0
—
ns
Write pulse width
tWP
5.5
—
7
—
8
—
ns
Address set up time
tAS
0
—
0
—
0
—
ns
Write recovery time (WE)
tWR
0
—
0
—
0
—
ns
Write recovery time ( CE )
tWR1
0
—
0
—
0
—
ns
Output Low Z from end of write
tWLZ*
2
—
3
—
3
—
ns
Write to output in High Z
tWHZ*
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested
Rev: 1.03 12/2005
7/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tAS
tWP
WE
tDW
Data In
tDH
Data valid
tWHZ
tWLZ
Data Out
High impedance
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tWP
WE
tDW
Data In
Data valid
Data Out
Rev: 1.03 12/2005
tDH
High impedance
8/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Package Dimensions—119-Bump FPBGA (Package B, Variation 1)
(Date Code: yyww.31)
Pin #1 Corner
BOTTOM VIEW
A1
Ø0.10S C
Ø0.30S C AS B S
Ø0.60~0.90 (119x)
1 2 3 4 5 6 7
Ø1.00(3x) REF
20.32
22±0.20
19.50
B
0.70 REF
1.27
7.62
12.00
C
Rev: 1.03 12/2005
0.15 C
30 TYP.
14±0.20
SEATING PLANE
0.50~0.70
2.06.±0.13
0.90±0.10
0.15 C
A
0.20(4x)
0.56±0.05
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1.27
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
7 6 5 4 3 2 1
9/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
(Date Code: yyww.3H)
TOP VIEW
A1
1
2
3
4
5
6
BOTTOM VIEW
A1
Ø0.10S C
Ø0.30S C AS B S
Ø0.60~0.90 (119x)
7
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
20.32
22±0.10
1.27
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
B
1.27
C
Rev: 1.03 12/2005
SEATING PLANE
A
0.20(4x)
14±0.10
0.50~0.70
1.86.±0.13
0.15 C
7.62
10/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Ordering Information
Part Number1
Package
Access Time
Temp. Range
GS73024AB-8
119-Bump BGA2
8 ns
Commercial
GS73024AB-10
119-Bump BGA2
10 ns
Commercial
GS73024AB-12
119-Bump BGA2
12 ns
Commercial
GS73024AB-8I
119-Bump BGA2
8 ns
Industrial
GS73024AB-10I
119-Bump BGA2
10 ns
Industrial
GS73024AB-12I
119-Bump BGA2
12 ns
Industrial
Status
Notes:
1. Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS73024AB-12T.
2. Please see pages 9 and 10 for date code information for Variation 1 and Variation 2 of the 119-bump BGA.
Rev: 1.03 12/2005
11/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS73024AB
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
• Creation of new datasheet
GS73024A_r1
GS73024A_r1; GS73024A_r1_01
Content
GS73024A_r1_01;
GS73024A_r1_02
Content/Format
GS73024A_r1_02;
GS73024A_r1_03
Content
Rev: 1.03 12/2005
Page/Revisions/Reason
• Corrected pinout (balls C3, C5, R2, R3, R5, R6 changed to NC)
• Corrected pin description table to reflect pinout corrections
• Corrected truth table to reflect pinout corrections
• Updated format
• Added variation informtion to package mechanical
• Added Variation 2 119 BGA to datasheet
• Added date codes to mechanicals
12/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology