Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available • Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices SigmaCIO™ Family Overview The GS8342T08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8342T08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, A0 presets an internal 1 bit address counter. The counter increments by 1 (toggles) for each beat of a burst of two data transfer. Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, the LSB is internally set to 0 for the first read or write transfer, and incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always one address pin less than the advertised index depth (e.g., the 8M x 8 has a 2M addressable index). Parameter Synopsis -333 -300 -267* -250 -200 -167 tKHKH 3.0 ns 3.3 ns 3.75 ns 4.0 ns 5.0 ns 6.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns * The 267 MHz speed bin is only available on the x18 part. Rev: 1.02 8/2005 1/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 1M x 36 SigmaCIO DDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (144Mb) SA R/W BW2 K BW1 LD SA MCL/SA (72Mb) CQ B NC DQ27 DQ18 SA BW3 K BW0 SA NC NC DQ8 C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35 2. MCL = Must Connect Low Rev: 1.02 8/2005 2/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 2M x 18 SigmaCIO DDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (72Mb) SA R/W BW1 K NC LD SA SA CQ B NC DQ9 NC SA NC K BW0 SA NC NC DQ8 C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17 2. MCL = Must Connect Low Rev: 1.02 8/2005 3/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 4M x 9 SigmaCIO DDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (72Mb) SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC DQ4 C NC NC NC VSS SA SA SA VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ5 VDDQ VSS VSS VSS VDDQ NC NC DQ3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ6 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ2 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ7 NC VDDQ VSS VSS VSS VDDQ NC NC DQ1 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS SA SA SA VSS NC NC NC P NC NC DQ8 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 is set to 0 at the beginning of each access. 2. MCL = Must Connect Low Rev: 1.02 8/2005 4/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 4M x 8 SigmaCIO DDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (72Mb) SA R/W NW1 K NC LD SA SA CQ B NC NC NC SA NC K NW0 SA NC NC DQ3 C NC NC NC VSS SA SA SA VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS SA SA SA VSS NC NC NC P NC NC DQ7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 is set to 0 at the beginning of each access. 2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7 3. MCL = Must Connect Low Rev: 1.02 8/2005 5/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R/W Synchronous Read/Write Input — BW0–BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active Low CQ Output Echo Clock Output — CQ Output Echo Clock Output — VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.5 V Nominal VSS Power Supply: Ground Supply — Note: NC = Not Connected to die or any other pin Rev: 1.02 8/2005 6/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Background Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted. Deselect Cycles Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer and then execute the deselect command, returning the output drivers to high-Z. A high on the LD# pin prevents the RAM from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations. SigmaCIO DDR-II B2 SRAM Read Cycles The SRAM executes pipelined reads. The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The read command (LD# low and R/W# high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, for a total of two transfers per address load. SigmaCIO DDR-II B2 SRAM Write Cycles The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command (LD# and R/W# low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures data in on the next rising edge of K#, for a total of two transfers per address load. Rev: 1.02 8/2005 7/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Special Functions Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 3 D0–D8 Byte 4 D9–D17 Written Unchanged Unchanged Written Beat 1 Beat 2 Output Register Control SigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM. Rev: 1.02 8/2005 8/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Example Four Bank Depth Expansion Schematic LD3 LD2 LD1 LD0 R/W A0–An K Bank 0 Bank 1 Bank 2 Bank 3 A A A A LD LD LD LD R/W R/W R/W R/W K CQ DQ K C C K CQ K DQ C CQ DQ C CQ DQ C DQ1– CQ Note: For simplicity BWn (or NWn), K, and C are not shown. Rev: 1.02 8/2005 9/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z. Rev: 1.02 8/2005 10/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Common I/O SigmaCIO DDR-II B2 SRAM Truth Table Kn LD R/W ↑ 1 ↑ ↑ DQ Operation A+0 A+1 X Hi-Z Hi-Z Deselect 0 0 D@Kn+1 D@Kn+1 Write 0 1 Q@Kn+1 or Cn+1 Q@Kn+2 or Cn+2 Read Note: Q is controlled by K clocks if C clocks are not used. B2 Byte Write Clock Truth Table BW BW Current Operation D D K↑ (tn+1) K↑ (tn+2) K↑ (tn) K↑ (tn+1) K↑ (tn+2) T T Write Dx stored if BWn = 0 in both data transfers D1 D2 T F Write Dx stored if BWn = 0 in 1st data transfer only D1 X F T Write Dx stored if BWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.02 8/2005 11/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 B2 Nybble Write Clock Truth Table NW NW Current Operation D D K↑ (tn+1) K↑ (tn+2) K↑ (tn) K↑ (tn+1) K↑ (tn+2) T T Write Dx stored if NWn = 0 in both data transfers D1 D2 T F Write Dx stored if NWn = 0 in 1st data transfer only D1 X F T Write Dx stored if NWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more NWn = 0, then NW = “T”, else NW = “F”. *Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles. Rev: 1.02 8/2005 12/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 x36 Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Data In Don’t Care Don’t Care Don’t Care 1 0 1 1 Don’t Care Data In Don’t Care Don’t Care 0 0 1 1 Data In Data In Don’t Care Don’t Care 1 1 0 1 Don’t Care Don’t Care Data In Don’t Care 0 1 0 1 Data In Don’t Care Data In Don’t Care 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Data In Data In Data In Don’t Care 1 1 1 0 Don’t Care Don’t Care Don’t Care Data In 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Don’t Care Data In Don’t Care Data In 0 0 1 0 Data In Data In Don’t Care Data In 1 1 0 0 Don’t Care Don’t Care Data In Data In 0 1 0 0 Data In Don’t Care Data In Data In 1 0 0 0 Don’t Care Data In Data In Data In 0 0 0 0 Data In Data In Data In Data In x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In x8 Nybble Write Enable (NWn) Truth Table NW0 NW1 D0–D3 D4–D7 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In Rev: 1.02 8/2005 13/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 B2 State Diagram Power-Up LOAD NOP LOAD LOAD LOAD Load New Address LOAD READ WRITE DDR Read LOAD DDR Write Notes: 1. The internal address burst counter is a 1 bit counter (i.e., when first address is A0, next internal burst address is A0+1). 2. “READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low. 3. “LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High. Rev: 1.02 8/2005 14/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 oC TSTG Storage Temperature –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.7 1.8 1.9 V Reference Voltage VREF 0.68 — 0.95 V Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O) and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD.. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C Rev: 1.02 8/2005 15/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes DC Input Logic High VIH (dc) VREF + 0.10 VDD + 0.3 V V 1 DC Input Logic Low VIL (dc) –0.3 V VREF – 0.10 V 1 Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns). 4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns). HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 0.20 — V 3,4 AC Input Logic Low VIL (ac) — VREF – 0.20 V 3,4 VREF (ac) — 5% VREF (DC) V 1 VREF Peak to Peak AC Voltage Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKHKH VDD + 1.0 V VSS 50% 50% VDD VSS – 1.0 V 20% tKHKH Rev: 1.02 8/2005 VIL 16/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Clock Capacitance CCLK — 5 6 pF Notes Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level VDDQ Input low level 0V Max. input slew rate 2 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ RQ = 250 Ω (HSTL I/O) VREF = 0.75 V 50Ω VT = VDDQ/2 Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IINDOFF VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –2 uA 2 uA 2 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Rev: 1.02 8/2005 17/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 VDDQ V 1, 3 Output Low Voltage VOL1 Vss VDDQ/2 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = –1.0 mA 6. IOL = 1.0 mA Operating Currents -333 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR -300 -267 -250 -200 -167 Notes 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 880 mA 900 mA 800 mA 820 mA n/a n/a 700 mA 720 mA 600 mA 620 mA 520 mA 540 mA 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 770 mA 790 mA 720 mA 740 mA 630 mA 650 mA 630 mA 650 mA 540 mA 560 mA 480 mA 500 mA 2, 3 Operating Current (x9): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 770 mA 790 mA 720 mA 740 mA n/a n/a 630 mA 650 mA 540 mA 560 mA 480 mA 500 mA 2, 3 Operating Current (x8): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 770 mA 790 mA 720 mA 740 mA n/a n/a 630 mA 650 mA 540 mA 560 mA 480 mA 500 mA 2, 3 Standby Current (NOP): DDR ISB1 Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V 350 mA 360 mA 330 mA 340 mA 300 mA 310 mA 300 mA 310 mA 280 mA 290 mA 260 mA 270 mA 2, 4 Notes: 1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.02 8/2005 18/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Parameter Symbol -333 -300 -267 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics Clock K, K Clock Cycle Time C, C Clock Cycle Time tKHKH tCHCH 3.0 3.5 3.3 4.2 3.75 5.5 4.0 6.3 5.0 7.88 6.0 8.4 ns tTKC Variable tKCVar — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 ns K, K Clock High Pulse Width C, C Clock High Pulse Width tKHKL tCHCL 1.2 — 1.32 — 1.6 — 1.6 — 2.0 — 2.4 — ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width tKLKH tCLCH 1.2 — 1.32 — 1.6 — 1.6 — 2.0 — 2.4 — ns K to K High C to C High tKHKH 1.35 — 1.49 — 1.8 — 1.8 — 2.2 — 2.7 — ns K, K Clock High to C, C Clock High tKHCH 0 1.3 0 1.45 0 1.8 0 1.8 0 2.3 0 2.8 ns DLL Lock Time tKCLock 1024 — 1024 — 1024 — 1024 — 1024 — 1024 — cycle K Static to DLL reset tKCReset 30 — 30 — 30 — 30 — 30 — 30 — ns K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid tKHQV tCHQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold tKHQX tCHQX –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid tKHCQV tCHCQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold tKHCQX tCHCQX –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns CQ, CQ High Output Valid tCQHQV — 0.25 — 0.27 — 0.30 — 0.30 — 0.35 — 0.40 ns 7 CQ, CQ High Output Hold tCQHQX –0.25 — –0.27 — –0.30 — –0.30 — –0.35 — –0.40 — ns 7 K Clock High to Data Output High-Z C Clock High to Data Output High-Z tKHQZ tCHQZ — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z tKHQX1 tCHQX1 –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 Address Input Setup Time tAVKH 0.4 — 0.4 — 0.5 — 0.5 — 0.6 — 0.7 — ns Control Input Setup Time tIVKH 0.4 — 0.4 — 0.5 — 0.5 — 0.6 — 0.7 — ns Data Input Setup Time tDVKH 0.28 — 0.3 — 0.35 — 0.35 — 0.4 — 0.5 — ns 5 6 Output Times Setup Times Rev: 1.02 8/2005 19/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 2 Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Parameter Symbol -333 -300 -267 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics (Continued) Hold Times Address Input Hold Time tKHAX 0.4 — 0.4 — 0.5 — 0.5 — 0.6 — 0.7 — ns Control Input Hold Time tKHIX 0.4 — 0.4 — 0.5 — 0.5 — 0.6 — 0.7 — ns Data Input Hold Time tKHDX 0.28 — 0.3 — 0.35 — 0.35 — 0.4 — 0.5 — ns Notes: 1. 2. 3. 4. 5. 6. 7. All Address inputs must meet the specified setup and hold times for all latching clock edges. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). If C, C are tied high, K, K become the references for C, C timing parameters To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations. Rev: 1.02 8/2005 20/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Rev: 1.02 8/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 21/37 CQ CQ DQ C C BWx R/W LD Address K K KHKH KHKH KHIX IVKH NOP A KHKL KHIX IVKH KHAX AVKH KHKL Read A KLKH B CHCQV KHnKH KHnKH Read B CHCQX KLKH C and C Controlled Read First Timing Diagram A CQHQV CHQV NOP A+1 CQHQX B CHQX1 C Write C B+1 C CHQX C D DVKH KHIX IVKH Read D C+1 C+1 KHDX Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 © 2003, GSI Technology Rev: 1.02 8/2005 CQ CQ DQ1 BWx R/W LD Address K K KHKH KHCQX KHCQV KHBX BVKH NOP A KHAX KHBX BVKH AVKH KHKL Read A B KHCQV KHCQX KLKH K and K Controlled Read First Timing Diagram KHnKH Read B A CQHQV KHQX1 A+1 NOP CQHQX B KHQV C B+1 Write C KHQX C C D DVKH C+1 C+1 KHBX BVKH Read D KHDX Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 22/37 © 2003, GSI Technology Rev: 1.02 8/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 23/37 CQ CQ DQ C C BWx R/W LD Address K K CHCQX CHCQV KHIX IVKH NOP CHCQX A KHKH KHKH KHAX AVKH Write A DVKH A+1 KHKL C KHnKH KHnKH Read C KHDX KLKH KLKH A+1 KHIX IVKH KHIX IVKH CHCQV A A B KHKL Read B C and C Controlled Write First Timing Diagram B CQHQV CHQX1 D NOP CHQV B+1 CQHQX C E Write D C+1 CHQX D D NOP D+1 D+1 Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 © 2003, GSI Technology Rev: 1.02 8/2005 CQ CQ KHCQV KHCQX DVKH KLKH A+1 A+1 KHBX BVKH KHBX BVKH KHKL Read B KHCQV A B DQ KHAX A KHCQX KHBX BVKH A KHKH AVKH Write A BWx R/W LD Address K K NOP K and K Controlled Write First Timing Diagram KHDX C KHnKH Read C B CQHQV KHQX1 D KHQV B+1 NOP CQHQX C E C+1 KHQX Write D D D NOP D+1 D+1 Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 24/37 © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up. JTAG Port Registers Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Rev: 1.02 8/2005 25/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram · · · · · · Boundary Scan Register · · 0 Bypass Register 0 108 · 1 · · 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.02 8/2005 26/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x9 X X X X 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 x8 X X X X 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.02 8/2005 27/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Pause IR 0 1 Exit2 IR 0 1 Update DR 1 1 0 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Rev: 1.02 8/2005 28/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 RFU 101 Do not use this instruction; Reserved for Future Use. 1 RFU 110 Do not use this instruction; Reserved for Future Use. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.02 8/2005 29/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VDDQ 1.7 1.8 1.9 V Input High Voltage VIH 1.3 — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.5 V Output High Voltage (IOH = –2 mA) VOH 1.4 — VDD V Output Low Voltage (IOL = 2 mA) VOL VSS — 0.4 V Note: The input level of SRAM pin is to follow the SRAM DC specification. JTAG Port AC Test Conditions Parameter Symbol Min Unit Input High/Low Level VIH/VIL 1.3/0.5 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 0.9 V Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.02 8/2005 30/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min. Max Unit TCK Cycle Time tCHCH 50 — ns TCK High Pulse Width tCHCL 20 — ns TCK Low Pulse Width tCLCH 20 — ns TMS Input Setup Time tMVCH 5 — ns TMS Input Hold Time tCHMX 5 — ns TDI Input Setup Time tDVCH 5 — ns TDI Input Hold Time tCHDX 5 — ns SRAM Input Setup Time tSVCH 5 — ns SRAM Input Hold Time tCHSX 5 — ns Clock Low to Output Valid tCLQV 0 10 ns Rev: 1.02 8/2005 31/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.08 M C Ø0.15 M C A B Ø0.40~0.50 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 17±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 0.15 C B C Rev: 1.02 8/2005 SEATING PLANE 15±0.05 0.15(4x) 0.25~0.40 1.40 MAX. (0.36) 0.53 0.20 C 10.0 32/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Ordering Information—GSI SigmaCIO DDR-II SRAM Org Part Number1 Type Package Speed (MHz) TA2 Status 4M x 8 GS8342T08E-333 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 C ES 4M x 8 GS8342T08E-300 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 C ES 4M x 8 GS8342T08E-250 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 C ES 4M x 8 GS8342T08E-200 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 C ES 4M x 8 GS8342T08E-167 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 C ES 4M x 8 GS8342T08E-333I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 I ES 4M x 8 GS8342T08E-300I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 I ES 4M x 8 GS8342T08E-250I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 I ES 4M x 8 GS8342T08E-200I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 I ES 4M x 8 GS8342T08E-167I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 I ES 4M x 9 GS8342T09E-333 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 C ES 4M x 9 GS8342T09E-300 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 C ES 4M x 9 GS8342T09E-250 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 C ES 4M x 9 GS8342T09E-200 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 C ES 4M x 9 GS8342T09E-167 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 C ES 4M x 9 GS8342T09E-333I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 I ES 4M x 9 GS8342T09E-300I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 I ES 4M x 9 GS8342T09E-250I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 I ES 4M x 9 GS8342T09E-200I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 I ES 4M x 9 GS8342T09E-167I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 I ES 2M x 18 GS8342T18E-333 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 C ES 2M x 18 GS8342T18E-300 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 C ES 2M x 18 GS8342T18E-267 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 267 C ES 2M x 18 GS8342T18E-250 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 C ES 2M x 18 GS8342T18E-200 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 C ES 2M x 18 GS8342T18E-167 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 C ES 2M x 18 GS8342T18E-333I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 I ES 2M x 18 GS8342T18E-300I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 I ES 2M x 18 GS8342T18E-267I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 267 I ES Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.02 8/2005 33/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Ordering Information—GSI SigmaCIO DDR-II SRAM Org Part Number1 Type Package Speed (MHz) TA2 Status 2M x 18 GS8342T18E-250I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 I ES 2M x 18 GS8342T18E-200I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 I ES 2M x 18 GS8342T18E-167I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 I ES 1M x 36 GS8342T36E-333 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 C ES 1M x 36 GS8342T36E-300 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 C ES 1M x 36 GS8342T36E-250 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 C ES 1M x 36 GS8342T36E-200 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 C ES 1M x 36 GS8342T36E-167 SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 C ES 1M x 36 GS8342T36E-333I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 333 I ES 1M x 36 GS8342T36E-300I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 300 I ES 1M x 36 GS8342T36E-250I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 250 I ES 1M x 36 GS8342T36E-200I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 200 I ES 1M x 36 GS8342T36E-167I SigmaCIO DDR-II B2 SRAM 165-Pin BGA 167 I ES 4M x 8 GS8342T08GE-333 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 C ES 4M x 8 GS8342T08GE-300 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 C ES 4M x 8 GS8342T08GE-250 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 C ES 4M x 8 GS8342T08GE-200 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 C ES 4M x 8 GS8342T08GE-167 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 C ES 4M x 8 GS8342T08GE-333I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 I ES 4M x 8 GS8342T08GE-300I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 I ES 4M x 8 GS8342T08GE-250I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 I ES 4M x 8 GS8342T08GE-200I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 I ES 4M x 8 GS8342T08GE-167I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 I ES Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.02 8/2005 34/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Ordering Information—GSI SigmaCIO DDR-II SRAM Org Part Number1 Type Package Speed (MHz) TA2 Status 4M x 9 GS8342T09GE-333 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 C ES 4M x 9 GS8342T09GE-300 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 C ES 4M x 9 GS8342T09GE-250 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 C ES 4M x 9 GS8342T09GE-200 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 C ES 4M x 9 GS8342T09GE-167 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 C ES 4M x 9 GS8342T09GE-333I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 I ES 4M x 9 GS8342T09GE-300I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 I ES 4M x 9 GS8342T09GE-250I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 I ES 4M x 9 GS8342T09GE-200I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 I ES 4M x 9 GS8342T09GE-167I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 I ES 2M x 18 GS8342T18GE-333 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 C ES 2M x 18 GS8342T18GE-300 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 C ES 2M x 18 GS8342T18GE-267 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 267 C ES 2M x 18 GS8342T18GE-250 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 C ES 2M x 18 GS8342T18GE-200 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 C ES 2M x 18 GS8342T18GE-167 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 C ES 2M x 18 GS8342T18GE-333I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 I ES 2M x 18 GS8342T18GE-300I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 I ES Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.02 8/2005 35/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Ordering Information—GSI SigmaCIO DDR-II SRAM Org Part Number1 Type Package Speed (MHz) TA2 Status 2M x 18 GS8342T18GE-267I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 267 I ES 2M x 18 GS8342T18GE-250I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 I ES 2M x 18 GS8342T18GE-200I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 I ES 2M x 18 GS8342T18GE-167I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 I ES 1M x 36 GS8342T36GE-333 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 C ES 1M x 36 GS8342T36GE-300 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 C ES 1M x 36 GS8342T36GE-250 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 C ES 1M x 36 GS8342T36GE-200 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 C ES 1M x 36 GS8342T36GE-167 SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 C ES 1M x 36 GS8342T36GE-333I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 333 I ES 1M x 36 GS8342T36GE-300I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 300 I ES 1M x 36 GS8342T36GE-250I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 250 I ES 1M x 36 GS8342T36GE-200I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 200 I ES 1M x 36 GS8342T36GE-167I SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 167 I ES Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.02 8/2005 36/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 Revision History Rev. Code: Old; New Types of Changes Format or Content GS8342Txx_r1 Format • Creation of new datasheet GS8342Txx_r1; GS8342Txx_r1_01 Content • Corrected DQ reference in pin description table Content • Removed 400 MHz speed bin • Added 333 MHz speed bin • Added x9 part • Updated timing diagrams • Added 267 MHz speed bin for x18 • Added RoHS-compliant information GS8342Txx_r1_01; GS8342Txx_r1_02 Rev: 1.02 8/2005 Revisions 37/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology