Preliminary GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 SigmaRAM™ Family Overview GS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 1M addressable index). Parameter Synopsis Rev: 1.01 9/2005 - 333 -300 -250 -200 -167 tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns 1/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 8M x 8 SigmaQuad SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W NW1 K NC LD SA SA CQ B NC NC NC SA NC K NW0 SA NC NC Q3 C NC NC NC VSS SA SA SA VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS SA SA SA VSS NC NC NC P NC NC Q7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 2/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 8M x 9 SigmaQuad SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC Q4 C NC NC NC VSS SA SA SA VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS SA SA SA VSS NC NC NC P NC NC Q8 SA SA C SA SA NC D0 NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW controls writes to D0:D7 1. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 3/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 4M x 18 SigmaQuad SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/SA (144Mb) SA R/W BW1 K NC LD SA SA CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 4/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 2M x 36 SigmaQuad SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/SA (288Mb) SA R/W BW2 K BW1 LD SA VSS/SA (144Mb) CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. 3. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 5/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R/W Read/Write Contol Pin Input Write Active Low; Read Active High NW0–NW1 Synchronous Nybble Writes Input Active Low x08 Version BW0–BW1 Synchronous Byte Writes Input Active Low x18 Version BW0–BW3 Synchronous Byte Writes Input Active Low x36 Version K Input Clock Input Active High C Output Clock Input Active High TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — K Input Clock Input Active Low C Output Clock Output Active Low DOFF DLL Disable — Active Low LD Synchronous Load Pin — Active Low CQ Output Echo Clock Output Active Low CQ Output Echo Clock Output Active High Dn Synchronous Data Inputs Input Qn Synchronous Data Outputs Output VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 or 1.5 V Nominal VSS Power Supply: Ground Supply — Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. NC = Not Connected to die or any other pin Rev: 1.01 9/2005 6/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Background Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Burst of 2 Sigma SIO-II SRAM DDR Read The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K. Burst of 2 Sigma SIO-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K. Rev: 1.01 9/2005 7/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. 1b. 1c. Apply VDD. Apply VDDQ. Apply VREF (may also be applied at the same time as VDDQ). 2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled. Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized. DLL Constraints • The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 21). • The DLL cannot operate at a frequency lower than 119 MHz. • If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage. Power-Up Sequence (Doff controlled) Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation K K VDD VDDQ VREF Doff Power-Up Sequence (Doff tied High) Power UP Interval Unstable Clocking Interval Stop Clock Interval 30ns Min DLL Locking Interval (1024 Cycles) Normal Operation K K VDD VDDQ VREF Doff Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock. Rev: 1.01 9/2005 8/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Special Functions Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Resulting Write Operation Beat 1 Beat 2 D0–D8 D9–D17 D0–D8 D9–D17 Written Unchanged Unchanged Written Output Register Control SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs. Rev: 1.01 9/2005 9/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Example Four Bank Depth Expansion Schematic R/W3 LD3 R/W2 LD2 R/W1 LD1 R/W0 LD0 A0–An K D1–Dn Bank 0 Bank 1 Bank 2 Bank 3 A A A A R/W R/W R/W R/W LD LD LD LD K D K D K D K Q C Q C Q C D Q C C Q1–Qn Note: For simplicity BWn is not shown. Rev: 1.01 9/2005 10/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Burst of 2 SigmaSIO-II SRAM Depth Expansion Write B Read C Write D Read E Write F Read G Read H Read J NOP K K Address B C D E F G H J LD Bank 1 LD Bank 2 R/W Bank 1 R/W Bank 2 BWx Bank 1 BWx Bank 2 B+1 D Bank 1 F+1 B F D+1 D Bank 2 D C Bank 1 C Bank 1 E Q Bank 1 E+1 H H+1 CQ Bank 1 CQ Bank 1 C Bank 2 C Bank 2 Q Bank 2 C C+1 G G+1 CQ Bank 2 CQ Bank 2 Rev: 1.01 9/2005 11/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology J Preliminary GS8662S08/09/18/36E-333/300/250/200/167 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z. Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table A LD R/W Current Operation D D Q Q K↑ (tn) K↑ (tn) K↑ (tn) K↑ (tn) K↑ (tn+1) K↑ (tn+1) K↑ (tn+1) K↑ (tn+1) X 1 X Deselect X — Hi-Z — V 0 1 Read X — Q0 Q1 V 0 0 Write D0 D1 Hi-Z — Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. “—” indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses. Rev: 1.01 9/2005 12/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 x18 Byte Write Clock Truth Table BW BW Current Operation D D K↑ (tn+1) K↑ (tn+2) K↑ (tn) K↑ (tn+1) K↑ (tn+2) T T Write Dx stored if BWn = 0 in both data transfers D1 D2 T F Write Dx stored if BWn = 0 in 1st data transfer only D1 X F T Write Dx stored if BWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.01 9/2005 13/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 x36 Byte Write Enable (BWn) Truth Table BW3 BW2 BW1 BW0 D27–D35 D18–D26 D9–D17 D0–D8 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Don’t Care Don’t Care Don’t Care Data In 1 0 1 1 Don’t Care Don’t Care Data In Don’t Care 0 0 1 1 Don’t Care Don’t Care Data In Data In 1 1 0 1 Don’t Care Data In Don’t Care Don’t Care 0 1 0 1 Don’t Care Data In Don’t Care Data In 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Don’t Care Data In Data In Data In 1 1 1 0 Data In Don’t Care Don’t Care Don’t Care 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Data In Don’t Care Data In Don’t Care 0 0 1 0 Data In Don’t Care Data In Data In 1 1 0 0 Data In Data In Don’t Care Don’t Care 0 1 0 0 Data In Data In Don’t Care Data In 1 0 0 0 Data In Data In Data In Don’t Care 0 0 0 0 Data In Data In Data In Data In x8 Nybble Write Enable (NWn) Truth Table NW1 NW0 D9–D17 D0–D8 1 1 Don’t Care Don’t Care 0 1 Don’t Care Data In 1 0 Data In Don’t Care 0 0 Data In Data In Rev: 1.01 9/2005 14/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 State Diagram Power-Up LOAD NOP LOAD Load New LOAD LOAD LOAD READ WRITE DDR Read Rev: 1.01 9/2005 LOAD DDR Write 15/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.3 (≤ 2.9 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ +0.3 (≤ 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 o C TSTG Storage Temperature –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.7 1.8 1.9 V Reference Voltage VREF 0.68 — 0.95 V Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O) and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C Rev: 1.01 9/2005 16/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes DC Input Logic High VIH (dc) VREF + 0.1 VDDQ + 0.3 mV 1 DC Input Logic Low VIL (dc) –0.3 VREF – 0.1 mV 1 Note: Compatible with both 1.8 V and 1.5 V I/O drivers HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 0.2 — mV 3,4 AC Input Logic Low VIL (ac) — VREF – 0.2 mV 3,4 VREF (ac) — 5% VREF (DC) mV 1 VREF Peak to Peak AC Voltage Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below. HSTL I/O AC Input Definitions VIH (ac) VREF VIL (ac) Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKHKH VDD + 1.0 V VSS 50% 50% VDD VSS – 1.0 V 20% tKHKH Rev: 1.01 9/2005 VIL 17/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Notes Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level VDDQ Input low level 0V Max. input slew rate 2 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ RQ = 250 Ω (HSTL I/O) VREF = 0.75 V 50Ω VT = VDDQ/2 Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IINDOFF VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –2 uA 2 uA 2 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Rev: 1.01 9/2005 18/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = –1.0 mA 6. IOL = 1.0 mA Rev: 1.01 9/2005 19/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Operating Currents -333 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR -300 -250 -200 -167 Notes 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Operating Current (x9): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Operating Current (x8): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Standby Current (NOP): DDR ISB1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4 Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V Notes: 1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.01 9/2005 20/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Parameter Symbol -333 -300 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics Clock K, K Clock Cycle Time C, C Clock Cycle Time tKHKH tCHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.0 7.9 6.0 8.4 ns tTKC Variable tKCVar — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 ns K, K Clock High Pulse Width C, C Clock High Pulse Width tKHKL tCHCL 1.2 — 1.32 — 1.6 — 2.0 — 2.4 — ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width tKLKH tCLCH 1.2 — 1.32 — 1.6 — 2.0 — 2.4 — ns K to K High C to C High tKHKH 1.35 — 1.49 — 1.8 — 2.2 — 2.7 — ns K, K Clock High to C, C Clock High tKHCH 0 1.3 0 1.45 0 1.8 0 2.3 0 2.8 ns DLL Lock Time tKCLock 1024 — 1024 — 1024 — 1024 — 1024 — cycle K Static to DLL reset tKCReset 30 — 30 — 30 — 30 — 30 — ns K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid tKHQV tCHQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold tKHQX tCHQX –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid tKHCQV tCHCQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold tKHCQX tCHCQX –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns CQ, CQ High Output Valid tCQHQV — 0.25 — 0.27 — 0.30 — 0.35 — 0.40 ns 7 CQ, CQ High Output Hold tCQHQX –0.25 — –0.27 — –0.30 — –0.35 — –0.40 — ns 7 K Clock High to Data Output High-Z C Clock High to Data Output High-Z tKHQZ tCHQZ — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z tKHQX1 tCHQX1 –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 Address Input Setup Time tAVKH 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Control Input Setup Time tIVKH 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Data Input Setup Time tDVKH 0.28 — 0.3 — 0.35 — 0.4 — 0.5 — ns 5 6 Output Times Setup Times Rev: 1.01 9/2005 21/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 2 © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Parameter Symbol -333 -300 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics (Continued) Hold Times Address Input Hold Time tKHAX 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Control Input Hold Time tKHIX 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Data Input Hold Time tKHDX 0.28 — 0.3 — 0.35 — 0.4 — 0.5 — ns Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). 3. If C, C are tied high, K, K become the references for C, C timing parameters 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations. Rev: 1.01 9/2005 22/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 K Controlled Read-First Timing Diagram Read A Write B Read C Read E Deselect Deselect KHKL KHKH KLKH K KH#KH K AVKH KHAX Address A B C IVKH KHIX IVKH KHIX D E LD R/W IVKH KHIX B BWx B+1 DVKH KHDX B D B+1 KHQX1 A Q KHQZ A+1 KHQV C C+1 KHQX D D+1 CQ KHCQV KHCQX CQHQV CQHQX CQ Rev: 1.01 9/2005 23/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 K Controlled Write-First Timing Diagram NOP Write A Read B Read C Write D Write E Deselect KHKL KHKH KLKH K KH#KH K AVKH KHAX A Address IVKH B C D E KHIX LD IVKH KHIX R/W KHIX IVKH A BWx A+1 D D+1 E E+1 D D+1 E E+1 KHDX DVKH A D A+1 KHQV KHQX1 B Q KHQX B+1 C KHQZ C+1 KHCQX KHCQV CQ KHCQX KHCQV CQHQX CQHQV CQ Rev: 1.01 9/2005 24/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 C Controlled Read-First Timing Diagram Read A Write B Read C Read D Deselect Deselect KHKL KHKH KLKH K KHKH# K AVKH KHAX A Address B C D IVKH KHIX LD IVKH KHIX R/W KHIX IVKH B BWx B+1 KHDX DVKH B D B+1 CLCH KHCH CHCL CHCH C CHCH# C CHQX1 A Q CHQZ A+1 CHQV C CHQX C+1 D D+1 CQ CHCQX CHCQV CQHCV CQHQX CQ Rev: 1.01 9/2005 25/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 C Controlled Write-First Timing Diagram NOP Write A Read B Write C Write D Read E Deselect KHKL KHKH KLKH K KH#KH K KHAX AVKH A Addr IVKH B C D E KHIX LD IVKH KHIX R/W KHIX IVKH A BWx A+1 C C+1 D D+1 C C+1 D D+1 KHDX DVKH A D A+1 KHKL KHKH KLKH C KH#KH C CHQZ CHQX1 CHQX CHQV B Q B+1 CQ CQHQV CQHQX CQ JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.01 9/2005 26/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up. JTAG Port Registers Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.01 9/2005 27/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 JTAG TAP Block Diagram · · · · · · · · Boundary Scan Register · · 1 · 108 0 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Control Signals TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x9 X X X X 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 x8 X X X X 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. Rev: 1.01 9/2005 28/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Pause IR 0 1 Exit2 IR 0 1 Update DR 1 1 0 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the Rev: 1.01 9/2005 29/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.01 9/2005 30/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 RFU 101 Do not use this instruction; Reserved for Future Use. 1 RFU 110 Do not use this instruction; Reserved for Future Use. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VDDQ 1.7 1.8 1.9 V Input High Voltage VIH 1.3 — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.5 V Output High Voltage (IOH = –2 mA) VOH 1.4 — VDD V Output Low Voltage (IOL = 2 mA) VOL VSS — 0.4 V Note: The input level of SRAM pin is to follow the SRAM DC specification. Rev: 1.01 9/2005 31/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 JTAG Port AC Test Conditions Parameter Symbol Min Unit Input High/Low Level VIH/VIL 1.3/0.5 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 0.9 V Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input Rev: 1.01 9/2005 32/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 JTAG Port AC Electrical Characteristics Parameter Symbol Min. Max Unit TCK Cycle Time tCHCH 50 — ns TCK High Pulse Width tCHCL 20 — ns TCK Low Pulse Width tCLCH 20 — ns TMS Input Setup Time tMVCH 5 — ns TMS Input Hold Time tCHMX 5 — ns TDI Input Setup Time tDVCH 5 — ns TDI Input Hold Time tCHDX 5 — ns SRAM Input Setup Time tSVCH 5 — ns SRAM Input Hold Time tCHSX 5 — ns Clock Low to Output Valid tCLQV 0 10 ns Rev: 1.01 9/2005 33/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 17±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 10.0 0.20 C B Rev: 1.01 9/2005 SEATING PLANE 0.20(4x) 0.36~0.46 1.50 MAX. C 15±0.05 34/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaSIO-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 2M x 36 GS8662S36E-333 SigmaSIO-II SRAM 165-bump BGA 333 C 2M x 36 GS8662S36E-300 SigmaSIO-II SRAM 165-bump BGA 300 C 2M x 36 GS8662S36E-250 SigmaSIO-II SRAM 165-bump BGA 250 C 2M x 36 GS8662S36E-200 SigmaSIO-II SRAM 165-bump BGA 200 C 2M x 36 GS8662S36E-167 SigmaSIO-II SRAM 165-bump BGA 167 C 2M x 36 GS8662S36E-333I SigmaSIO-II SRAM 165-bump BGA 333 I 2M x 36 GS8662S36E-300I SigmaSIO-II SRAM 165-bump BGA 300 I 2M x 36 GS8662S36E-250I SigmaSIO-II SRAM 165-bump BGA 250 I 2M x 36 GS8662S36E-200I SigmaSIO-II SRAM 165-bump BGA 200 I 2M x 36 GS8662S36E-167I SigmaSIO-II SRAM 165-bump BGA 167 I 4M x 18 GS8662S18E-333 SigmaSIO-II SRAM 165-bump BGA 333 C 4M x 18 GS8662S18E-300 SigmaSIO-II SRAM 165-bump BGA 300 C 4M x 18 GS8662S18E-250 SigmaSIO-II SRAM 165-bump BGA 250 C 4M x 18 GS8662S18E-200 SigmaSIO-II SRAM 165-bump BGA 200 C 4M x 18 GS8662S18E-167 SigmaSIO-II SRAM 165-bump BGA 167 C 4M x 18 GS8662S18E-333I SigmaSIO-II SRAM 165-bump BGA 333 I 4M x 18 GS8662S18E-300I SigmaSIO-II SRAM 165-bump BGA 300 I 4M x 18 GS8662S18E-250I SigmaSIO-II SRAM 165-bump BGA 250 I 4M x 18 GS8662S18E-200I SigmaSIO-II SRAM 165-bump BGA 200 I 4M x 18 GS8662S18E-167I SigmaSIO-II SRAM 165-bump BGA 167 I 8M x 9 GS8662S09E-333 SigmaSIO-II SRAM 165-bump BGA 333 C 8M x 9 GS8662S09E-300 SigmaSIO-II SRAM 165-bump BGA 300 C 8M x 9 GS8662S09E-250 SigmaSIO-II SRAM 165-bump BGA 250 C 8M x 9 GS8662S09E-200 SigmaSIO-II SRAM 165-bump BGA 200 C 8M x 9 GS8662S09E-167 SigmaSIO-II SRAM 165-bump BGA 167 C 8M x 9 GS8662S09E-333I SigmaSIO-II SRAM 165-bump BGA 333 I 8M x 9 GS8662S09E-300I SigmaSIO-II SRAM 165-bump BGA 300 I 8M x 9 GS8662S09E-250I SigmaSIO-II SRAM 165-bump BGA 250 I 8M x 9 GS8662S09E-200I SigmaSIO-II SRAM 165-bump BGA 200 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01 9/2005 35/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaSIO-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 8M x 9 GS8662S09E-167I SigmaSIO-II SRAM 165-bump BGA 167 I 8M x 8 GS8662S08E-333 SigmaSIO-II SRAM 165-bump BGA 333 C 8M x 8 GS8662S08E-300 SigmaSIO-II SRAM 165-bump BGA 300 C 8M x 8 GS8662S08E-250 SigmaSIO-II SRAM 165-bump BGA 250 C 8M x 8 GS8662S08E-200 SigmaSIO-II SRAM 165-bump BGA 200 C 8M x 8 GS8662S08E-167 SigmaSIO-II SRAM 165-bump BGA 167 C 8M x 8 GS8662S08E-333I SigmaSIO-II SRAM 165-bump BGA 333 I 8M x 8 GS8662S08E-300I SigmaSIO-II SRAM 165-bump BGA 300 I 8M x 8 GS8662S08E-250I SigmaSIO-II SRAM 165-bump BGA 250 I 8M x 8 GS8662S08E-200I SigmaSIO-II SRAM 165-bump BGA 200 I 8M x 8 GS8662S08E-167I SigmaSIO-II SRAM 165-bump BGA 167 I 2M x 36 GS8662S36GE-333 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 C 2M x 36 GS8662S36GE-300 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 C 2M x 36 GS8662S36GE-250 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 C 2M x 36 GS8662S36GE-200 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 C 2M x 36 GS8662S36GE-167 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 C 2M x 36 GS8662S36GE-333I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 I 2M x 36 GS8662S36GE-300I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 I 2M x 36 GS8662S36GE-250I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 I 2M x 36 GS8662S36GE-200I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 I 2M x 36 GS8662S36GE-167I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 I 4M x 18 GS8662S18GE-333 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 C 4M x 18 GS8662S18GE-300 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 C 4M x 18 GS8662S18GE-250 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 C 4M x 18 GS8662S18GE-200 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 C 4M x 18 GS8662S18GE-167 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 C 4M x 18 GS8662S18GE-333I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 I 4M x 18 GS8662S18GE-300I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 I 4M x 18 GS8662S18GE-250I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 I 4M x 18 GS8662S18GE-200I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01 9/2005 36/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662S08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaSIO-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 4M x 18 GS8662S18GE-167I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 I 8M x 9 GS8662S09GE-333 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 C 8M x 9 GS8662S09GE-300 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 C 8M x 9 GS8662S09GE-250 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 9 GS8662S09GE-200 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 9 GS8662S09GE-167 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 9 GS8662S09GE-333I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 I 8M x 9 GS8662S09GE-300I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 I 8M x 9 GS8662S09GE-250I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 9 GS8662S09GE-200I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 9 GS8662S09GE-167I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 I 8M x 8 GS8662S08GE-333 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 C 8M x 8 GS8662S08GE-300 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 C 8M x 8 GS8662S08GE-250 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 8 GS8662S08GE-200 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 8 GS8662S08GE-167 SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 8 GS8662S08GE-333I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 333 I 8M x 8 GS8662S08GE-300I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 300 I 8M x 8 GS8662S08GE-250I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 8 GS8662S08GE-200I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 8 GS8662S08GE-167I SigmaSIO-II SRAM RoHS-compliant 165-bump BGA 167 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. SigmaSIO-II Revision History File Name Format/Content 8662Sxx_r1 8662Sxx_r1; 8662Sxx_r1_01 Rev: 1.01 9/2005 Description of changes Creation of datasheet Content Added RoHS-compliant package information 37/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology