HITACHI HD66520TA0

HD66520T
(160-Channel 4-Level Grayscale Display Column Driver with
Internal Bit-Map RAM)
Description
The HD66520 is a column driver for liquid crystal dot-matrix graphic display systems. This LSI
incorporates 160 liquid crystal drive circuits and a 160 × 240 × 2-bit bit-map RAM, which is suitable for
LCDs in portable information devices. It also includes a general-purpose SRAM interface so that draw
access can be easily implemented from a general-purpose CPU. The HD66520 also has a new arbitration
method which prevents flicker when the CPU performs draw access asynchronously. The on-chip display
RAM greatly decreases power consumption compared to previous liquid crystal display systems because
there is no need for high-speed data transfer. The chip also incorporates a four-level grayscale controller
for enhanced graphics capabilities, such as icons on a screen.
Features
•
•
•
•
•
•
•
•
Duty cycle: 1/64 to 1/240
Liquid crystal drive circuits: 160
Low-voltage logic circuit: 3.0 to 5.5-V operation power supply voltage
High-voltage liquid crystal drive circuit: 8 to 28-V liquid crystal drive voltage
Grayscale display: FRC four-level grayscale display
Grayscale memory management: Packed pixel
Internal bit-map display RAM: 76800 bits (160 × 240 lines × two planes)
CPU interface
 SRAM interface
 Address bus: 16 bits, data bus: 8 bits
1014
HD66520T
• High-speed draw function: Supports burst transfer mode
• Arbitration function: Implemented internally (draw access has priority)
• Access time
 180 ns (VCC = 5V operation)
 240 ns (VCC = 3V operation)
• Low power consumption:
VCC = 3.3-V operation
 360 µA during display (logic circuit, liquid crystal drive circuit)
 10 mA during RAM access (logic circuit)
VCC = 5.5-V operation
 400 µA during display (logic circuit, liquid crystal drive circuit)
 16 mA during RAM access (logic circuit)
• On-chip address management function
• Refresh unnecessary
• Internal display off function
• Package: 208-pin TCP
Ordering Information
Type No.
TCP
Outer Lead Pitch (µm)
HD66520TA0
Straight TCP
200
HD66520TB0
Folding TCP
200
1015
V2L
V4L
V3L
V1L
VEE1
VCC1
LS0
LS1
SHL
GND1
FLM
M
CL1
DISPOFF
CS
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND2
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC2
VEE2
V1R
V3R
V4R
V2R
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1016
10
9
8
7
6
5
4
3
2
1
160
159
158
157
156
155
154
153
152
151
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y160
Y159
Y158
Y157
Y156
Y155
Y154
Y153
Y152
Y151
HD66520T
Pin Arrangement
Top View
Note : This figure does not specify the TCP dimensions.
HD66520T
Pin Description
Classification
Symbol
Power
supply
Control
Number
of Pins Function
Pin Name
I/O
VCC1
VCC2
VCC
VCC
—
—
GND1
GND2
GND
GND
—
—
VEE1
VEE2
LCD drive
circuit power
supply
—
—
V1L,
V1R
LCD select
high-level
voltage
Input
2
V2L,
V2R
LCD select
low-level
voltage
Input
2
V3L,
V3R
LCD deselect
high-level
voltage
Input
2
V4L,
V4R
LCD deselect
low- level
voltage
Input
2
LS0,
LS1
LSI ID select
switch pin0
and 1
Input
2
Pins for setting LSI ID no (refer to
signals Pin Functions for details).
SHL
Shift direction Input
control signal
1
Reverses the relationship between LCD
drive output pins Y and addresses.
FLM
First line
marker
Input
1
First line select signal.
CL1
Data transfer
clock
Input
1
Clock signal to transfer the line data to
an LCD display driver block.
M
AC switching
signal
Input
1
Switching signal to convert LCD drive
output to AC.
',632)
Display off
signal
Input
1
Control signal to fix LCD driver outputs
to LCD select high level. When low,
LCD drive outputs Y1 to Y160 are set to
V1, or LCD select high level. Display
can be turned off by setting a common
driver to V1.
)
Pin No.
VCC–GND: logic power supply
VCC–VEE: LCD drive circuit power supply
LCD drive level power supplies See
Figure 1.
The user should apply the same
potential to the L and R side.
1017
HD66520T
Classification
Symbol
Bus
interface
A0 to
A15
Address input Input
16
Upper 9 bits (A15–A7) are used for the
duty-directional addresses, and lower 7
bits (A6–A0) for the output-pin
directional addresses (refer to Pin
Functions for details).
DB0 to
DB7
Data input/
output
I/O
8
Packed-pixel 2-bit/pixel display data
transfer (refer to Pin Functions for
details).
&6
Chip select
signal
Input
1
LSI select signal during draw access
(refer to Pin Functions for details).
:(
Write signal
Input
1
Write-enable signal during draw access
(refer to Pin Functions for details).
2(
Output
enable signal
Input
1
Output-enable signal during draw
access (refer to Pin Functions for
details).
Y1 to
Y160
LCD drive
output
Output 160
LCD
drive
output
Pin No.
Pin Name
I/O
Number
of Pins Function
Each Y outputs one of the four voltage
levels V1, V2, V3, or V4, depending on
the combination of the M signal and
data levels
Note: The number of input outer leads: 48
V1
V3
V4
V2
Figure 1 LCD Drive Levels
1018
HD66520T
Pin Functions
Control Signals
LS0 and LS1 (Input): The LS pins can assign four (0 to 3) ID numbers to four LSIs, thus making it
possible to connect a maximum of four HD66520s sharing the same &6 pin to the same bus (Figure 2.)
SHL (Input): This pin reverses the relationship between LCD drive output pins Y1 to Y160 and
addresses. There is no need to change the address assignment for the display regardless of whether the
HD66520 is mounted from the back or the front of the LCD panel. Refer to Driver Layout and Address
Management for details.
FLM (Input): When the pin is high, it resets the display line counter, returns the display line to the start
line, and synchronizes common signals with frame timing.
CL1 (Input): At each falling edge of data-transfer clock pulses input to this pin, the latch circuits latch
display data and output it to the liquid crystal display driver section.
M (Input): AC voltage needs to be applied to liquid crystals to prevent deterioration due to DC voltage
application. The M pin is a switch signal for liquid crystal drive voltage and determines the AC cycle.
(Input): A control signal to fix liquid crystal driver output to liquid crystal select high level.
When this pin is low, liquid crystal drive outputs Y1 to Y160 are set to liquid crystal select high level V1.
The display can be turned off by setting the outputs of the common driver to level V1. In this case,
display RAM data will be retained. Therefore, if signal ',632)) returns to high level, liquid crystal
drive outputs will return to normal display state. Draw access can be executed when signal ',632)) is
either in high or low state.
',632))
HD66503
HD66503
ID = 0
HD66520
ID = 2
HD66520
320
480
LCD panel
HD66520
ID = 1
HD66520
ID = 3
LS1
LS0
ID No.
RAM Address Arrangement
L
L
0
Upper-left of LCD panel
L
H
1
Lower-left of LCD panel
H
L
2
Upper-right of LCD panel
H
H
3
Lower-right of LCD panel
L: Low level
H: High level
Figure 2 LS Pins and Address Assignment
1019
HD66520T
Power Supply Pins
VCC1–2 and GND1–2: These pins supply power to the logic circuit.
VCC1–2 and VEE1–2: These pins supply power to the liquid crystal circuits.
V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R: These pins are used to input the level power supply to
drive the liquid crystal.
Bus Interface
(Input): A basic signal of the RAM area. When &6 is low (active), the system can access the on-chip
RAM of the LSI whose address space, set by LS0, LS1, and SHL pins, contains the input address. When
&6 is high, it is prohibited to access the RAM.
&6
In addition, this signal is used for arbitration control when draw access from the CPU competes with
display access that is used to transfer line data to the liquid crystal panel. Note that there are restraints for
the pulse width, as shown in Figure 3. The example shown here is when VCC = 3V for a write operation.
A0 to A15 (Input): A bus to transfer addresses during RAM access. Upper nine bits (A15 to A7) are
duty-direction addresses, and lower seven bits (A6 to A0) are output pin-direction addresses.
(Input): When :( is during low level, the RAM is in active mode, and during high level, it is
prohibited to access the RAM. This is used to write display data to the RAM. Only the LSI whose address
space, set by pins LS0, LS1, and SHL, contains the input address can be written to when &6 is low.
:(
(Input): When 2( is during low level the RAM is in active mode, and during high level, it is
prohibited to access the RAM. This is used to read display data from the RAM. Only the LSI whose
address space, set by pins LS0, LS1, and SHL, contains the input address can be read from when &6 is
low.
2(
DB0 to DB7 (Input/Output): The pins function as data input/output pins. They can accommodate to a
data format with 2 bits/pixel, which implement packed-pixel four-level grayscale display.
180 ≤ tCHW (ns)
180 ≤ tCLW ≤ tFS – 1000 (ns)
tCHW: CS high-level width
tCLW: CS low-level width
tCLW
tCHW
CS
FLM
tFS
CL1
Note: Refer to restraints for details on pulse-width restraints.
Figure 3
1020
(Input)
&6
HD66520T
Block Diagram
SHL
LS1, LS0
Address
management
circuit
Bidirectional
buffer
DB7 to DB0
FLM
CS
WE
OE
Data line decoder
Line
counter
Timing
control
circuit
Word line decoder
A15 to A0
I/O selector
RAM
160 × 240 × 2 bits
FRC control circuit
Data latch circuit (1)
CL1
M
V4L, V3L
V2L, V1L
Data latch circuit (2)
DISPOFF
V4R, V3R,
V2R, V1R
LCD drive circuit
Y1 Y2 Y3
Y160
Figure 4 Block Diagram
1021
HD66520T
Address Management Circuit: Converts the addresses input via A15–A0 from the system to the
addresses for a memory map of the on-chip RAM. When several LSIs (HD66520s) are used, only the LSI
whose address space, set by pins LS0, LS1, and SHL, contains the input address, accepts the access from
the system, and enables the inside. The address management circuit enables configuration of the LCD
display system with memory addresses not affected by the connection direction, and reduces burdens of
software and hardware in the system. Refer to the How to Use the LS1 and LS0 Pins to set pins LS0,
LS1, and SHL.
Timing Control Circuit: This circuit controls arbitration between display access and draw access.
Specifically, it controls access timing while receiving signals FLM, CL1, &6, :(, and 2( as input. FLM
and CL1 are used to perform refresh (display access), that is, to transfer line data to the liquid crystal
circuit. &6, :(, and 2( are used for the CPU to perform draw operation (draw access), that is, to read
and write display data from and to the internal RAM. This circuit also generates a timing signal for the
FRC control circuit to implement four-level grayscale display.
Line Counter: Operates refresh functions. When FLM is high, the counter clears the count value and
generates an address to select the first line in the RAM section. The counter increments its value
whenever CL1 is valid and generates an address to select subsequent lines in the RAM section.
Bidirectional Buffer: Controls the transfer direction of the display data according to signals from pins
:( and 2( in draw operation from the system.
Word Line Decoder: Decodes duty addresses (A15 to A7) and selects one of 240 lines in the display
RAM section, and activates one-line memory cells in the display RAM section.
Data Line Decoder: Decodes pin addresses (A6 to A0) and selects a data line in the display RAM
section for the 7-bit memory cells in one-line memory cells activated by the word line decoder.
I/O Selector: Reads and writes 8-bit display data for the memory cells in the RAM section.
Display RAM: 160 × 240 × 2-bit memory cell array. Since the memory is static, display data can be held
without refresh operation during power supply.
FRC Circuit: Implements FRC (frame rate control) function for four-level grayscale display. For details,
refer to Half Tone Display.
Data Latch Circuit (1): Latches 160-pixel grayscale display data processed by the FRC control circuit
after being read from the display RAM section by refresh operation. This circuit is needed to arbitrate
between display access for performing liquid crystal display and draw access from the CPU.
Data Latch Circuit (2): This circuit again outputs the data in data latch circuit (1) synchronously with
signal CL1.
LCD Drive Circuit: Selects one of LCD select/deselect power levels V4R to V1R and V4L to V1L
according to the grayscale display data, AC signal M, and display-off signal ',632)). The circuit is
configured with 160 circuits each generating LCD voltage to turn on/off the display.
1022
HD66520T
Configuration of Display Data Bit
Packed Pixel Method
For grayscale display, multiple bits are needed for one pixel. In the HD66520, two bits are assigned to
one pixel, enabling a four-level grayscale display.
One address (eight bits) specifies four pixels, and pixel bits 0 and 1 are managed as consecutive bits.
When grayscale display data is manipulated in bit units, one memory access is sufficient, which enables
smooth high-speed data rewriting.
The bit data to input to pin DB7, DB5, DB3, and DB1 becomes MSB and the bit data to input via pin
DB6, DB4, DB2, and DB0 is LSB.
4 pixels/address
Address: n
Bit 0 1 2 3 4 5 6 7
0 0 1 0 0 1 1 1
Address: n + 1
Address: n + 2
0 1 2 3 4 5 6 7
0 0 0 0 0 1 0 1
0 1 2 3 4 5 6 7
1 0 1 0 1 1 1 1
Physical memory
FRC control circuit
0
1
2
3
0
0
2
2
1
1
3
3
Grayscale level
LCD display state
Note: Black is shown when the LCD select high-level power supply V1 (M = 1) and LCD select
low-level power V2 (M = 0) are selected. White is shown when the LCD non-select
high-level power supply V3 (M = 1) and LCD non-select low-level power supply V4 (M = 0)
are selected.
Figure 5 Packed Pixel System
1023
HD66520T
Half Tone Display (FRC: Frame Rate Control Function)
The HD66520 incorporates an FRC function to display four-level grayscale half tone.
The FRC function utilizes liquid crystal characteristics whose brightness is changed by an effective value
of applied voltage. Different voltages are applied to each frame and half brightness is expressed in
addition to display on/off.
Since the HD66520 has two-bit grayscale data per one pixel, it can display four-level grayscale and
improve user interface (Figure 6). Figure 7 shows the relationships between voltage patterns applied to
each frame, the effective voltage value, and brightness obtained.
Edit
a) Display with two values
Edit
b) Display with four values
Figure 6 Example of User Interface Improvement
1024
HD66520T
Applied voltage pattern
1st frame
2nd frame
3rd frame
Effective voltage
White (0, 0)
(Vrm0)
Light gray
(0, 1)
(Vrm1)
Dark gray
(1, 0)
(Vrm2)
Black (1, 1)
(Vrm3)
V1 (M = 1)
V2 (M = 0)
V3 (M = 1)
V4 (M = 0)
Brightness
White
Light gray
Dark gray
Black
Vrm0 Vrm1 Vrm2
Vrm3
Effective voltage
Effective voltage and Brightness
Note: Black is shown when the LCD select high-level power supply V1 (M = 1) and LCD select
low-level power V2 (M = 0) are selected. White is shown when the LCD non-select
high-level power supply V3 (M = 1) and LCD non-select low-level power supply V4 (M = 0)
are selected.
Figure 7 Effective Voltage Values vs. Brightness
1025
HD66520T
Address Management
The HD66520 has an address management function that corresponds to three display sizes all of which
are standard sizes for portable information devices: a 160-dot-wide by 240-dot-long display (small
information devices); a 320-dot-wide by 240-dot-long display (quarter VGA size); and a 320-dot-wide by
480-dot-long display (half VGA size). Up to four HD66520s can be connected to at a time to configure
easily liquid crystal displays with the resolutions mentioned above.
Driver Layout and Address Management
The Y lines on a liquid crystal panel and memory data in a driver are inverted horizontally depending on
the connection side of the liquid crystal panel and the driver. When several drivers are connected, address
management is needed for each driver. Although reinverted bit-map plotting or address management by
the &6 pin in each driver are possible by using special write addressing, the load on the software is
significantly increased. To avoid this, the HD66520 provides memory addresses independent of
connection side, but responds to the setting of pins LS0, LS1, and SHL.
How to Use the LS1 and LS0 Pins
Pins LS1 and LS0 set the LSI position (up to four) as shown in Figure 8 by assigning ID numbers 0 to 3
to each HD66520.
LS0
ID No.
Address Arrangement
L
L
0
Upper-left side
L
H
1
Lower-left side
H
L
2
Upper-right side
H
H
3
Lower-right side
L: Low level
H: High level
HD66503
LS1
HD66503
ID = 0
HD66520
ID = 2
HD66520
320
480
LCD panel
HD66520
ID = 1
HD66520
ID = 3
Figure 8 LS0 and LS1 Pin Setting and Internal Memory Map
1026
HD66520T
How to Use the SHL Pin
It is possible to invert the relationship between the addresses and output pins Y1 to Y160 by setting the
SHL pin (Figure 9). The upper left section on the screen can be assigned to address H’0000 regardless of
which side of the LCD panel the HD66520 is connected to.
The Relationship between the Data Bus and Output Pins
The 8-bit data on the data bus has a 2-bit/pixel configuration for a 4-level grayscale display. In addition,
the 8-bit data on the data bus has a relationship as shown in table regardless of the relationship between
pins LS0, LS1, and SHL.
Table 1
Data Bus and Output Pins
Output Pins
DB 0, 1
Y1
Y5
·········
Y153
Y157
DB 2, 3
Y2
Y6
·········
Y154
Y158
DB 4, 5
Y3
Y7
·········
Y155
Y159
DB 6, 7
Y4
Y8
·········
Y156
Y160
HD66520
HD66520
Y160
Y1 Y160 Y1
320
320
HD66503
HD66520
HD66520
Y160 Y1
Y160
Y1
HD66503
480
HD66503
HD66503
Data Bus
LCD panel
Y160
Y1 Y160
HD66520
Y1
HD66520
When the HD66520 is connected to the
back of the panel (SHL = Low).
480
LCD panel
Y160 Y1
Y160
Y1
HD66520
HD66520
When the HD66520 is connected to the
front of the panel (SHL = High).
Figure 9 Address Assignment and SHL Pin Setting
1027
HD66520T
Since the relationship between data bus pins DB0 to DB7 and the output pins are fixed, connect the data
from the CPU to data bus pins DB0 to DB7 according to the driver arrangement on the panel as shown in
Figure 10.
Drive Arrangement
Data Bus Connection
When Y1 is placed on the left side of the liquid
crystal panel
CPU data
HD66520
Y1
Y160
Liquid crystal
panel
D0
D1
D2
D3
D4
D5
D6
D7
HD66520 data
bus pin
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
When Y160 is placed on the left side of the
liquid crystal panel
CPU data
HD66520
Y160
Y1
Liquid crystal
panel
D0
D1
D2
D3
D4
D5
D6
D7
HD66520 data
bus pin
DB6
DB7
DB4
DB5
DB2
DB3
DB0
DB1
Figure 10 Relationship between Data Bus Pins DB0 to DB7 and Output Pins
1028
HD66520T
Application Example
The HD66520 is suitable for a 160-dot-wide by 240-dot-long display (small information devices); a 320dot-wide by 240-dot-long display (quarter VGA size); and a 320-dot-wide by 480-dot-long display (half
VGA size). All of these are standard sizes for portable information devices. The following shows the
system configuration.
Quarter VGA size
320-dot-wide by 240-dot-long
HD66520
160
160
160
160
240
Expands
horizontally
HD66503
240
Line scan direction
HD66520
240
HD66520
240
320
Expands
horizontally
and vertically
Half VGA size
320-dot-wide by 480-dot-long
HD66520
Line scan direction
160
HD66520
160
240
HD66503
160
480
240
Line scan direction
HD66520
HD66503
Line scan direction
HD66503
Small-size information device
160-dot-wide by 240-dot-long
160
HD66520
320
Figure 11 Application Examples
1029
HD66520T
Small Information Device (SHL = Low)
ID No. 0
LS0 = Low
LS1 = Low
L1
L2
L3
HD66520
Y1
Y160
0000 0001
0080 0081
0100 0101
0026 0027
00A6 00A7
0126 0127
Scan direction
240
L238
L239
L240
240
HD66503
160
7680
7700
7780
Y1
Y4
7681
7701
7781
Y5
Y8
76A6 76A7
7726 7727
77A6 77A7
Y153 Y157
Y156 Y160
Liquid crystal
panel
160
CPU
D0
D1
D2
D3
D4
D5
D6
D7
HD66520
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
Display memory
0
0
0
0
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
Y157 Y159
Y158 Y160
Liquid crystal
display image
Figure 12 Small Information Device (1)
1030
Duty direction
1
1
1
1
HD66520T
Small Information Device (SHL = High)
ID No. 0
LS0 = Low
LS1 = Low
L1
L2
L3
HD66520
Y160
Y1
0000 0001
0080 0081
0100 0101
0026 0027
00A6 00A7
0126 0127
7680 7681
7700 7701
7780 7781
Y157 Y153
Y160 Y156
76A6 76A7
7726 7727
77A6 77A7
Y5
Y1
Y8
Y4
Scan direction
240
L238
L239
L240
240
HD66503
160
Liquid crystal
panel
160
CPU
HD66520
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
Display memory
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
1
Y159 Y157 Y155 Y153
Y160 Y158 Y156 Y154
Y4 Y3 Y2 Y1
Liquid crystal
display image
Duty direction
D1
D0
D3
D2
D5
D4
D7
D6
Figure 13 Small Information Device (2)
1031
HD66520T
Quarter VGA Size (SHL = Low)
L1
L2
L3
L238
L239
L240
0000 0001
0080 0081
0100 0101
7680
7700
7780
Y1
Y4
L1
L2
L3
0026 0027
00A6 00A7
0126 0127
7681
7701
7781
Y5
Y8
76A6 76A7
7726 7727
77A6 77A7
Y153 Y157
Y156 Y160
ID No. 0
LS0 = Low
LS1 = Low
L238
L239
L240
004E 004F
00CE 00OF
014E 014F
76A8
7728
77A8
Y1
Y4
76CE 76CF
774E 774F
77CE 77CF
Y153 Y157
Y156 Y160
76A9
7729
77A9
Y5
Y8
ID No. 2
LS0 = Low
LS1 = High
HD66520
HD66520
Y160 Y1
Y1
Y160
160
240
240
Scan direction
160
HD66503
0028 0029
00A8 00A9
0128 0129
Liquid crystal
panel
320
Figure 14 Quarter VGA Size (1)
1032
HD66520T
CPU
HD66520
HD66520
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Display
memory
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
Y1 Y2 Y3 Y4
Duty direction
D0
D1
D2
D3
D4
D5
D6
D7
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
Display
memory
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
Y157 Y159
Y1 Y2 Y3 Y4
Y158 Y160
Y157 Y159
Y158 Y160
Liquid crystal
display image
Figure 15 Quarter VGA Size (2)
1033
HD66520T
Quarter VGA Size (SHL = High)
L1
L2
L3
0000 0001
0080 0081
0100 0101
L238
L239
L240
7680 7681
7700 7701
7780 7781
Y157 Y153
Y160 Y156
0026 0027
00A6 00A7
0126 0127
76A6 76A7
7726 7727
77A6 77A7
Y5
Y1
Y8
Y4
ID No. 0
LS0 = Low
LS1 = Low
HD66520
Y160
L1
L2
L3
0028 0029
00A8 00A9
0128 0129
004E 004F
00CE 00CF
014E 014F
L238
L239
L240
76A8 76A9
7728 7729
77A8 77A9
Y157 Y153
Y160 Y156
76CE 76CF
774E 774F
77CE 77CF
Y1
Y5
Y4
Y8
ID No. 2
LS0 = Low
LS1 = High
HD66520
Y1 Y160
Y1
240
Scan direction
160
240
HD66503
160
Liquid crystal
panel
320
Figure 16 Quarter VGA Size (3)
1034
HD66520T
CPU
HD66520
HD66520
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
Display
memory
Y159 Y157
Y160 Y158
Duty direction
D1
D0
D3
D2
D5
D4
D7
D6
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
Display
memory
Y4 Y3 Y2 Y1
Y159 Y157
Y160 Y158
Y4 Y3 Y2 Y1
Liquid crystal
display image
Figure 17 Quarter VGA Size (4)
1035
HD66520T
Half VGA Size (SHL = Low)
L1
L2
L3
L238
L239
L240
0000 0001
0080 0081
0100 0101
7680
7700
7780
Y1
Y4
L1
L2
L3
0026 0027
00A6 00A7
0126 0127
7681
7701
7781
Y5
Y8
76A6 76A7
7726 7727
77A6 77A7
Y153 Y157
Y156 Y160
L238
L239
L240
ID No. 0
LS0 = Low
LS1 = Low
480
Scan direction
Y160
160
240
Scan direction
76CE 76CF
774E 774F
77CE 77CF
Y153 Y157
Y156 Y160
Y1
160
HD66503
76A9
7729
77A9
Y5
Y8
HD66520
Y160
HD66503
76A8
7728
77A8
Y1
Y4
004E 004F
00CE 00CF
014E 014F
ID No. 2
LS0 = Low
LS1 = High
HD66520
Y1
0028 0029
00A8 00A9
0128 0129
160
Liquid crystal
panel
160
Y160
HD66520
ID No. 1
LS0 = High
LS1 = Low
L1
L2
L3
L238
L239
L240
240
320
Y1 Y160
HD66520
Y1
ID No. 3
LS0 = High
LS1 = High
Y157 Y153
Y160 Y156
7800 7801
7880 7881
7900 7901
Y5
Y1
Y8
Y4
7826 7827
78A6 78A7
7926 7927
L1
L2
L3
Y157 Y153
Y160 Y156
7828 7829
78A8 78A9
7928 7929
Y5
Y1
Y8
Y4
784E 784F
78CE 78CF
794E 794F
EE80 EE81
EF00 EF01
EF80 EF81
EEA6 EEA7
EF26 EF27
EFA6 EFA7
L238
L239
L240
EEA8 EEA9
EF28 EF29
EFA8 EFA9
EECE EECF
EF4E EF4F
EFCE EFCF
Figure 18 Half VGA Size (1)
1036
HD66520T
CPU
D0
D1
D2
D3
D4
D5
D6
D7
HD66520
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Display
memory
HD66520
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
Display
memory
Y157 Y159
Y1 Y2 Y3 Y4
Y158 Y160
Duty direction
Y1 Y2 Y3 Y4
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
Y157 Y159
Y158 Y160
Duty direction
Liquid crystal
display image
Y159 Y157
Y160 Y158
1
1
1
1
CPU
D6
D7
D4
D5
D2
D3
D0
D1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
Y4 Y3 Y2 Y1
Display
memory
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
Y159 Y157
Y160 Y158
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Y4 Y3 Y2 Y1
Display
memory
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
HD66520
HD66520
Figure 19 Half VGA Size (2)
1037
HD66520T
Half VGA Size (SHL = High)
L1
L2
L3
0000 0001
0080 0081
0100 0101
0026 0027
00A6 00A7
0126 0127
L1
L2
L3
L238
L239
L240
7680 7681
7700 7701
7780 7781
Y157 Y153
Y160 Y156
76A6 76A7
7726 7727
77A6 77A7
Y5
Y1
Y8
Y4
L238
L239
L240
ID No. 0
LS0 = Low
LS1 = Low
HD66520
Scan direction
Scan direction
76A8 76A9
7728 7729
77A8 77A9
Y157 Y153
Y160 Y156
76CE 76CF
774E 774F
77CE 77CF
Y5
Y1
Y8
Y4
ID No. 2
LS0 = Low
LS1 = High
HD66520
Y1 Y160
160
Y1
160
480
HD66503
004E 004F
00CE 00CF
014E 014F
240
HD66503
Y160
0028 0029
00A8 00A9
0128 0129
240
320
160
Liquid crystal
panel
Y160
Y1
ID No. 1
LS0 = High
LS1 = Low
Y1
160
Y1
Y160
ID No. 3
LS0 = High
LS1 = High
Y5
Y4
Y8
7800 7801
7880 7881
7900 7901
Y153 Y157
Y156 Y160
7826 7827
78A6 78A7
7926 7927
Y1
L1
L2
L3
L1
L2
L3
Y5
Y4
Y8
7828 7829
78A8 78A9
7928 7929
Y153 Y157
Y156 Y160
784E 784F
78CE 78CF
794E 794F
L238
L239
L240
EE80 EE81
EF00 EF01
EF80 EF81
EEA6 EEA7
EF26 EF27
EFA6 EFA7
L238
L239
L240
EEA8 EEA9
EF28 EF29
EFA8 EFA9
EECE EECF
EF4E EF4F
EFCE EFCF
Figure 20 Half VGA Size (3)
1038
HD66520T
CPU
D1
D0
D3
D2
D5
D4
D7
D6
HD66520
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Display
memory
Y159 Y157
Y160 Y158
HD66520
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
01
01
01
01
Duty direction
Y4 Y3 Y2 Y1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
Display
memory
Y159 Y157
Y160 Y158
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
Y4 Y3 Y2 Y1
Duty direction
Liquid crystal
display image
Y157 Y159
Y1 Y2 Y3 Y4
Y158 Y160
Y1 Y2 Y3 Y4
0
0
0
0
CPU
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
Display
memory
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Y157 Y159
Y158 Y160
Display
memory
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HD66520
HD66520
Figure 21 Half VGA Size (4)
1039
HD66520T
Display-Data Transfer
Display RAM data is transferred to 160-bit data latch circuits 1 and 2 at each falling edge of the CL1
clock pulse. Since display data transfer and RAM access to draw data are completely synchronousseparated in the LSI, there will be no draw data loss or display flickering due to display data transfer
timing.
The first line data transfer involves the first line marker (FLM), which initializes a line counter, and
transfers the first line data to data latch circuits 1 and 2. Subsequent line data transfers involve
transferring the second and the subsequent line data to data latch circuits 1 and 2 while incrementing the
line counter value.
First Line Data Transfer
The line counter is initialized synchronously with an FLM signal. The first line is transferred to data latch
circuits 1 and 2 at the falling edge of the CL1 (Figure 22).
Subsequent Line Data Transfer
The second and the subsequent line data are transferred to data latch circuits 1 and 2 at the falling edge of
the CL1 to update the line counter value (Figure 23).
CL1
FLM
Line counter
Data latch circuit 1
Data latch circuit 2
(Y1 to Y160)
X+1
1
Xth + 1 line
2
1st line
Xth line
2nd line
1st line
Figure 22 First Line Data Transfer
CL1
Line counter
n
n+1
Data latch circuit 1
nth line
nth + 1 line
Data latch circuit 2
(Y1 to Y160)
nth – 1 line
nth line
Note: Outputs Y1 to Y160 are converted into four levels before output according the liquid crystal altemating signal.
Figure 23 Subsequent Line Data Transfer
1040
HD66520T
Draw Access
Random Cycle
Random cycle sequence is the same as that for the general-purpose SRAM interface (Figures 24 and 25).
It can easily be connected to a CPU address bus and data bus.
A15 to 0
CS
OE
WE
DB7 to 0 out
Valid Dout
DB7 to 0 in
Figure 24 Read Cycle
A15 to 0
CS
OE
WE
DB7 to 0 out
DB7 to 0 in
Valid Din
Figure 25 Write Cycle
1041
HD66520T
Burst Cycle
Continuous access (burst cycle) can be performed by enabling addresses and
(Figures 26 and 27). Refer to restraints for the period of continuous transfer.
2(
A15 to 0
CS
OE
WE
DB7 to 0 out
Valid Dout
Valid Dout
Valid Dout
DB7 to 0 in
Figure 26 Burst Read Cycle
A15 to 0
CS
OE
WE
DB7 to 0 out
DB7 to 0 in
Valid Din
Valid Din
Figure 27 Burst Write Cycle
1042
Valid Din
or
:(
when
&6
is low
HD66520T
Arbitration Control
The HD66520 controls the arbitration between draw access and display access. The draw access reads
and writes display data of the display memory incorporated in the HD66520. The display access outputs
display memory line data to the liquid crystal panel. In this case, draw access is performed before display
access, so continuous access is enabled without having the system to wait. For arbitration control, draw
access is recognized as valid when signal &6 is low.
The following describes the typical examples of display memory access state during arbitration control.
Sequence Line Data Transfer Display Access Performed by Subsequent Line Data Transfer
If no draw access is attempted, normal display access is performed when signal CL1 is low (Figure 28).
Draw Access 1
If draw access is attempted when signal CL1 is high, draw access is performed regardless of the display
access (Figure 29).
CS
CL1
Display memory
access state
nth line data
display access
nth + 1 line data
display access
Figure 28 Sequence Line Data Transfer
Draw access
CS
CL1
Display memory
access state
nth line data
display access
Draw access
nth + 1 line data
display access
Figure 29 Draw Access (1)
1043
HD66520T
Draw Access 2
If draw access is attempted when signal CL1 is low, the display access is suspended to perform draw
access (Figure 30). After the draw access, the display access is performed again. As a result, even if draw
access is attempted asynchronously, at least one of the display accesses will be performed.
Display Access by First Line Data Transfer
If no draw access is attempted, display access for the first line is performed when signal FLM is high and
CL1 is low. The display access for the second line is performed when signal CL1 is low (Figure 31).
Draw access
CS
CL1
Display memory
access state
nth line data
display access
Draw access
nth line data
display access
nth + 1 line data
display access
Figure 30 Draw Access (2)
CS
FLM
CL1
Display memory
access state
1st line data
display access
2nd line data
display access
Figure 31 First Line Data Transfer
1044
HD66520T
Draw Access 3
If draw access is attempted when signal FLM is high, stop the display access is suspended to perform the
draw access (Figure 32). After the draw access, the display access is performed again. As a result, even if
draw access is attempted asynchronously, at least one of the two display accesses will be performed.
Note: In order to satisfy draw access 3 and transfer the first line data, there are restraints for the period
when pins FLM and CL1 are both high and for the low level pulse width of pin &6. Refer to
Restraints for details on the restraints for the pulse width.
CS
Draw access
FLM
CL1
Display memory
access state
Draw access
1st line data
display access
2nd line data
display access
1st line data
display access
Figure 32 Draw Access (3)
1045
HD66520T
Example of System Configuration
Figure 33 shows a system configuration for a 320-dot-wide by 240-dot-long LCD panel using HD66520s
and common driver HD66503 with internal liquid crystal display timing control circuits. All required
functions can be prepared for liquid crystal display with just three chips except for liquid crystal display
power supply circuit functions.
/3
/8
/ 16
CS, WE, OE
DB0–DB7
A15–A0
/
Power supply
circuit
DOC (DISPOFF) 1
/
FLM, CL1, M 3
VCC
LS0
LS1
SHL
HD66520
(ID No.0)
HD66520
(ID No.2)
C
160
240
Line scan direction
R
1/240 duty
CR
HD66503
Scan driver
160
320
Figure 33 System Configuration
1046
LS0
LS1
SHL
HD66520T
Restraints
The HD66520 can perform continuous draw access (burst access) when signal
display data can be rewritten at high speed.
&6
is low. As a result,
However, since signal &6 is necessary to perform arbitration control between draw access and display
access to the display memory, the following restraints exist for the pulse width of signal &6.
VCC = 3.0 to 4.5V
• Read operation
Item
Symbol
Min
Max
Unit
Chip select high level width
tCHR
180
—
ns
Chip select low level width
tCLR
240
tFS – 1000
ns
Item
Symbol
Min
Max
Unit
Chip select high level width
tCHW
180
—
ns
Chip select low level width
tCLW
180
tFS – 1000
ns
• Write operation
VCC = 4.5 to 5.5V
• Read operation
Item
Symbol
Min
Max
Unit
Chip select high level width
tCHR
120
—
ns
Chip select low level width
tCLR
180
tFS – 1000
ns
Item
Symbol
Min
Max
Unit
Chip select high level width
tCHW
120
—
ns
Chip select low level width
tCLW
120
tFS – 1000
ns
• Write operation
1047
HD66520T
Chip Select High Level Width
Display access is performed when signal &6 is high during normal draw access. Therefore, only the
minimum display access time is necessary for the chip select high level width (Figure 34).
tCHR (tCHW)
CS
CL1
Display memory
access state
Draw
access
Display
access
Draw
access
Figure 34 Chip Select High Level Width
1048
HD66520T
Chip Select Low Level Width
When continuous draw access (burst access) is performed when signal &6 is low, the maximum display
access time, that is, tFS–1000 (ns) is necessary for the chip select low level width (Figure 35). This is
needed to secure the display access period for the first line.
When common driver HD66503 is used together with the HD66520, tFS can be calculated with the
following formula.
tFS =
1
4·nDUTY·fFLM
fFLM: frame frequency
nDUTY: duty
When write operation is performed with the burst access having a frame frequency of 70 Hz and a duty
cycle of 1/240, display data of 77 bytes can be consequtively written in one burst access (write cycle is
180 ns).
tCLR (tCLW)
CS
FLM
tFS
CL1
Display memory
access state
1
1st line data
display access
Draw access
2
2nd line data access
2nd line data
display access
Figure 35 Chip Select Low Level Width
1049
HD66520T
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Notes
Logic circuit
VCC
–0.3 to +7.0
V
1
LCD drive circuit
VEE
VCC – 30.0 to VCC + 0.3
V
Input voltage (1)
VT1
–0.3 to VCC + 0.3
V
1, 2
Input voltage (2)
VT2
VEE – 0.3 to VCC + 0.3
V
1, 3
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Power voltage
Notes: 1. The reference point is GND (0V).
2. Applies to pins LS0, LS1, SHL, FLM, CL1, M, A0 to A15, DB0 to DB7, ',632)), &6, :(, and
2(.
3. Applies to pins V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R.
4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It
should always be used within the limits of its electrical characteristics in order to prevent
malfunction or unreliability.
1050
HD66520T
Electrical Characteristics
DC Characteristics 1 (VCC = 3.0 to 5.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
Applicable
Pins
Min
Typ
Max
Unit
Measurement
Condition
–2.5
—
2.5
µA
VIN = VCC to GND
IIL2
V1L/R, V2L/R, –25
V3L/R, V4L/R
—
25
µA
VIN = VCC to VEE
Tri-state
leakage
current
IIST
DB0 to DB7
–10
—
10
µA
VIN = VCC to GND
Vi-Yj on
resistance
RON
Y1 to Y160
—
1.0
2.0
kΩ
ION = 100 µA
Item
Symbol
Input leakage
current (1)
IIL1
Except for
DB0 to DB7
Input leakage
current (2)
1
1. Indicates the resistance between one pin from Y1 to Y160 and another pin from V1L/V1R,
V2L/V2R, V3L/V3R, V4L/V4R when load current is applied to the Y pin; defined under the
following conditions:
VCC–VEE = 28V
V1L/V1R, V3L/V3R = VCC – 2/10 (VCC–VEE)
V4L/V4R, V2L/V2R = VEE + 2/10 (VCC–VEE)
V1L/V1R and V3L/V3R should be near the VCC level, and V2L/V2R and V4L/V4R should be near
the VEE level. All voltage must be within ÆV. ÆV is the range within which RON, the LCD drive
circuits’ output impedance, is stable. Note that ÆV depends on power supply voltage V CC–VEE.
VCC
V1L/R
∆V
∆V (V)
Note:
Notes
V3L/R
6.4
2.5
∆V
V4L/R
V2L/R
VEE
8
28
VCC–VEE (V)
Relationship between Driver Output Waveform and Output Voltage
1051
HD66520T
DC Characteristics 2 (VCC = 3.0 to 4.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
Item
Symbol
Input high level VIH1
voltage (1)
Applicable
Pins
Min
Unit
—
VCC
V
0
—
0.2 × VCC
V
0.7 × VCC
—
VCC
V
0
—
0.15 × VCC
V
0.9 × VCC
—
—
V
IOH = –50 µA
—
—
0.1 × VCC
V
IOL = 50 µA
10
mA
Access time
600 ns
VCC = 3.3V
2
VCC–VEE = 28V
VCC = 3.3V
tCYC = 59.5 µs
No access
2, 3
LS0–1, SHL, 0.8 × VCC
FLM, CL1, M,
Input low level VIL1
voltage (1)
',632))
Input high level VIH2
voltage (2)
DB0 to DB7,
CS, A0 to
A15,
Input low level VIL2
voltage (2)
:(2(
Output high
level voltage
VOH
DB0 to DB7
Output low
level voltage
VOL
Current
consumption
during RAM
access
ICC
Measurement —
pin VCC
8
Current
IEE
consumption in
LCD drive part
Measurement —
pin VEE
200 300
µA
Current
consumption
during display
operation
Measurement —
pin GND
40
µA
IDIS
Measurement
Condition
Typ Max
60
Notes
Notes: 2. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to
VCC and GND levels, respectively.
3. Indicates the current when the memory access is stopped and the still image of a zig-zag
pattern is displayed in its place.
1052
HD66520T
DC Characteristics 3 (VCC = 4.5 to 5.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
Item
Symbol
Input high level VIH1
voltage (1)
Applicable
Pins
Min
LS0–1, SHL, 0.8 × VCC
FLM, CL1, M,
Typ Max
Measurement
Unit Condition
—
VCC
V
Notes
',632))
0
—
0.2 × VCC
V
DB0 to DB7,
, A0 to
A15,
2.2
—
VCC
V
Input low level VIL2
voltage (2)
:(2(
0
—
0.8
V
Output high
level voltage
VOH
DB0 to DB7
2.4
—
—
V
IOH = –100 µA
Output low
level voltage
VOL
—
—
0.4
V
IOL = 100 µA
Current
consumption
during RAM
access
ICC
Measurement —
pin VCC
13
16
mA
Access time
600 ns
VCC = 5.5V
Current
IEE
consumption in
LCD drive part
Measurement —
pin VEE
200 300
µA
2, 3
VCC–VEE = 28V,
VCC = 5.5V,
tCYC = 59.5 µs, no
access
Current
consumption
during display
operation
GND
60
µA
Input low level VIL1
voltage (1)
Input high level VIH2
voltage (2)
IDIS
&6
—
100
2
Notes: 2. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to
VCC and GND levels, respectively.
3. Indicates the current when the memory access is stopped and the still image of a zig-zag
pattern is displayed in its place.
1053
HD66520T
AC Characteristics 1 (VCC = 3.0 to 5.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
• Display-Data Transfer Timing
No.
Item
Symbol
Applicable Pins Min
Max
Unit
Notes
(1)
Clock cycle time
tCYC
CL1
10
—
µs
1
(2)
CL1 high-level width
tCWH
CL1
1.0
—
µs
(3)
CL1 low-level width
tCWL
CL1
1.0
—
µs
(4)
CL1 rise time
tr
CL1
—
50
ns
(5)
CL1 fall time
tf
CL1
—
50
ns
(6)
FLM setup time
tFS
FLM, CL1
2.0
—
µs
(7)
FLM hold time
tFH
FLM, CL1
1.0
—
µs
Notes: 1.
(4) tr
CL1
(2) tCWH
(3) tCWL
fCYC = 1/tCYC
Max: 100 kHz
(1) tCYC
0.8 VCC
0.2 VCC
(6) tFS
FLM
(5) tf
(7) tFH
0.8 VCC
When executing draw access with burst transfer, the period described in the restrains must be
satisfied in the relationship with the arbitration control.
1054
HD66520T
AC Characteristics 2 (VCC = 3.0 to 4.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
• Draw Access Timing
 Read Cycle
Measurement conditions:
Input level:
VIH = 2.4V, VIL = 0.8V
Output level:
VOH/VOL = 1.5V
Output load:
1 TTL gate + 100 pF capacitor
No.
Item
Symbol
Min
Max
Unit
(8)
Read cycle time
tRC
240
—
ns
(9)
Address access time
tAA
—
240
ns
(10)
Chip select access time
tCA
—
240
ns
(11)
&6
high level width
tCHR
180
—
ns
(12)
&6
low level width
tCLR
240
tFS–1000
ns
(13)
2(
delay time
tOE
—
150
ns
(14)
2(
delay time (low impedance)
tOLZ
5
—
ns
(15)
Output-disable delay time
tOHZ
0
35
ns
(16)
Output hold time
tOH
5
—
ns
Note
 Write Cycle
Measurement conditions:
Input level: VIH = 2.4V, VIL = 0.8V
No.
Item
Symbol
Min
Max
Unit
(17)
Write cycle time
tWC
180
—
ns
(18)
Address-to-:( setup time
tASW
30
—
ns
(19)
&6
high level width
tCHW
180
—
ns
(20)
&6
low level width
tCLW
180
tFS–1000
ns
(21)
Address-to-:( hold time
(22)
&6
(23)
tAHW
0
—
ns
-to-:( hold time
tCH
0
—
ns
:(
low level width
tWLW
100
—
ns
(24)
:(
high level width
tWHW
30
—
ns
(25)
Data-to-:( setup time
tDS
80
—
ns
(26)
Data-to-:( hold time
tDH
30
—
ns
Note
1055
HD66520T
AC Characteristics 3 (VCC = 4.5 to 5.5V, GND = 0V, VCC–VEE = 8 to 28V, Ta = –20 to +75°C)
• Access Timing
 Read Cycle
Regulation terms:
Input level:
VIH = 2.4V, VIL = 0.8V
Output judge-level:
VOH/VOL = 1.5V
Output load:
1 TTL gate + capa. 100 pF
No.
Item
Symbol
Min
Max
Unit
(8)
Read cycle time
tRC
180
—
ns
(9)
Address access time
tAA
—
180
ns
(10)
Chip select access time
tCA
—
180
ns
(11)
&6
high level width
tCHR
120
—
ns
(12)
&6
low level width
tCLR
180
tFS–1000
ns
(13)
2(
delay time
tOE
—
100
ns
(14)
2(
delay time (low impedance)
tOLZ
5
—
ns
(15)
Output-disable delay time
tOHZ
0
35
ns
(16)
Output hold time
tOH
5
—
ns
Note
 Write Cycle
Regulation terms:
Input level:
VIH = 2.4V, VIL = 0.8V
No.
Item
Symbol
Min
Max
Unit
(17)
Write cycle time
tWC
120
—
ns
(18)
Address-to-:( setup time
tASW
20
—
ns
(19)
&6
high level width
tCHW
120
—
ns
(20)
&6
low level width
tCLW
120
tFS–1000
ns
(21)
Address-to-:( hold time
(22)
&6
(23)
tAHW
0
—
ns
-to-:( hold time
tCH
0
—
ns
:(
low level width
tWLW
80
—
ns
(24)
:(
high level width
tWHW
30
—
ns
(25)
Data-to-:( setup time
tDS
60
—
ns
(26)
Data-to-:( hold time
tDH
20
—
ns
1056
Note
HD66520T
Read Cycle 1
(8) tRC
Address
(9) tAA
CS
WE
(13) tOE
OE
(15) tOHZ
(16) tOH
(14) tOLZ
I/O out
Valid Data
Read Cycle 2
Address
(12) tCLR
CS
(11) tCHR
(10) tCA
(9) tAA
WE
(13) tOE
OE
(15) tOHZ
(14) tOLZ
DB out
(16) tOH
Valid Data
1057
HD66520T
Write Cycle 1
(17) tWC
Address
(18) tASW
(21) tAHW
CS
(24) tWHW
(23) tWLW
WE
OE
(25) tDS
I/O in
(26) tDH
Valid Data
Write Cycle 2
(17) tWC
Address
(20) tCLW
(19) tCHW
(22) tCH
CS
(18) tASW
(23) tWLW
(24) tWHW
WE
OE
(25) tDS
I/O in
1058
(26) tDH
Valid Data