HM6208H Series 65,536-word × 4-bit High Speed CMOS Static RAM Features • Single 5 V supply and high density 24-pin package • High speed: Access time 25/35/45 ns (max) • Low power Operation: 300 mW (typ) Standby: 100 µW (typ) 30 µW (typ) (L-version) • Completely static memory required No clock or timing strobe required • Equal access and cycle time • Directly TTL compatible: All inputs and outputs • Battery backup operation capability (L-version) Ordering Information Type No. Access Time Package HM6208HP-25 HM6208HP-35 HM6208HP-45 25 ns 35 ns 45 ns 300-mil, 24-pin plastic DIP (DP-24NC) HM6208HLP-25 HM6208HLP-35 HM6208HLP-45 25 ns 35 ns 45 ns HM6208HJP-25 HM6208HJP-35 HM6208HJP-45 25 ns 35 ns 45 ns HM6208HLJP-25 HM6208HLJP-35 HM6208HLJP-45 25 ns 35 ns 45 ns 300-mil, 24-pin SOJ (CP-24D) HM6208H Series Pin Arrangement A0 1 24 VCC A1 2 23 A15 A2 3 22 A14 A3 4 21 A13 A4 5 20 A12 A5 6 19 A11 A6 7 18 A10 A7 8 17 I/O1 A8 9 16 I/O2 A9 10 15 I/O3 CS 11 14 I/O4 VSS 12 13 WE (Top view) Pin Description Pin Name Function A0–A15 Address I/O1–I/O4 lnput/output CS Chip select WE Write enable VCC Power supply VSS Ground 2 HM6208H Series Block Diagram A14 A15 A0 A1 A2 A3 A4 A5 VCC Memory array 256 × 1024 Row decoder I/O1 Column I/O Input data control I/O2 I/O3 VSS Column decoder I/O4 A13 A12 A11 A10 A9 A8 A7 A6 CS WE Truth Table CS WE Mode VCC Current I/O Pin Ref. Cycle H × Not selected I SB , I SB1 High-Z — L H Read I CC Dout Read cycle L L Write I CC Din Write cycle Note: ×: Don’t care. Absolute Maximum Ratings Parameter Symbol Value *1 Unit Voltage on any pin relative to V SS Vin –0.5 to +7.0 V Power dissipation PT 1.0 W Operating temperature range Topr 0 to +70 °C Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –10 to +85 °C Note: 1. Vin min = –2.5 V for pulse widths ≤ 10 ns. 3 HM6208H Series Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 — 6.0 V — 0.8 V Input high (logic 1) voltage Input low (logic 0) voltage Note: VIL –0.5 *1 1. VIL min = –2.0 V for pulse width ≤ 10 ns. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM6208H-25 *2 HM6208H-35/45 Parameter Symbol Min Typ Max Min Typ*2 Max Unit Test Conditions Input leakage current I LI — — 2.0 — — 2.0 Output leakage current I LO — — 10.0 — — 10.0 µA CS = VIH, VIO = VSS to V CC Operating power supply current I CC — 60 120 — 50 100 mA CS = VIL, I I/O = 0 mA, min cycle, duty = 100% I CC1 — 40 80 — 40 80 mA CS = VIL, II/O = 0 mA, t cycle = 50 ns, duty = 100% Standby power supply current I SB — 20 40 — 15 30 mA CS = VIH, min cycle Standby power supply current I SB1 (1) — 0.02 2.0 — 0.02 2.0 I SB1*1 — 0.006 0.1 *1 — 0.006 0.1 *1 Output low voltage VOL — — 0.4 — — 0.4 V I OL = 8 mA Output high voltage VOH 2.4 — — 2.4 — — V I OH = –4.0 mA µA VCC = Max Vin = VSS to V CC CS ≥ V CC – 0.2 V, 0 V ≤ Vin < 0.2 V, or Vin ≥ V CC – 0.2 V Notes: 1. L-version 2. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. Capacitance (Ta = 25°C, f = 1 MHz)*1 Parameter Symbol Min Max Unit Test Conditions Input capacitance Cin — 6 pF Vin = 0 V Input/output capacitance CI/O — 11 pF VI/O = 0 V Note: 4 1. These parameters are sampled and not 100% tested. HM6208H Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted) Test Conditions • • • • Input pulse levels: V SS to 3.0 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figure Output Load +5V +5V 480 Ω Dout 255 Ω 480 Ω Dout 255 Ω 30 pF *1 Output load (A) 5 pF *1 Output load (B) (tHZ, tLZ, tWZ, and tOW) Note: 1. Including scope and jig Read Cycle HM6208H-25 HM6208H-35 HM6208H-45 Parameter Symbol Min Max Min Max Min Max Unit Read cycle time t RC 25 — 35 — 45 — ns Address access time t AA — 25 — 35 — 45 ns Chip select access time t ACS — 25 — 35 — 45 ns Output hold from address change t OH Chip selection to output in low-Z t LZ 5 — 5 — 5 — ns *1 5 — 5 — 5 — ns *1 0 15 0 20 0 20 ns Chip deselection to output in high-Z t HZ Chip selection to power up time t PU 0 — 0 — 0 — ns Chip deselection to power down time t PD — 15 — 25 — 30 ns Note: 1. Transition is measured ±200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 5 HM6208H Series Read Timing Waveform (1) tRC Address tAA tOH tOH Valid Data Dout Notes: 1. WE is high for read cycle. 2. Device is continuously selected. Read Timing Waveform (2) tRC CS tHZ tACS tLZ Dout VCC supply current ICC Valid Data High impedance tPU tPD 50% 50% ISB Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with the CS transition to low. 6 High impedance HM6208H Series Write Cycle HM6208H-25 HM6208H-35 HM6208H-45 Parameter Symbol Min Max Min Max Min Max Unit Write cycle time t WC 25 — 35 — 45 — ns Chip selection to end of write t CW 20 — 30 — 40 — ns Address valid to end of write t AW 20 — 30 — 40 — ns Address setup time t AS 0 — 0 — 0 — ns Write pulse width t WP 20 — 25 — 30 — ns Write recovery time t WR 3 — 3 — 3 — ns Data valid to end of write t DW 15 — 20 — 20 — ns Data hold time t DH Write enabled to output in high-Z Output active from end of write Note: t WZ 0 — 0 — 0 — ns *1 0 8 0 10 0 15 ns *1 0 — 0 — 0 — ns t OW 1. Transition is measured ± 200 mV from high impedance voltage with load (B). These parameters are sampled and not 100% tested. 7 HM6208H Series Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS tWR *2 tWP *1 WE tDW Valid Data Din tWZ *3 Dout tDH *4 tOH *5 tOW *4 High impedance Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. During this period, I/O pins are in the output state. The input signals of the opposite phase to the outputs must not be applied. 4. If CS is low during this period, I/O pins are in the output state. The data input signals of opposite phase to the outputs must not be applied to them. 5. Dout is the same phase of write data of this write cycle. 8 HM6208H Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tWR *2 tAS tCW CS tWP *1 WE tDW Din tDH Valid Data High impedance *3 Dout Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high-impedance state. 9 HM6208H Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) These characteristics are guaranteed for the L-version only. Parameter Symbol Min Typ Max Unit Test Conditions VCC for data retention VDR 2.0 — — V CS ≥ V CC – 0.2 V, Vin ≥ V CC – 0.2 V, or 0 V ≤ Vin < 0.2 V,or Data retention current I CCDR — 2 50*1 µA Chip deselect to data retention time t CDR 0 — — ns Operation recovery time 5 — — ms Note: tR 1. VCC = 3.0 V Low V CC Data Retention Timing Waveform Data retention mode VCC 4.5 V tCDR tR 2.2 V VDR CS ≥ VCC – 0.2 V CS 0V 10 HM6208H Series Package Dimensions HM6208HP/HLP Series (DP-24NC) Unit: mm 29.88 30.48 Max 1 7.40 Max 13 7.10 24 12 1.14 1.30 7.62 0.48 ± 0.10 2.54 Min 2.54 ± 0.25 0.51 Min 5.08 Max 1.27 Max + 0.11 0.25 – 0.05 0° – 15° HM6208HJP/HLJP Series (CP-24D) Unit: mm 15.63 16.00 Max 7.62 ± 0.13 0.43 ± 0.10 1.27 0.80 1.30 Max 0.21 2.40 +– 0.24 12 +0.25 –0.17 0.74 3.50 ± 0.26 1 8.64 ± 0.13 13 24 + 0.35 6.76 – 0.16 0.10 11