OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. Change Summary CHANGES No. 1 Applicable Section Title 2 Ordering Information 3 General Description Functional Block Diagram Description Reference Application Circuit Package information Throughout data sheet 4 5 6 7 Description Change the title to read ‘Phase-Shift PWM Controller’ Add OZ964GN, OZ964IG, OZ964IGN, OZ964D & OZ964DN st Add 1 paragraph ‘OZ964 is a high…LCD.’ st Page(s) 1 1 1 st Add 1 paragraph 1 sentence ‘Specific DC/CD…’ 5 Add DC/DC Reference Application Circuit 10 Correct 20 Pin SOIC 300mil drawing Miscellaneous corrections 12 --- REVISION HISTORY Revision No. 0.95 0.96 1.0 1.1 Description of change Initial Release 1. Ordering information: add OZ964SN & OZ964ISN. 2. Pin Description: modified pin description of CTIMR, DIM. 3. Electrical Characteristics: revise a) ‘Nominal Voltage’ Typ limit, b) ‘Normal Operating Frequency’ Typ limit, c) ‘Ramp Peak’ Typ limit, d) ‘Operating Frequency’ Typ limit, e) ‘Negative-Going Threshold Voltage’ Max limit, f) ‘SST Current’ Typ limit, g) ‘CTIMR Current 1’ Typ limit, h) ‘Protection Release Threshold’ Typ limit, i) ‘PDR_A/ PDR_C’ Typ`limit, j) ‘Enable’ Min limit, k) ‘NDR_B/ NDR_D’ Typ limit, l) ‘BBM Time Between PDR and NDR’ Typ limit, m) ‘Minimum Overlap’ Typ limit. 4. Simplified Functional Block Diagram. 5. Modified formula in No. 4 Ignition & No. 5 Normal Operation in Functional Information. 6. Revise Application Circuit. 7. Miscellaneous corrections. 1. Electrical Characteristics: a) Fill in Min & Max limits of all parameters b) Correct ‘SST Protection Release Threshold’ Typ limit. 2. Application Circuit: Correct a) C10 to 6.8n, b) T1 to 28:2200. 3. Miscellaneous corrections. 1. Footer: Add patent number 6,259,615 2. Application circuit: a.) Delete R3, R7, R6 & R11. b) Change R9 value from 45.3k to 47K 09/03/04 Copyright 2004 by O2Micro OZ964-DS-1.2 All Rights Reserved Release Date 1/13/2004 3/19/2004 4/5/2004 7/29/2004 Page 0 U.S. Patent No. 6,259,615 CONFIDENTIAL OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. Phase-Shift PWM Controller FEATURES • • • • • • • • • • • • Controller for high-voltage DC/DC and DC/AC converters High efficiency, zero-voltage switching Supports wide input voltage range Constant operating frequency Built-in PWM dimming control with wide dimming range Soft start function Built-in intelligence for ignition and normal operation of CCFLs Built-in open-lamp protection and overvoltage protection Shutdown delay for input voltage brownout condition Built-in under-voltage lockout protection Toggle pin to reset the IC after shutdown Low stand-by power ORDERING INFORMATION Part Number OZ964S Temp Range 0° C to 70° C OZ964SN 0° C to 70° C OZ964IS -40° C to +85°C OZ964ISN -40° C to +85°C OZ964G 0° C to 70° C OZ964GN 0° C to 70° C OZ964IG -40° C to +85°C OZ964IGN -40° C to +85°C OZ964D 0° C to 70° C OZ964DN 0° C to 70° C Package 20-pin SSOP 20-pin SSOP, Leadfree 20-pin SSOP 20-pin SSOP, Leadfree 20-pin SOIC 20-pin SOIC, Leadfree 20-pin SOIC 20-pin SOIC, Leadfree 20-pin PDIP 20-pin PDIP, Leadfree GENERAL DESCRIPTION OZ964 is a high efficiency, Pulse Width Modulation (PWM) controller designed for both DC/DC and DC/AC high-voltage applications. The average current mode control is suitable for DC/DC converters where both voltage and current feedback are required, as well as for Cold Cathode Fluorescent Lamp (CCFL)_ backlight applications for small and large Liquid Crystal Displays (LCD). 09/03/04 Copyright 2004 by O2Micro OZ964 operates in a zero-voltage switching mode that minimizes electromagnetic interference (EMI). In addition, OZ964 achieves a high power-conversion efficiency resulting in a lower operating temperature and higher system reliability. OZ964 supports a wide input voltage range and provides a constant, user-defined, operating frequency, ensuring that the CCFLs operate at a fixed frequency. This eliminates interference among CCFLs and the LCD panel. Interference causes electromagnetic compatibility (EMC) problems and may create visual effects (waterfall) on LCD panels. The controller provides a phase-shift square wave output that is able to drive a full bridge power train. OZ964 utilizes a pulse width modulation (PWM) dimming method to achieve a wide dimming range. The IC performs the CCFL dimming function with an analog or low frequency PWM control. The PWM frequency is user-defined. To avoid over-shoot and in-rush current to the CCFLs during ignition, a soft start function is provided for reliable CCFL operation. The controller provides open-lamp protection and over-voltage protection, while providing an appropriate response for either open-lamp ignition or removal of a CCFL during normal operation. Intelligent open-lamp protection and over voltage protection provides design flexibility with various transformer characteristics. Openlamp protection time is user-defined. In addition, OZ964 provides a shutdown delay function that will keep the inverter module in normal operation for a short period of time if the input voltage suddenly drops and subsequently resumes to a normal level. The shutdown delay time is user-defined. OZ964 provides under-voltage lockout protection and will disable the IC if VDDA falls below a threshold. OZ964 will resume normal operation when VDDA exceeds the threshold. To reset the IC, toggle the enable (ENA) pin. OZ964 operates with a standby current of approximately 200uA. OZ964-DS-1.2 All Rights Reserved Page 1 U.S. Patent No. 6,259,615 CONFIDENTIAL OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. PIN DESCRIPTION Names Pin No. CTIMR 1 OVP ENA SST VDDA GNDA REF RT1 FB CMP NDR_D PDR_C LPWM DIM LCT PGND RT CT PDR_A NDR_B 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description Timing capacitor to provide striking time and timing resistor to provide shutdown delay time Voltage feedback Enable input Timing capacitor to provide Soft-Start Time Supply voltage Signal ground Reference voltage output Timing resistor to provide striking frequency Current sense feedback Voltage control loop compensation N-MOSFET gate drive output P-MOSFET gate drive output Low-frequency PWM signal for dimming control DC voltage input for LPWM duty cycle Timing capacitor to provide LPWM frequency Power MOSFET driver ground Timing resistor to provide striking and operating frequency Timing capacitor to provide striking and operating frequency P-MOSFET gate drive output N-MOSFET gate drive output ABSOLUTE MAXIMUM RATINGS(1) VDDA GNDA, PGND Signal inputs Operating Temp. 7.0V +/- 0.3V -0.3V to (VDDA +0.3)V OZ964 0oC to 70oC Operating junction temp. Storage temp. OZ964I -40oC to +85oC 125 oC -55 C to 150 oC o RECOMMENDED OPERATING RANGE VDDA fOP- operating frequency Resistor connected to RT (RRT) Capacitor connected to CT (CCT) fLF- LPWM frequency Thermal Impedance (θJ-A) 20-pin SSOP 20-pin SOIC 4.6V to 5.5V 40 kHz to 150kHz(2) 20 kΩ to 150 kΩ 100pF to 470pF 100Hz to 500Hz o 80 C/W o 105 C/W Note (1): The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The “Functional Specifications” table will define the conditions for actual device operation. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note (2): The frequency of PDR_A, NDR_B, PDR_C, and NDR_D outputs pulses, fOP, is half of fosc value, fOP =(fosc/2). CONFIDENTIAL OZ964-DS-1.2 Page 2 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. ELECTRICAL CHARACTERISTICS Parameter Symbol Test Conditions Limits o VDDA=5V; Tamb=25 C; Unit Min Typ Max Iload = 30µA 3.22 3.35 3.48 V Temp coefficient o (Tamb=25 C) - 125 - ppm/ C Reference Voltage Nominal voltage Vref o Line regulation KL VDDA=4.6V to 5.5V - 2 - mV/V Load regulation KV Iload = 5 µA to 80 µA - 2 - mV fop CCT =220pF ; 61.5 63.0 65.5 kHz - 125 - ppm/ C Operating Frequency Normal Operating Frequency (1) (1) RRT =47kΩ Temp coefficient o (Tamb=25 C) o Ramp peak CT Vpeak 2.35 2.50 2.65 V Ramp valley CT Vvalley 1.00 1.05 1.12 V CLCT=6.8nF(2); VDIM=1.2V 209 220 225 Hz Temp coefficient o (Tamb=25 C) - 470 - ppm/ C V Low Frequency Oscillator Operating frequency fLF o Ramp peak LCT Vpeak 1.96 2.06 2.18 Ramp valley LCT Vvalley 0.27 0.31 0.33 V LPWM 0 - 100 % VSST=0V 0.49 0.50 0.55 V VSST=2V 0.79 0.80 0.81 V VSST=4V 1.19 1.24 1.29 V Positive-Going Threshold Voltage 4.3 - - V Negative-Going Threshold Voltage - - 3.2 V - 200 300 µA - 3.0 4.2 mA 4.5 5.5 6.2 µA - 420 - ppm/ C VDDA -1.25 VDDA -1.0 VDDA -0.93 V 2.0 2.5 2.9 µA - 395 - ppm/ C CTIMR current 2 20 30 40 µA Protection release threshold 2.9 3.1 3.3 V Duty Cycle Range Error Amplifier Reference voltage at non- VADJ inverting input pin (internal) Under-Voltage Lockout Supply Stand-by Current IOFF ENA=low Supply Current ION DIM=1.2V; LPWM=50kΩ Ca=Cb=Cc=Cd=0.5nF (3) (1) CCT =220pF , (1) RRT =47kΩ (2) ;CLCT=6.8nF Soft Start SST current Temp coefficient o (Tamb=25 C) SST Protection Release Threshold o CTIMR CTIMR current 1 Temp coefficient o (Tamb=25 C) CONFIDENTIAL OZ964-DS-1.2 o Page 3 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter Symbol Test Conditions o VDDA=5V; Tamb=25 C; Limits Unit Min Typ Max Output Driver Rds(on) PDR_A / PDR_C Sourcing=75mA 12 25 35 Ω NDR_B / NDR_D Sinking=75mA 13 25 36 Ω Enable 2.3 - - V Disable - - 1.0 V 1.95 2.00 2.20 V 2.54 2.70 2.82 V 150 200 220 ns - 495 - ppm/ C 91 95 - % - 2.5 3.9 % Enable Thresholds Over-Voltage Protection Threshold Voltage OVP Open-Lamp Protection Threshold Open-Lamp Threshold CMP> open-lamp threshold causes shutdown Break-Before-Make (BBM) BBM Time Between PDR and NDR Temp coefficient o (Tamb=25 C) o Maximum / Minimum Duty Cycle Maximum Overlap Vsst = 3.75V ; Vcmp = 3.24V Minimum Overlap Vsst = 0.8V ; Vcmp = 3.5V (1) Note CCT: capacitor from ”CT” (Pin 18) to ground RRT: resistor from “RT” (Pin 17) to ground (2) Note CLCT: capacitor from “LCT” (Pin 15) to ground (3) Note Ca: capacitor from PDR_A (Pin 19) to VDDA Cb: capacitor from NDR_B (Pin 20) to ground Cc: capacitor from PDR_C (Pin 12) to VDDA Cd: capacitor from NDR_D (Pin 11) to ground CONFIDENTIAL OZ964-DS-1.2 Page 4 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. FUNCTIONAL BLOCK DIAGRAM DESCRIPTION Specific DC/DC applications can be shown with a Reference Application Circuit in Figure 3, page 10. The following discussions will address the OZ964 driving a DC/AC CCFL application. Refer to the Functional Block Diagram in Figure 1, page 6 and the Reference Application Circuit in Figure 2 , page 9. The drive circuit consists of four outputs, PDR_A, NDR_B, PDR_C and NDR_D, (pins 19, 20, 12 and 11) respectively. The drive circuit is designed to achieve high efficiency, zero-voltage switching operation. The four power MOSFET gate output drives, PDR_A, NDR_B, PDR_C and NDR_D are designed such that switches QA/QB and QC/QD never turn-on simultaneously. The configuration prevents any shoot-through issues associated with bridge-type power conversion applications. CCFL current regulation is achieved by adjusting the overlap conduction between diagonal switches QA/QD and QB/QC. The overlap is adjusted when the power source voltage varies. The Protection Block intelligently monitors and differentiates the striking condition and openlamp condition. The open-lamp protection function disables the drive circuit if a fault condition is encountered. The Reference Block provides a precision reference voltage for both internal and external uses. The LPWM Generator Block provides a low frequency PWM (LPWM) function that provides wide dimming control for the CCFLs. The LPWM frequency is user-defined by connecting an external capacitor to LCT (pin 15). An analog voltage at DIM (pin 14) is compared with the LCT waveform that yields a LPWM signal to control the power delivered to the CCFLs. OZ964 is enabled with a voltage greater than 2V applied to ENA (pin 3). A voltage of less than 1V to ENA pin will disable the controller. Toggling ENA (pin 3) from High-Low-High will reset the controller. A current source of 30uA coupled with an external capacitor and external resistor connected to pin 1 controls the shutdown delay time. The shutdown delay time will keep the inverter module in normal operation for a short period of time if the input voltage suddenly drops and subsequently increases to a normal level. The shutdown delay time is user-defined. The Under-Voltage Lockout block provides a brown-out period during which the output signals are disabled while the VDDA voltage drops below a ~3.4V threshold. OZ964 resumes normal operation once VDDA voltage reaches a voltage threshold of greater than ~4.3V. Soft-start circuitry provides a gradual increase in power to the drive circuit to power the CCFLs during the ignition period. The Soft-Start Time (SST) is user-defined by an external capacitor connected to SST (pin 4) coupled with an SST current source of 5.5uA. A High Frequency Oscillator Block generates a user-defined operating frequency determined by an external capacitor (C5) and timing resistor (R9) connected to CT (pin 18) and RT (pin 17) respectively. An external resistor (R10) connected to RT1 (pin 8) in parallel with RT determines the striking frequency. The current control loop monitors CCFL current that is sensed with a voltage at FB (pin 9). The voltage at FB (pin 9) is input to an Error Amplifier and the output, CMP (pin 10), regulates the CCFL current. OZ964 provides an Over-Voltage Protection (OVP) function to safely operate the CCFLs under all conditions. The OVP Block regulates the striking voltage for the CCFL during start-up. The striking time is user-defined and determined by an external capacitor connected to CTIMR (pin 1) coupled with the CTIMR current source of 2.6uA. CONFIDENTIAL OZ964-DS-1.2 Page 5 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. FUNCTIONAL BLOCK DIAGRAM 1 20 Fault Protection Logic 2 19 3 18 ZVS Phase Shift Driver 4 5 17 16 V-REF I-BIAS 6 15 + - 7 Control Logic 8 9 14 13 12 + 11 10 Figure 1 CONFIDENTIAL OZ964-DS-1.2 Page 6 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. FUNCTIONAL INFORMATION 1. Steady-State Operation Referring to the example schematic shown in Figure 2, page 9, OZ964 drives a full-bridge power train where the transformer couples the energy from the power supply source to the CCFL. The switches in the bridge denoted as QA, QB, QC and QD are configured such that the transistors in each pair, QA/QB and QC/QD, are turned-on complementarily. The turn-on duration of the diagonal switches, QA/QD and QB/QC, simultaneously determines the amount of energy delivered to the transformer and subsequently to the CCFL. The current in the CCFL is sensed and regulated by adjusting the turn-on time (overlap) for both diagonal switches. This is accomplished through an error amplifier in the current feedback loop. A voltage loop is used to regulate the output voltage for CCFL ignition and is programmable by using a capacitor divider (C8/C13). Over Voltage Protection (OVP) limits the transformer voltage under an open-lamp condition. A soft-start circuit ensures a gradual increase in power to the CCFL. The soft-start capacitor (C9) determines the rate of rise of the voltage on the SST pin. Meanwhile, the voltage level determines the turn-on time of the diagonal switches QA/QD and QB/QC. The output drives for the power MOSFET gates include PDR_A, NDR_B, PDR_C and NDR_D that output a complementary square pulse. The operation of the four switches is implemented with zero-voltage switching that provides a highefficiency power conversion. 2. Enable OZ964 is enabled when the voltage on ENA (pin 3) is greater than 2V. A voltage of less than 1V disables the IC. When the inverter controller is disabled, it draws approximately 200uA. An under-voltage lockout protection feature is provided that will disable the IC if VDDA voltage drops below an ~3.4V threshold. The IC will resume normal operation once VDDA reaches a threshold voltage of greater than ~4.3V. the voltage at ENA (pin 3) is greater than 2V. The soft-start time is determined by an external capacitor (C9) connected to the SST (pin 4). At start-up, as C9 charges via a charging current, the voltage level at the capacitor controls the gradual increase in power delivered to the transformer T1. 4. Ignition The OZ964 provides an option of selecting a different frequency for striking the CCFLs. The striking time is user-defined and determined by an external capacitor CCTIMR (C6) and external resistor RCTIMR (R5) connected to CTIMR (pin 1). The approximate striking time is determined by the following equation. T[second] = CCTIMR[µF] x (3-(RCTIMR[kΩ] x 0.0026)) 2.6 The approximate striking frequency is determined by the following equation. 65•10 4 fstriking[kHz] = CCT[pF]•(RRT // RRT1) [kΩ] Note: RRT // RRT1 means RRT is in parallel with RRT.1. 5. Normal Operation Once the IC is enabled, the voltage at SST (pin 4) controls the rate of power delivered to the load. SST voltage increases to a level such that the CCFLs are ignited. The striking frequency is determined by external components R10, R9 and C5 connected to RT1 (pin 8), RT (pin 17) and CT (pin 18) respectively. Once the external resistor R16 senses sufficient current, the control loop takes control and regulates the CCFL current. The normal operating frequency is determined by the combination of external resistor R9 and external capacitor C5. The operating frequency is approximated by the following equation. 65•10 4 fop[kHz] = 3. Soft-Start CCT[pF]•RRT[kΩ] To avoid component stresses and in-rush current to the CCFLs during ignition, a soft start function is implemented to provide reliable CCFL operation. The soft-start function is initiated when CONFIDENTIAL OZ964-DS-1.2 Page 7 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. 6. Open Lamp Protection If the controller encounters an open lamp, damaged lamp or lamp removal during normal operation, the control loop generates a protection signal and will immediately shutdown the controller. OZ964 provides a shutdown delay feature that keeps the inverter module in normal operation if the input voltage suddenly drops and subsequently recovers. The shutdown delay time is user-defined by external resistor RCTIMR (R5) and external capacitor CCTIMR (C6) connected to CTIMR (pin 1). The shutdown delay time is approximated by the following equation: CCTIMR[µF] x (3 – (RCTIMR [kΩ] * 0.03)) T[second] = 30 7. Over-Voltage Protection & Striking Time During start-up, once the voltage at the transformer secondary reaches a programmed threshold, the control loop takes over and regulates the voltage at the transformer secondary. SST voltage at pin 4 is held constant and CTIMR is activated to provide additional time to ignite an aged CCFL. If no current is sensed after approximately 1 to 2 seconds, the controller shuts down. Toggling the ENA pin will reset the controller. 8. PWM Dimming Control OZ964 provides a low frequency PWM (LPWM) dimming function to perform a wide dimming range of 0% to 100%. The LPWM frequency is determined by external capacitor C10 connected to LCT (pin 15). The frequency is approximated by the following equation. Note: RCTIMR (R5) value equal or greater than 110kΩ will result in zero delay time. Toggling ENA (pin 3) from High-Low-High resets the controller. CONFIDENTIAL 1496 f LF[Hz] = CLCT[nF] The LPWM frequency is user-defined by the selection of external capacitor C10. An analog voltage at DIM (pin 14) is compared with the LCT waveform that yields a LPWM signal to control the power delivered to the CCFLs. The typical peak and valley of the LCT waveform is ~2.06V and ~0.31V respectively. OZ964-DS-1.2 Page 8 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. OZ964 REFERENCE APPLICATION CIRCUIT VIN: 8.0V - 22V VADJ: 2.1V Max. Brightness; 0.6V Min. Brightness Striking frequency: 75.1KHz Operating frequency: 63KHz 5VDC: 4.75V – 5.25V CONFIDENTIAL Figure 2 OZ964-DS-1.2 Page 9 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. OZ964 DC/DC REFERENCE APPLICATION CIRCUIT Figure 3 CONFIDENTIAL OZ964-DS-1.2 Page 10 OZ964 D Detail A h x 45 deg E1 E 1 c ZD A A2 SEATING PLANE B A1 0.10MM C e NOTES: DIMENSION D DOES NOT INCLUDE M OLD PROTRUSIONS OR GATE BURRS M OLD PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED 6 MIL PER SIDE DIM θ2 θ1 Gauge Plane 0.25MM Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. PACKAGE INFORMATION – 20-PIN SSOP 150mil: OZ964S R θ L Detail A CONFIDENTIAL R1 A A1 A2 B c e D E E1 L h ZD R1 R θ θ1 θ2 JEDEC MILLIMETERS NOM MAX MIN MIN 1.35 1.63 1.75 53 0.10 0.15 0.25 4 1.50 0.20 0.30 8 0.18 0.25 7 0.635 BASIC 8.56 8.66 8.74 337 5.79 5.99 6.20 228 3.81 3.91 3.99 150 0.41 0.635 1.27 16 0.25 0.50 10 1.4732 REF 0.20 0.33 8 0.20 8 0° 8° 0° 0° 0° 5° 10° 15° 5° MO-137 (AD) OZ964-DS-1.2 MIL NOM MAX 64 69 6 10 59 12 10 25 BASIC 341 344 236 244 154 157 25 50 20 58 REF 13 8° 10° 15° Page 11 OZ964 b 11 20 D e ta il X H E 1 10 e c A D Y S E A T IN G P L A N E A1 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. PACKAGE INFORMATION – 20-PIN SOIC 300mil: OZ964G NOTES: 1 . R E F E R T O J E D E C S T D . M S -0 1 3 A C . 2 . D IM E N S IO N S " D " D O E S N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S O R G A T E B U R R S . M O L D F L A S H , P R O T R U S IO N S A N D G A T E B U R R S S H A L L N O T E X C E E D 0 .1 5 m m (6 m il) P E R S ID E . 3 . D IM E N S IO N S " E " D O S E N O T IN C L U D E IN T E R L E A D F L A S H O R P R O T U R S IO N S . IN T E R -L E A D F L A S H A N D P R O T R U S IO N S S H A L L N O T E X C E E D 0 .2 5 m m (1 0 m il) P E R S ID E . 4 . C O N T R O L L IN G D IM E N S IO N : M IL L IM E T E R h x 45 O SYMBOL θ L DETAIL "X" CONFIDENTIAL A A1 b c D E e H h L Y θ MILLIMETERS NOM MAX MIN 2.36 2.54 2.64 0.10 0.20 0.30 0.35 0.406 0.48 0.23 0.254 0.31 12.60 12.80 13.00 7.40 7.50 7.60 1.27 BSC 10.00 10.31 10.65 0.25 0.66 0.75 0.51 0.76 1.02 0.075 0° 8° OZ964-DS-1.2 MIN 93 4 14 9 496 291 394 10 20 0° MIL NOM 100 8 16 10 504 295 50 BSC 406 26 30 - MAX 104 12 19 12 512 299 419 30 40 3 8° Page 12 OZ964 Controlled Recipient #101461 printed on 10/25/2004. Updates will be provided to registered recipients. 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Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customer acknowledges that O2Micro products are not designed, manufactured or intended for incorporation into any systems or products intended for use in connection with life support or other hazardous activities or environments in which the failure of the O2Micro products could lead to death, bodily injury, or property or environmental damage (“High Risk Activities”). O2Micro hereby disclaims all warranties, and O2Micro will have no liability to Customer or any third party, relating to the use of O2Micro products in connection with any High Risk Activities. Any support, assistance, recommendation or information (collectively, “Support”) that O2Micro may provide to you (including, without limitation, regarding the design, development or debugging of your circuit board or other application) is provided “AS IS.” O2Micro does not make, and hereby disclaims, any warranties regarding any such Support, including, without limitation, any warranties of merchantability or fitness for a particular purpose, and any warranty that such Support will be accurate or error free or that your circuit board or other application will be operational or functional. O2Micro will have no liability to you under any legal theory in connection with your use of or reliance on such Support. COPYRIGHT © 2004, O2Micro International Limited CONFIDENTIAL OZ964-DS-1.2 Page 13