bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINY™-III) FEATURES • • • • • • • • • • • • • DESCRIPTION Small 3.5 mm × 4.5 mm QFN package Designed for single-cell Li-Ion or Li-Pol based portable applications Integrated dynamic power-path management (DPPM) feature allowing the AC adapter or the USB port to simultaneously power the system and charge the battery Power supplement mode allows battery to supplement the USB or AC input current Autonomous power source selection (AC Adapter or USB) Integrated USB charge control with selectable 100-mA and 500-mA charge rates Dynamic total current management for USB Supports up to 2-A total current 3.3 V Integrated LDO output Thermal regulation for charge control Charge status outputs for LED or system interface indicates charge and fault conditions Reverse current, short-circuit and thermal protection Power Good (AC adapter and USB port present) Status outputs The bqTINY-III series are highly integrated and flexible Li-Ion linear charge and system power path management devices targeted at space limited portable applications. The bqTINY-III series offer integrated USB-port and DC supply (AC adapter) and power-path management with autonomous power-source selection, power FET and current sensor, high accuracy current and voltage regulation, charge status, and charge termination, in a single monolithic device. The bqTINY-III powers the system while independently charging the battery. This features reduces the charge and discharge cycles on the battery, allows for proper charge termination and allows the system to run with an absent or defective battery pack. This feature also allows for system to instantaneously turn on from an external power source in the case of a deeply discharged battery pack. The bqTINY-III automatically selects the USB-Port or the AC-adapter as the power source for the system. In the USB configuration, the host can select from the 2 preset charge rates of 100 mA and 500 mA. The bqTINY-III dynamically adjusts the USB charge rate based on system load to stay within the 100 mA or 500 mA charge rates. In the ac-adapter configuration an external resistor sets the magnitude of the charge current. The AC input can also be programmed using the PSEL pin to perform like a USB input. APPLICATIONS • • • • Smartphones and PDA MP3 players Digital cameras Handheld devices Internet appliances TYPICAL APPLICATION AC Adapter AC OUT VDC USB Port D+ D− VBUS GND System Q1 PACK+ USB 30 mΩ BAT + PACK− GND Q3 Q2 bq2403x UDG−04082 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOSFET gates. ORDERING INFORMATION TA -40°C to 125°C (1) (2) OUTPUT VOLTAGE (V) OUT PIN FOR AC INPUT CONDITIONS PART NUMBER (1) (2) 4.2 Regulated to 6 V bq24030RHLR Preview ANB 4.2 Regulated to 4.4 V bq24032RHLR Released AMZ 4.2 Cut off at 6 V bq24035RHLR Preview ANA STATUS PACKAGE MARKING The RHL package isavailable taped and reeled only in quantities of 3,000 devices perreel. This product is RoHScompatible, including a lead concentration that does not exceed 0.1% of totalproduct weight, and is suitable for use in specified lead-free solderingprocesses. In addition, this product uses package materials that do not containhalogens, including bromine (Br) or antimony (Sb) above 0.1% of total productweight. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) bq24030 bq24032 bq24035 Input voltage AC (DC voltage wrt VSS) -0.3 to 18 Input voltage BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, STAT1, STAT2, TS, USBPG (all DC voltages wrt VSS) -0.3 to 7 LDO (DC voltage wrt VSS) Input current Output current -0.3 to VO(OUT) + 0.3 2.75 A USB 600 mA OUT 4 BAT (2) -4 to 1.75 LDO 30 Output sink current ACPG, STAT1, STAT2, USBPG, 1.5 Storage temperature range, Tstg -65 to 150 Junction temperature range, TJ -40 to 150 (1) (2) 2 V AC Output source current (in regulation at 3.3 V LDO) Lead temperature (solderig, 10 seconds) UNIT A mA °C 300 Stresses beyond thoselisted under "absolute maximum ratings" may cause permanent damage to thedevice. These are stress ratings only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating conditions" is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect device reliability. All voltagevalues are with respect to the network ground terminal unless otherwisenoted. Negative current isdefined as current flowing into the BAT pin. bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 RECOMMENDED OPERATING CONDITIONS MIN MAX (1) (2) 4.35 16.00 (1) 4.35 6.5 VCC Supply voltage (from AC input) VCC Supply voltage (from USB input) IAC Input current, AC IUSB Input current, USB TJ Operating junction temperature range (1) (2) UNIT V 2 A 0.5 -40 °C 125 VCC is defined as the greater of AC or USBinput. Verify that powerdissipation and junction temperatures are within limits at maximum VCC . DISSIPATION RATINGS (1) PACKAGE TA≤ 40°C POWER RATING DERATING FACTOR TA > 40°C θJA 20-pin RHL (1) 1.81 W 21 mW/°C 46.87 °C/W This data is based onusing the JEDEC High-K board and the exposed die pad is connected to a Cu padon the board. This is connected to the ground plane by a 2×3 viamatrix. ELECTRICAL CHARACTERISTICS over junction temperature range (0°C ≤ TJ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENT ICC(SPLY) Active supply current, VCC VVCC > VVCC(min) 1 2 ICC(SLP) Sleep current (current into BAT pin) V(AC) < V(UVLO), V(USB) < V(UVLO), 2.6 V ≤ VI(BAT)≤ VO(BAT-REG), Excludes load on OUT pin 2 5 ICC(AS-STDBY) AC standby current VI(AC)≤ 6V, Total current into AC pin with chip disabled, Excludes all loads, (1) CE=LOW, after t(CE-HOLDOFF) delay 200 USB standby current Total current into USB pin with chip disabled, Excludes all loads, (1)CE=LOW, after t(CE-HOLDOFF) delay 200 ICC(USBSTDBY) ICC(BAT-STDBY) BAT standby current Total current into BAT pin with AC and/or USB present and chip disabled, Excludes all loads, CE=LOW, after t(CE-HOLDOFF) delay (1) 45 60 IIB(BAT) Charge done current, BAT Charge DONE, AC or USB supplying the load 1 5 Output regulation voltage Active only if AC or USB is present, VI(OUT)≥ VO(LDO) + (IO(LDO)× RDS(on)) mA µA LDO OUTPUT VO(LDO) (2)-5% Regulation accuracy IO(LDO) Output current RDS(on) On resistance C(OUT) 3.3 V 5% OUT to LDO Output capacitance 20 mA 50 Ω (3)1 µF OUT TERMINAL AND DPPM MODE VO(OUT-REG) Output regulation voltage V(DPPM-SET) DPPM set point (4) I(DPPM-SET) DPPM current source (1) (2) (3) (4) bq24030 VI(AC)≥ 6 V+VDO bq24032 VI(AC)≥ 4.4 V+VDO 6.0 6.3 4.4 4.5 2.6 AC or USB present 95 V 3.7 100 105 µA This includes thequiescent current for the integrated LDO. In standby mode (CElow) the accuracy is ±10%. LDO output capacitornot required but one with a value of 0.1-µF is recommended. V(DPPM-SET) is scaled up by the scale factor forcontrolling the output voltage V(DPPM-REG). 3 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) over junction temperature range (0°C ≤ TJ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER SF DPPM scale factor TEST CONDITIONS MIN TYP 1.139 1.150 1.162 1.8 2.0 2.2 VI(AC)≥ VCC(min), PSEL=High, II(AC) = 1 A, (IO(OUT)+IO(BAT)) 300 475 VI(USB)≥ VCC(min), PSEL=Low, ISET2 = High II(USB) = 0.4 A, (IO(OUT)+IO(BAT)) 140 180 28 36 V(DPPM-REG)= V(DPPM-SET)× SF DPPM disable set point V(ACDO) V(usbDO) AC to OUT dropout voltage (5) USB to OUT dropout voltage VI(USB)≥ VCC(min), PSEL=Low, ISET2 = Low II(USB) = 0.08 A, (IO(OUT)+IO(BAT)) Enter battery supplement mode (battery supplements OUT current in the presence of input source VI(BAT)> 2 V MAX UNIT VI(OUT)≤ VI(BAT)- 60 mV VI(OUT)≥ VI(BAT)- 20 mV Exit battery supplement mode VI(BAT)> 2 V BAT to OUT short circuit recovery Series resistor between BAT to OUT for short circuit recovery to VI(OUT)≤ VI(BAT) -200mV AC to OUT short circuit limit VI(OUT)≤ 1 V 500 USB to OUT short circuit limit VI(OUT)≤ 1 V 500 10 V mV V mA Ω BATTERY CHARGE VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT)≤ 1 A VO(BAT-REG) Battery charge voltage Battery charge voltage regulation accuracy 4.2 TA = 25°C V --0.5% 0.5% -1% 1% V(DO) BAT to OUT dropout voltage (discharging) VI 3 V, Ii(BAT)= 1.0 A, VCC < Vi(BAT) 30 100 V(DO) USB dropout voltage 3.0 V ≤ VO(BAT) < VO(BAT-REG) , II(BAT) = 1 A, 1 A current source on AC input, VI(DPPM) < 2.2 V 30 100 1000 1500 (BAT)≥ mV CURRENT REGULATION (6) (7) VVCC≥ 4.35 V, Vi (BAT) > V(LOWV), VI(OUT) - VI (BAT) > V(DO-MAX), PSEL = High IOUT(BAT) = (K(SET)× V(SET) / RSET), AC to OUT and USB to OUT short-circuit pull-up VI(OUT) < 1 V V(SET) Battery charge current set voltage (8) Voltage on ISET1, VVCC≥ 4.35 V, VI(OUT)- VI(BAT) > V(DO-MAX), VI(BAT) > V(LOWV) K(SET) Charge current set factor, BAT IO(BAT) (5) (6) (7) (8) (9) 4 AC battery charge current range 100 mA Ω 500 2.475 2.500 2.525 100 mA ≤ IO(BAT)≤ 1 A 400 425 450 10 mA ≤ IO(BAT)≤ 100 mA (9) 300 450 600 V VDO(max), dropout voltage is a function of the FET,RDS(on), and drain current. the dropoutvoltage increases proportionally to the increase in current. When input currentremains below 2 A, the battery charging current may be raised until the thermalregulation limits the charge current. When PSEL is pulledlow, and USBPG is high, the AC inputfunctions as a USB input. For half-chargerate, V(SET) is 1.25 V ± 25mV. Specification is formonitoring charge current via the ISET1 pin during voltage regulation mode, notfor a reduced fast charge level. bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) over junction temperature range (0°C ≤ TJ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER USB input current range TEST CONDITIONS MIN TYP MAX UNIT VVCC(min)≥ 4.35 V, VI(BAT) > V(LOWV), VI(USB) - VI(BAT) > V(DO-MAX), ISET2= Low, PSEL = Low (10) 80 100 VVCC(min)≥ 4.35 V, VI(BAT) > V(LOWV), VI(USB) - VI(BAT) > V(DO-MAX), ISET2= High, PSEL = Low (11) 400 500 mA PRECHARGE and SHORT-CIRCUIT CURRENT REGULATION V(LOWV) Precharge to fast-charge transition Voltage on BAT threshold Deglitch time for fast-charge to precharge transition (12) VVCC(min)≥ 4.5 V, tFALL = 100 ns, 10 mV overdrive, VI(BAT) decreasing below threshold IO(PRECHG) Precharge range 1 V < VI(BAT) < V(LOWV), t < t(PRECHG), IO(PRECHG) = (K(SET)× V(PRECHG))/ RSET V(PRECHG) Precharge set voltage 1 V < VI(BAT) < V(LOWV), t < t(PRECHG) Short circuit pull-up, BAT VI(BAT)≤ 1 V 2.9 3.0 3.1 22.5 10 230 250 V ms 150 mA 270 mV 1 kΩ CHARGE TAPER DETECTION I(TAPER) Charge taper detection range VI(BAT) < V(RCH), I(TAPER) = (K(SET)× V(TAPER))/ RSET V(TAPER) Charge taper detection set voltage Voltage on ISET1, VREG(BAT) = 4.2 V, VI(BAT) > V(RCH) Deglitch time for taper detection VVCC(min)≥ 4.5 V, tFALL = 100 ns, 10 mV overdrive, ICHG increasing above or decreasing below threshold 10 235 250 150 mA 265 mV 22.5 ms TEMPERATURE SENSE COMPARATORS VHTF High voltage threshold 2.465 2.500 2.535 VLTF Low voltage threshold 0.485 0.500 0.515 V ITS Temperature sense current source 94 100 106 µA Deglitch time for temperature fault detection (12) VVCC(min)≥ 4.5 V, R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above and below; 100-ns fall time, 10-mv overdrive 22.5 V ms BATTERY RECHARGE THRESHOLD VRCH Recharge threshold voltage Deglitch time for recharge detection (12) VO(BAT- VO(BAT- REG) REG) REG) -0.075 -0.100 -0.125 VVCC(min)≥ 4.5 V, R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing below threshold, 100-ns fall time, 10-mv overdrive VO(BAT- 22.5 V ms STAT1, STAT2. ACPG AND USBPG OUTPUTS VOL Low-level output saturation voltage IOL = 5 mA Input leakage current 1 0.25 V 5 µA ISET2, CE AND PSEL INPUTS VIL Low-level input voltage 0 VIH High-level input voltage 1.4 0.4 V (10) With the PSEL= low,the bqTINY-III defaults to USB charging. If USB input is grounded, then thebqTINY-III charges from the AC input at the USB charge rate. In thisconfiguration the specification is 75 mA (min) and 95 mA (max). (11) With the PSEL= low,the bqTINY-III defaults to USB charging. If USB input is grounded, then thebqTINY-III charges from the AC input at the USB charge rate. In thisconfiguration the specification is 375 mA (min) and 475 mA (max). (12) All deglitch periodsare a function of the timer setting. 5 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) over junction temperature range (0°C ≤ TJ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS IIL Low-level input current, CE or PSEL IIH High-level input current, CE or PSEL IIL Low-level input current, ISET2 VISET2 = 0 V IIH High-level input current, ISET2 VISET2 = VCC t(CE-HLDOFF) Hold off time, CE CE going low only K(TMR) Timer set factor t(CHG) = K(TMR)× R(TMR) R(TMR) External resistor limits MIN TYP MAX UNIT -1 1 µA -20 40 4 6 TIMERS 0.313 0.360 30 0.09 × t(CHG) t(PRECHG) Precharge timer I(FAULT) Timer fault recovery pull-up from OUT to BAT 0.01 × t(CHG) 0.414 s/Ω 100 kΩ 0.11 × t(CHG) 1 s mA CHARGER SLEEP THRESHOLDS V(SLPENT) V(SLPEXIT) t(DEGL) Sleep mode entry threshold V(UVLO)≤ VI(BAT)≤ VO(BAT-REG), No t(BOOT-UP) delay Sleep mode exit threshold V(UVLO)≤ VI(BAT)≤ VO(BAT-REG), No t(BOOT-UP) delay Deglitch time for sleep mode (13) VVCC≤ VI(BAT) +125 mV VVCC≥ VI(BAT) +190 mV R(TMR) = 50 kΩ, V(AC) or V(USB) or decreasing below threshold, 100-ns fall time, 10-mv overdrive 22.5 V ms START-UP CONTROL and USB BOOT-UP t(BOOT-UP) Boot-up time Upon the first application of USB input power or AC input with PSEL low 120 150 180 ms SWIITCHING POWER SOURCE TIMING Switching power source from inputs (AC or USB) to battery After ACPG or USBPG detection, low to high (no (t(BOOT-UP)) delay) or after CE hold off time Switching from AC to USB, or, USB to AC by input source removal. (14) After ACPG or USBPG detection, low to high (no (t(BOOT-UP)) delay) Switching from AC to USB, or USB to AC by toggling PSEL Toggling PSEL High to Low or Low to High 50 100 µs 50 THERMAL SHUTDOWN REGULATION (15) T(SHTDWN) TJ(REG) Temperature trip TJ (Q1 and Q3 only) 155 Thermal hysteresis TJ (Q1 and Q3 only) 30 Temperature regulation limit TJ (Q2) 115 Undervoltage lockout Decreasing VCC 2.45 °C 135 UVLO V(UVLO) Hysteresis 2.50 27 2.65 V mV (13) Doesn’tdeclare sleep mode until after the deglitch time and implement the needed powertransfer immediately according to the switching specification. (14) The power handoff isimplemented once the PG pin goes goeshigh (removed source’s PG) which is when the removed source drops to thebattery voltage. if the battery voltage is critically low the system may loosepower unless the system takes control of the PSEL pin and switches to theavailable power source prior to shutdown. the USB source often has less currentavailable so the system may have to reduce its load when switching from AC toUSB. (15) Reaching thermalregulation reduces the charging current. Battery supplement current is notrestricted by either thermal regulation or shutdown. Input power FETs turn offduring thermal shutdown. The battery FET is only protected by a short circuitlimit which typically doesn't cause a thermal shutdown (input FETs turning off)by itself. 6 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 DEVICE INFORMATION USBPG 19 20 LDO USB bq24030RHL bq 24032RHL, bq24035RHL RHL PACKAGE (BOTTOM VIEW) 1 2 STAT1 3 STAT2 OUT 17 4 AC OUT 16 5 BAT OUT 15 6 BAT TMR 14 7 ISET2 DPPM 13 8 PSEL 9 CE TS 12 11 10 ISET1 18 VSS ACPG TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AC 4 I Charge input voltage from AC adapter ACPG 18 O AC powergood status output (open-drain) BAT 5 I/O BAT 6 I/O CE 9 I Chip enable input (active high) DPPM 13 I Dynamic power path management set point (account for scale factor) ISET1 10 I/O ISET2 7 I Charge current set point for USB port. (High = 500 mA, Low = 100 mA) For bq24032 see half charge current mode using ISET2. LDO 1 O 3.3 V LDO regulator OUT 15 OUT 16 O Output terminal to the system OUT 17 PSEL 8 I Power source selection input (low for USB, High for AC) STAT1 2 O Charge status output 1 (open-drain) STAT2 3 O Charge status output 2 (open-drain) TMR 14 I/O Timer program input TS 12 I/O Temperature sense input USB 20 I USB charge input voltage USBPG 19 O USB powergood status output (open-drain) VSS 11 - Ground input (the thermal pad on the underside of the package) There is an internal electrical connection between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. Battery input and output. Charge current set point for AC input and precharge and taper set point for both AC and USB 7 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 FUNCTIONAL BLOCK DIAGRAM Short Circuit Recovery 500 Ω VO(OUT) USB Charge Enable 100 mA / 500 mA AC Q1 1 kΩ VSET AC Charge Enable 3.3 V LDO LDO Short Circuit Recovery VI(IUSB−SNS) VO(OUT) BAT Short Circuit Recovery 500 Ω + VIO(AC) OUT VO(LDO) Q2 Q3 + VI(BAT) BAT VO(OUT−REG) VI(IUSB−SNS) USB VI(ISET1) ISET1 Reference, Bias & UVLO VI(IUSB−SNS) UVLO VO(BAT−REG) TMR Oscillator VI(BAT) VI(BAT) USB Charge Enable + VO(BAT−REG) VI(ISET1) VO(OUT) DPPM + DPPM I(DPPM) Scaling + Fast Pre-Charge VSET BAT Charge Enable + VOUT TJ V(HTF) + Disable− Sleep 200 mV TS + I(TS) Suspend Thermal Shutdown + VO(OUT) TJ(REG) * 60 mV VI(BAT) + + 1V + 100 mA / 500 mA VSET + * V(LTF) Power Source Selection USB Charge Enable PSEL AC Charge Enable CE BAT Charge Enable VO(BAT−REG) VBAT Recharge * VBAT Precharge Charge Control Timer and Display Logic 500 mA/ 100 mA Fast Pre-Charge 1C − 500 mA C/S − 100 mA ISET2 * ACPG V(SET) VI(ISET1) Taper USBPG * STAT1 VBAT VAC VSS Sleep (AC) * STAT2 Sleep (USB) VBAT VUSB * * Signal Deglitched UDG−04084 UDG−04084 8 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 FUNCTIONAL DESCRIPTIONS CHARGE CONTROL The bqTINY-III supports a precision Li-Ion or Li-Pol charging system suitable for single-cell portable devices. See a typical charge profile, application circuit and an operational flow chart in Figure 1 through Figure 4 respectively. Pre-Conditioning Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase Regulation Voltage Regulation Current Minimum Charge Voltage Charge Voltage Charge Complete Charge Current Pre− Conditioning and Taper Detect UDG−04087 Figure 1. Charge Profile AC Adapter bq24023RHL VDC 4 AC 1 10 µF 10 µF GND LDO OUT 15 10 µF OUT 16 D+ D− VBUS System OUT 17 20 USB 10 µF PACK+ BAT 5 BAT 6 Battery Pack 14 TMR RTMR 1 µF + 7 ISET2 PACK− GND USB Port 2 STAT1 3 STAT2 19 USBPG TEMP TS 12 18 ACPG DPPM 13 9 CE ISET1 10 8 PSEL RSET RDPPM VSS 11 Control and Status Signals UDG−04083 Figure 2. Typical Application Circuit 9 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 FUNCTIONAL DESCRIPTIONS (continued) POR SLEEP MODE Vcc > V I(OUT) checked at all times No Indicate SLEEP MODE Yes V I(OUT) <V (LOWV) Yes Regulate IO(PRECHG) Reset and Start t(PRECHG) timer Indicate Charge− In−Progress No Reset all timers, Start t (CHG) timer Regulate Current or Voltage Indicate Charge− In−Progress No V I(OUT) <V (LOWV) Yes Yes t(PRECHG) Expired? No t(CHG) Expired? Yes No Yes Fault Condition Yes V I(OUT) <V (LOWV) Indicate Fault No VI(OUT) > V (RCH) ? No I(TAPER) detection? No Enable I (FAULT) current Yes No Yes VI(OUT) > V (RCH) ? Turn off charge Yes Yes Indicate DONE Disable I (FAULT) current No VI(OUT) < V (RCH) ? Figure 3. Charge Control Operational Flow Chart 10 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 FUNCTIONAL DESCRIPTIONS (continued) Autononous Power Source Selection Note that the PSEL pin selects the priority of the input sources (High = AC, Low = USB), if that primary source is not available (based on ACPG, USBPG signal), then it uses the secondary source. If neither input source is available, then the battery is selected as the source. With the PSEL input high, the bqTINY-III attempts to charge from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC adapter has the priority. With the PSEL input low, the bqTINY-III defaults to USB charging. If USB input is grounded, then the bqTINY-III charges from the AC input at the USB charge rate (as selected by ISET2). This feature can be used in system where AC and USB power source selection is done elsewhere. The PSEL function is summarized in Table 1. Table 1. Power Source Selection Function Summary PSEL STATE AC CHARGE SOURCE CHARGE RATE SYSTEM POWER SOURCE USB BOOT-UP FEATURE Present (1) Absent AC ISET2 AC Enabled Absent (2) Present USB ISET2 USB Enabled Present Present USB ISET2 USB Enabled Low High (1) (2) USB Absent Absent N/A N/A Battery Disabled Present Absent AC ISET1 AC Disabled Absent Present USB ISET2 USB Disabled Present Present AC ISET1 AC Disabled Absent Absent N/A N/A Battery Disabled Present is defined as input being at ahigher voltage than the BAT voltage. AC Absent is defined as AC input notpresent (sleep mode) or Q1 turned off due to overvoltage inbq24035. Boot-Up Sequence In order to facilitate the system startup and USB enumeration, the bqTINY-III offers a proprietarty boot-up sequence. Upon the first application of power to the bqTINY-III, this feature enables the 100 mA USB charge rate for a period of approximately 150 ms, (t(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of this period, the bqTINY-III implements CE and ISET2 inputs settings. Table 1 indicates when this feature is enabled. Power Path Management The bqTINY-III powers the system while independently charging the battery. This features reduces the charge and discharge cycles on the battery, allows for proper charge termination and allows the system to run with an absent or defective battery pack. This feature gives the system priopirty on input power allowing the system to power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is assumed HIGH for this discussion). AC Adapter AC OUT VDC USB Port D+ D− VBUS GND System Q1 PACK+ USB 30 mΩ BAT + PACK− GND Q3 Q2 bq2403x UDG−04082 Figure 4. Power Path Management 11 bq24030, bq24032, bq24035 SLUS618 – AUGUST 2004 www.ti.com Case 1: AC (PSEL = High) System Power In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see Figure 4). For bq24030, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)). Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035, once the AC voltage goes above 6 V, Q1 turns off. For bq24032, the output is regulated at 4.4 V from the AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the supply, the output voltage drops down to the battery’s voltage. Charge Control When AC is present the battery is charged through switch Q2 based on the charge rate set on the ISET1 input. Dynamic Power Path Management (DPPM) This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting or removal of the input supply. If the voltage on the OUT pin drops to a preset value, VDPPM× SF, due to a limited amount of input current, then the battery charging current is reduced until the output voltage stops dropping. The DPPM control tries and reach a steady state condition where the system gets its needed current and the battery is charged with the remaining current. There is no active control to limit the current to the system. Therefore if the system demands more current than the input can provide, the output voltage drops to the battery voltage and the battery tries and supplement the input current to the system. There are three main advantages of DPPM. 1. This feature allows the designer to select a lower power wall adapter, if the average system load is moderate compared to its peak power. For example if the peak system load is 1.75 A, average system load is 0.5 A and battery fast charge current is 1.25 A, the total peak demand could be 3.0 A. With DPPM a 2-A adaptor could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of 1.25 A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation voltage threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value. 2. There is a power savings using DPPM compared to configurations without DPPM. Without DPPM, if the system current plus charge current exceed the supply’s current limit, then the output is pulled down to the battery. Linear chargers, dissipate the unused power (VIN-VOUT) × ILOAD. The current remains high (at current limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less (VIN-VDPPM-REG) to the system which means better efficiency. The efficiency for charging the battery is the same for both cases. The advantages are less power dissipation, lower system temperature and better overall efficiency. 3. The DPPM’s function is to sustain the system voltage no matter what causes it to drop, if at all possible. It does this by reducing the non-critical charging load while maintaining the maximum power output of the adaptor. Note that the DPPM voltage, V(DPPM), is programmed as follows: V (DPPM) I (DPPM) R(DPPM) SF (1) where • RDPPM is the external resistor connected between the DPPM and VSS pins • I(DPPM) is the internal current source • SF is the scale factor as specified in the specification table The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly proportional to the programmed charging current. When the programmed charging current is reduced, due to DPPM, the ISET1 voltage is reduced and the timer’s clock is proportionally slowed, extending the safety time. 12 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 Case 2: USB (PSEL = Low) System Power In this case, the system load is powered directly from the USB port through the internal switch Q3 (see Figure 5 ). Note in this case Q3 regulates the total current to the 100 mA or 500 mA level, as selected on the ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected regulated limit, then Q3 is fully on and VOUT is approximately (VUSB-VUSB-DO). The system’s power management is responsible for keeping its system load below the USB current level selected (if the battery is critically low or missing), otherwise the output drops to the battery voltage. Therefore, the system should have a low power mode for USB power application. The DPPM feature keeps the output from dropping below its programmed threshold, due to the battery charging current, by reducing the charging current. Charge Control When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin (0.1/0.5A). The charge current to the battery is set by the ISET1 resistor (typically > 0.5A). Since the charge current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage or DPPM voltage, which ever is higher. If the DPPM threshold is reached first, the charge current is reduced as described below. Dynamic Power Path Management (DPPM) The theory of operation is the same as described above, in CASE 1, except that Q3 restricts the amount of input current delivered to the output and battery instead of the input supply. Note that the DPPM voltage, V(DPPM), is programmed as follows: V (DPPM) I (DPPM) R(DPPM) SF (2) where • RDPPM is the external resistor connected between the DPPM and VSS pins • I(DPPM) is the internal current source • SF is the scale factor as specified in the specification table Battery Temperature Monitoring The bqTINY-III continuously monitors battery temperature by measuring the voltage between the TS and VSS pins. An internal current source provides the bias for most-common 10 kΩ negative-temperature coefficient thermistors (NTC) (see Figure 5). The device compares the voltage on the TS pin against the internal V(LTF) and V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected the device immediately suspends the charge. The device suspends charge by turning off the powerFET and holding the timer value (i.e. timers are NOT reset). Charge is resumed when the temperature returns to the normal range. The allowed temperature range for 103AT type thermistor is 0°C to 45°C. However the user may increase the range by adding two external resistors. See Figure 6. PACK+ bqTINYIII TS VLTF HTF PACK− TS NTC 9 LTF + ITS PACK− ITS PACK+ bqTINYIII + LTF BATTERY PACK RT1 TEMP VLTF RT2 HTF VHTF 9 NTC BATTERY PACK VHTF UDG−04086 UDG−04085 Figure 5. TS Pin Configuration Figure 6. TS Pin Thresholds 13 bq24030, bq24032, bq24035 SLUS618 – AUGUST 2004 www.ti.com Battery Pre-Conditioning During a charge cycle if the battery voltage is below the V(LOWV) threshold, the bqTINY-III applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and K(SET)parameters are specified in the specifications table. Note that this applies to both AC and USB charging. V(PRECHG) K(SET) I O (PRECHG) RSET (3) The bqTINY-III activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not reached within the timer period, the bqTINY-III turns off the charger and enunciates FAULT on the STAT1 and STAT2 pins. The timeout is extended if the charge current is reduced by DPPM. Please refer to the Timer Fault Recovery section for additional details. Battery Charge Current The bqTINY-III offers on-chip current regulation with programmable set point. The resistor connected between the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the system priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications table. V(SET) K(SET) I O (OUT) RSET (4) When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed (ISET1) charging current and therefore the DPPM feature attempts to keep the output from being pulled down by reducing the charging current. For the bq24032 the charge level, during AC operation only (PSEL=High), can be changed by a factor of 2 by setting the ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, VSET1, is divided by 2 when in the half constant current charge mode. Note that With PSEL low the ISET2 pin controls only the 0.1 A/0.5 A USB current level. Please also refer to section titled Power Path Management for additional details. Battery Voltage Regulation The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the battery pack. The bqTINY-III monitors the battery-pack voltage between the BAT and VSS pins. When the battery voltage rises to VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper down. As a safety backup, the bqTINY-III also monitors the charge time in the charge mode. If charge is not terminated within this time period, t(CHG), the bqTINY-III turns off the charger and enunciates FAULT on the STAT1 and STAT2 pins. Refer to the DPPM operation under Case 1, for information on extending the safety timer during DPPM operation. Please refer to the Timer Fault Recovery section titled for additional details. Temperature Regulation and Thermal Protection In order to maximize charge rate, the bqTINY-III features a junction temperature regulation loop. If the power dissipation of the IC results in a junction temperature greater than the TJ(REG) threshold, the bqTINY-III throttles back on the charge current in order to maintain a junction temperature around the TJ(REG) threshold. To avoid false termination, the taper detect function is disabled while in this mode. The bqTINY-III also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from AC or USB inputs if TJ exceeds T(SHTDWN). This operation continues until TJ falls below T(SHTDWN) by the hysteresis level specified in the specification table. There is no thermal protection for the battery supplement mode. The Q2 FET continues to connect the battery to the output (system), if input power is not sufficient. However, there is a short circuit protection circuit that limits the battery discharge current such that the maximum power dissipation of the part is not exceeded, under typical design conditions 14 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 Charge Timer Operation As a safety backup, the bqTINY-III monitors the charge time in the charge mode. If taper threshold is not detected within the time period, t(CHG), the bqTINY-III turns off the charger and enunciates FAULT on the STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines the timer period. The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer, eliminate RTMR, connect the TMR pin directly to the LDO pin. Note that this action eliminates all safety timers also clears any timer fault. TMR pin should not be left floating. t (CHG) K(TMR) R(TMR) (5) While in the thermal regulation mode or DPPM mode, the bqTINY-III dynamically adjusts the timer period in order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to prevent against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by the equation Equation 6. t (CHG) V(SET) t (CHGTREG) V (SETREG) (6) Note that since this adjustment is dynamic and changes as the ambient temperature changes and the charge level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted inversely proportionately with the charge current and the battery is a current-hour rating the safety time dynamically adjusts appropriately. The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the thermal regulation mode and is a function of charge current. (Note that charge current is dynamically adjusted during the thermal regulation mode). I (OUT) R(SET) V (SETTREG) K(SET) (7) Charge Taper Detection, Termination and Recharge The bqTINY-III monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER), is detected the bqTINY-III terminates charge. The resistor connected between the ISET1 and VSS, RSET, determines the taper detection level. The V(TAPER) and K(SET)parameters are specified in the specifications table. Note that this applies to both AC and USB charging. V(TAPER) K(SET) I (TAPER) RSET (8) After charge termination, the bqTINY-III re-starts the charge once the voltage on the OUT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. Please see the Battery Absent Detection section for additional details. LDO Register The bqTINY-III provides a 3.3V LDO regulator. This regulator is typically used to power USB transceiver or drivers in portable applications. Note that this LDO is only enabled when either AC or USB inputs are present. Sleep and Standby Modes The bqTINY-III charger circuitry enters the low-power sleep mode if both AC and USB are removed from the circuit. This feature prevents draining the battery into the bqTINY-III during the absence of input supplies. Note that in SLEEP mode, Q2 remains on (i.e. battery connected to the OUT pin) in order for the battery to continue supplying power to the system. The bqTINY-III enters the low-power standby mode if while AC or USB is present, the CE input is low. In this suspend mode, internal PowerFETs Q1 and Q3 (refer to block diagram) are turned off, the BAT input is used to power the system through OUT pin and the LDO remains on (powered from output). This feature is designed to limit the power drawn from the input supplies (such as USB suspend mode). 15 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 Charge Status Outputs The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-drain transistor is turned off. Note this assumes CE=HIGH.. Table 2. Status Pins Summary CHARGE STATE STAT1 STAT2 Precharge in progress ON ON Fast charge in progress ON OFF Charge done OFF ON Charge suspend (temperature), timer fault, and sleep mode OFF OFF ACPG, USBPGOutputs (Power Good) The two open-drain pins, ACPG, USBPG (AC and USB Power Good) indicate when the AC adapter or USB port is present and above the battery voltage. The corresponding output turns ON (low) when exiting sleep mode (input voltage above battery voltage). This output is turned off in the sleep mode (open drain). The ACPG, USBPG pins can be used to drive an LED or communicate to the host processor. Note that OFF indicates the open-drain transistor is turned off. CE Input (Chip Enable) The CE (chip enable) digital input is used to disable or enable the IC. A high-level signal on this pin enables the chip and a low-level signal disables the device and initiates the standby mode. The bqTINY-III enters the low-power standby mode when the CE input is low with either AC or USB present. In this suspend mode, internal PowerFETs Q1 and Q3 (refer to block diagram) are turned off, the battery (BAT pin) is used to power the system via Q2 and the OUT pin which also powers the LDO. This feature is designed to limit the power drawn from the input supplies (such as USB suspend mode). Charge Disable Functions The DPPM input can be used to disable the charge process. This can be accomplished by floating the DPPM mode. Note that this applies to both AC and USB charging. TImer Fault Recovery As shown in Figure 3, bqTINY-III provides a recovery method to deal with timer fault conditions. The following summarizes this method: Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs. Recovery Method: bqTINY-III waits for the battery voltage to fall below the recharge threshold. This could happen as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the recharge threshold, the bqTINY-III clears the fault and starts a new charge cycle. A POR or CE toggle also clears the fault. Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs. Recovery Method:Under this scenario, the bqTINY-III applies the I(FAULT) current. This small current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, then the bqTINY-III disables the I(FAULT) current and executes the recovery method described for condition #1. Once the battery falls below the recharge threshold, the bqTINY-III clears the fault and starts a new charge cycle. A POR or CE toggle also clears the fault. 16 bq24030, bq24032, bq24035 www.ti.com SLUS618 – AUGUST 2004 APPLICATION INFORMATION Selecting the Input and Output Capacitors In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A 0.1-µF ceramic, placed in close proximity to AC and USB to VSS pins, works well. In some applications depending on the power supply characteristics and cable length it may be necessary to add an additional 10-µF ceramic to each input. The bqTINY-III only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed between the OUT and VSS pin is typically sufficient. The integrated LDO requires a maximum of 1-µF ceramic capacitor on its output. The output does not require a capacitor for a steady state load but a 0.1-µF minimum capacitance is recommended. It is recommended to install a minimum of 33-µF between the BAT pin and VSS (in parallel with the battery). This ensures proper hot plug power-up with a no load condition (no system load or battery attached). Thermal Considerations The bqTINY-III is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment (SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal performance is thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA is: T TA JA J P (9) where • TJ = chip junction temperature • TA = ambient temperature • P = device power dissipation Factors that can greatly influence the measurement and calculation of θJA include: • whether or not the device is board mounted • trace size, composition, thickness, and geometry • orientation of the device (horizontal or vertical) • volume of the ambient air surrounding the device under test and airflow • whether other surfaces are in close proximity to the device being tested The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET. It can be calculated from Equation 10: P V IN V OUT I OUT I BAT V OUT VBAT I BAT (10) Due to the charge profile of Li-xx batteries the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. Please see Figure 2. Typically the Li-Ion battery’s voltage quickly (< 2 V minimum) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery above 3 V). Therefore it is customary to perform the steady state thermal design using 3.5 V as the minimum battery voltage since the system board and charging device doesn't have time to reach a maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and charger’s power pad temperature. 17 bq24030, bq24032, bq24035 SLUS618 – AUGUST 2004 www.ti.com APPLICATION INFORMATION (continued) PCB Layout Considerations It is important to pay special attention to the PCB layout. The following provides some guidelines: • To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter capacitors from OUT to VSS should be placed as close as possible to the bqTINY-II, with short trace runs to both signal and VSS pins. • All low-current VSS connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small signal ground path and the power ground path. • The high current charge paths into AC and USB, and from the BAT and OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. • The bqTINY-III is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled, QFN/SON PCB Attachment (SLUA271). 18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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