ispLSI 3192 ® High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic ORP F3 F2 ORP F1 ORP E3 F0 E2 ORP E1 E0 Boundary Scan Global Routing Pool OR Array A1 A2 A3 D3 D Q D2 D Q Twin GLB D Q D1 D0 OR Array • IN-SYSTEM PROGRAMMABLE — Supports ISP™ or ispJTAG™ Programming — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging D Q ORP A0 AND Array ORP ORP • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100 MHz Maximum Operating Frequency — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power ORP D Q D Q D Q D Q B0 B1 ORP B2 B3 ORP C0 C1 ORP C2 C3 ORP • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE 0139/3192 • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Five Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity Description The ispLSI 3192 is a High Density Programmable Logic Device containing 384 Registers, 192 Universal I/O pins, five Dedicated Clock Input Pins, twelve Output Routing Pools (ORP), and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3192 features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 3192 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms The basic unit of logic on the ispLSI 3192 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3. There are a total of 24 of these Twin GLBs in the ispLSI 3192 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 3192_08 1 June 2002 I/O 72 I/O 74 I/O 76 I/O 78 I/O 80 I/O 82 I/O 84 I/O 86 I/O 88 I/O 90 I/O 92 I/O 94 I/O 73 I/O 75 I/O 77 I/O 79 I/O 81 I/O 83 I/O 85 I/O 87 I/O 89 I/O 91 I/O 93 I/O 95 B0 I/O 159 I/O 157 I/O 155 I/O 153 I/O 151 I/O 149 I/O 147 I/O 145 I/O 143 I/O 141 I/O 139 I/O 137 I/O 135 I/O 133 I/O 131 I/O 129 I/O 166 I/O 164 I/O 162 I/O 160 I/O 158 I/O 156 I/O 154 I/O 152 I/O 150 I/O 148 I/O 146 I/O 144 I/O 142 I/O 140 I/O 138 I/O 136 I/O 134 I/O 132 I/O 130 I/O 128 F2 B1 F1 A2 B2 F0 E3 B3 C0 2 E2 C1 E1 A0 D3 A1 D2 Global Routing Pool (GRP) D1 A3 D0 C2 Output Routing Pool Output Routing Pool Output Routing Pool Output Routing Pool Input Bus Input Bus Input Bus I/O 167 I/O 165 I/O 163 I/O 161 I/O 174 I/O 172 I/O 170 I/O 168 F3 Output Routing Pool Output Routing Pool TMS/MODE TCLK/SCLK BSCAN/ispEN I/O 175 I/O 173 I/O 171 I/O 169 I/O 182 I/O 180 I/O 178 I/O 176 Input Bus Output Routing Pool Output Routing Pool I/O 183 I/O 181 I/O 179 I/O 177 I/O 190 I/O 188 I/O 186 I/O 184 Output Routing Pool Output Routing Pool CLK 0 CLK 1 CLK 2 IOCLK 1 IOCLK 0 I/O 191 I/O 189 I/O 187 I/O 185 GOE1 GOE0 Generic Logic Blocks Y0 Y1 Y2 Y3 Y4 I/O 64 I/O 66 I/O 68 I/O 70 I/O 65 I/O 67 I/O 69 I/O 71 Megablock I/O 56 I/O 58 I/O 60 I/O 62 I/O 24 I/O 26 I/O 28 I/O 30 I/O 57 I/O 59 I/O 61 I/O 63 I/O 25 I/O 27 I/O 29 I/O 31 I/O 48 I/O 50 I/O 52 I/O 54 I/O 16 I/O 18 I/O 20 I/O 22 I/O 49 I/O 51 I/O 53 I/O 55 I/O 17 I/O 19 I/O 21 I/O 23 I/O 40 I/O 42 I/O 44 I/O 46 I/O 8 I/O 10 I/O 12 I/O 14 I/O 41 I/O 43 I/O 45 I/O 47 I/O 9 I/O 11 I/O 13 I/O 15 I/O 32 I/O 34 I/O 36 I/O 38 I/O 0 I/O 2 I/O 4 I/O 6 I/O 33 I/O 35 I/O 37 I/O 39 I/O 1 I/O 3 I/O 5 I/O 7 Output Routing Pool Output Routing Pool TOE Input Bus Specifications ispLSI 3192 Functional Block Diagram Figure 1. ispLSI 3192 Functional Block Diagram Input Bus Boundary Scan TDI/SDI E0 TRST TDO/SDO I/O 126 I/O 124 I/O 122 I/O 120 I/O 127 I/O 125 I/O 123 I/O 121 I/O 118 I/O 116 I/O 114 I/O 112 I/O 119 I/O 117 I/O 115 I/O 113 I/O 110 I/O 108 I/O 106 I/O 104 I/O 111 I/O 109 I/O 107 I/O 105 I/O 102 I/O 100 I/O 98 I/O 96 I/O 103 I/O 101 I/O 99 I/O 97 C3 RESET 0139.3192.2.eps Specifications ispLSI 3192 Description (Continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 192 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Clocks in the ispLSI 3192 device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the I/O cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3192 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device's input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The 192 I/O Cells are grouped into six sets of 32 bits. Each of these I/O groups is associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all I/O cells. That PTOE signal can be generated within any GLB in the Megablock. Each I/O cell can select either a Global OE or a PTOE. The ispLSI 3192 supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the ispLSI 3192 Attribute Four Twin GLBs, 32 I/O Cells and two ORPs are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 32 I/O cells by the two ORPs. The ispLSI 3192 device contains six of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Quantity Twin GLBs 24 Registers 384 I/O Pins 192 Global Clocks 5 Global OE 2 Test OE 1 Table - 003/3192 3 Specifications ispLSI 3192 Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER VCC Supply Voltage VIL VIH Input Low Voltage Input High Voltage MIN. MAX. UNITS Commercial TA = 0°C to +70°C 4.75 5.25 V Industrial TA = -40°C to +85°C 4.5 5.5 V 0 0.8 V 2.0 VCC +1 V Table 2 - 0005/3192 Capacitance (TA=25°C,f=1.0 MHz) TYPICAL UNITS I/O Capacitance 10 pf VCC = 5.0V, VI/O = 2.0V Clock Capacitance 15 pf VCC = 5.0V, VY = 2.0V SYMBOL C1 C2 PARAMETER TEST CONDITIONS Table 2 - 0006/3192 Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles Data Retention ispLSI Erase/Reprogram Cycles Table 2- 0008B 4 Specifications ispLSI 3192 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 3ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 See figure 2 3-state levels are measured 0.5V from steady-state active level. Device Output Table 2 - 0003 Test Point CL* R2 Output Load conditions (See figure 2) *CL includes Test Fixture and Probe Capacitance. TEST CONDITION A B C R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF 0213A Table 2 - 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL CONDITION 3 MIN. TYP. IOL= 8 mA – – Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA Bscan/ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA PARAMETER MAX. UNITS VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA ICC2,4 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V Commercial fTOGGLE = 1 MHz Industrial – – 320 320 – – mA mA 0.4 V Table 2 - 0007isp/3192 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 5 Specifications ispLSI 3192 External Switching Characteristics1, 2, 3 Over Recommended Operating Conditions PARAMETER TEST5 COND. #2 -100 DESCRIPTION1 -70 MIN. MAX. MIN. MAX. UNITS tpd1 A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass — 10 — 15 ns tpd2 A 2 Data Propagation Delay — 13 — 18 ns 100 — 70 — MHz 80 — 50 — MHz 125 — 83 — MHz — 9 — ns fmax A 3 Clock Frequency with Internal Feedback fmax (Ext.) — 4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 3 fmax (Tog.) — 5 Clock Frequency, Max Toggle tsu1 — 6 GLB Reg. Setup Time before Clock, 4PT bypass 5.5 tco1 A 7 GLB Reg. Clock to Output Delay, ORP bypass — 6 — 9 ns th1 — 8 GLB Reg. Hold Time after Clock, 4PT bypass 0 — 0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 6.5 — 11 — ns tco2 — 10 GLB Reg. Clock to Output Delay — 6.5 — 10 ns th2 — 11 GLB Reg. Hold Time after Clock 0 — 0 — ns tr1 A 12 Ext. Reset Pin to Output Delay — 13.5 — 15 ns trw1 — 13 Ext. Reset Pulse Duration 6.5 — 12 — ns tptoeen B 14 Input to Output Enable — 15 — 18 ns tptoedis C 15 Input to Output Disable — 15 — 18 ns tgoeen B 16 Global OE Output Enable — 9 — 12 ns tgoedis C 17 Global OE Output Disable — 9 — 12 ns ttoeen — 18 Test OE Output Enable — 12 — 15 ns 4 ttoedis — 19 Test OE Output Disable — 12 — 15 ns twh — 20 Ext. Sync. Clock Pulse Duration, High 4 — 6 — ns twl — 21 Ext. Sync. Clock Pulse Duration, Low 4 — 6 — ns tsu3 — 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4) 3.5 — 5 — ns th3 — 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4) 0 — 0 — ns 1. 2. 3. 4. 5. Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. Timing Ext.6192.eps 6 Specifications ispLSI 3192 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 -100 DESCRIPTION -70 UNITS MIN. MAX. MIN. MAX. — 1.3 — 1.9 ns 25 I/O Latch Delay — 9.2 — 11.9 ns 26 I/O Register Setup Time before Clock 6.5 — 9.3 — ns 27 I/O Register Hold Time after Clock -3.0 — -4.3 — ns 28 I/O Register Clock to Out Delay — 3.3 — 5.9 ns 29 I/O Register Reset to Out Delay — 3.3 — 3.9 ns 30 GRP Delay — 1.4 — 2.1 ns 31 4 Product Term Bypass Path Delay (Comb.) — 4.3 — 7.8 ns Inputs tiobp tiolat tiosu tioh tioco tior 24 I/O Register Bypass GRP tgrp GLB t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP torp torpbp 32 4 Product Term Bypass Path Delay (Reg.) — 5.5 — 7.4 ns 33 1 Product Term/XOR Path Delay — 6.0 — 8.3 ns 34 20 Product Term/XOR Path Delay — 6.5 — 9.4 ns — 7.1 — 10.3 ns 36 GLB Register Bypass Delay — 0.3 — 0.4 ns 37 GLB Register Setup Time before Clock 0.2 — 1.7 — ns 38 GLB Register Hold Time after Clock 3.5 — 5.3 — ns 39 GLB Register Clock to Output Delay — 0.1 — 1.7 ns 40 GLB Register Reset to Output Delay — 2.4 — 2.8 ns 41 GLB Product Term Reset to Register Delay — 5.0 — 7.5 ns 42 GLB Product Term Output Enable to I/O Cell Delay — 7.6 — 9.2 ns 43 GLB Product Term Clock Delay 4.9 5.9 7.4 8.8 ns 44 ORP Delay — 1.1 — 1.7 ns 45 ORP Bypass Delay — 0.6 — 0.7 ns 3 35 XOR Adjacent Path Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Specifications ispLSI 3192 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 -100 DESCRIPTION MIN. -70 MAX. MIN. MAX. UNITS Outputs tob 46 Output Buffer Delay — 2.4 — 2.5 ns tobs 47 Output Buffer Delay, Slow Slew — 22.4 — 27.5 ns toen 48 I/O Cell OE to Output Enabled — 4.7 — 4.8 ns todis 49 I/O Cell OE to Output Disabled — 4.7 — 4.8 ns tgy0/1/2 50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line 2.9 2.9 4.1 4.1 ns tioy3/4 51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 3.0 3.0 4.3 4.3 ns tgr 52 Global Reset to GLB and I/O Registers — 7.6 — 8.0 ns tgoe 53 Global OE Pad Buffer — 4.3 — 7.2 ns ttoe 54 Test OE Pad Buffer — 7.3 — 10.2 ns Clocks Global Reset 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Timing Int.2.3192.eps 8 Specifications ispLSI 3192 ispLSI 3192 Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback #31 I/O Reg Bypass I/O Pin (Input) #24 #52 GRP #30 Input D Register Q RST #25 - 29 4 PT Bypass GLB Reg Bypass ORP Bypass #32 #36 #45 20 PT XOR Delays GLB Reg Delay ORP Delay D #33 - 35 Q #44 RST #52 Reset Y3,4 #37 - 40 #51 Control RE PTs OE #41 - 43 CK #50 Y0,1,2 #53 GOE0,1 #54 TOE 0902/3192 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 1.8 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #34) + (#37) - (#24+ #30+ #43) (1.3 + 1.4 + 6.5) + (0.2) - (1.3 + 1.4 + 4.9) th = = = 2.9 ns = Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #43) + (#38) - (#24+ #30+ #34) (1.3 + 1.4 + 5.9) + (3.5) - (1.3 + 1.4 + 6.5) tco = = = 12.2 ns = Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #43) + (#39) + (#44 + #46) (1.3 + 1.4 + 5.9) + (0.1) + (1.1 + 2.4) Table 2- 0042-3192 Note: Calculations are based upon timing specifications for the ispLSI 3192-100L. 9 #46, 47 #48, 49 I/O Pin (Output) Specifications ispLSI 3192 Power Consumption Power Consumption in the ispLSI 3192 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax 640 ICC (mA) 540 ispLSI 3192 440 340 240 0 10 20 30 40 50 60 70 80 90 100 fmax (MHz) Notes: Configuration of 16 16-bit Counters Typical Current at 5V, 25° C ICC can be estimated for the ispLSI 3192 using the following equation: ICC = 50 + (# of PTs * 0.65) + (# of nets * Max. freq * 0.015) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/3192 Package Thermal Characteristics For the ispLSI 3192-100LB272, it is strongly recommended that the actual Icc be verified to ensure that the maximum junction temperature (TJ) with power supplied is not exceeded. Depending on the specific logic design and clock speed, airflow may be required to satisfy the maximum allowable junction temperature (TJ) specification. Please refer to the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ. 10 Specifications ispLSI 3192 Pin Description NAME PQFP PIN NUMBERS GOE0 and GOE1 TOE 152 and 153 154 Global Output Enable input pins. Test output enable pin. TOE tristates all I/O pins when a logic low is driven. RESET 33 Y0, Y1 and Y2 35, 34, 148 Y3 and Y4 149, 151 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells in the device. BSCAN/ispEN2 32 Input — Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP state machine control pins MODE, SDI, SDO and SLCK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in high-Z state. TDI/SDI2 30 TCK/SCLK2 29 TMS/MODE2 28 TRST/NC1, 2 155 TDO/SDO2 27 Input - This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. Input - Test Reset, active low to reset the Boundary Scan State Machine. Output - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the isp data. When ispEN is high it functions as Test Data Out. GND 13, 31, 105, 119, 197, 211, 6, 20, 98, 112, 190, 204, 147 NC1 38, 45, 52, 59, 66, 73, 80, 87, 94, 101, 108, 115, 122, 129, 136, 143, 158, 165, 172, 179, 186, 193, 200, 207, 214, 221, 228, 235, 2, 9, 16, 23, 49, 133, 225, 42, 126, 218, 39, 46, 53, 60, 67, 74, 81, 88, 95, 102, 109, 116, 123, 130, 137, 144, 159, 166, 173, 180, 187, 194, 201, 208, 215, 222, 229, 236, 3, 10, 17, 24, 40, 47, 54, 61, 68, 75, 82, 89, 96, 103, 110, 117, 124, 131, 138, 145, 160, 167, 174, 181, 188, 195, 202, 209, 216, 223, 230, 237, 4, 11, 18, 25, DESCRIPTION 36, 43, 50, 57, 64, 71, 78, 85, 92, 99, 106, 113, 120, 127, 134, 141, 156, 163, 170, 177, 184, 191, 198, 205, 212, 219, 226, 233, 240, 7, 14, 21, VCC 37, 44, 51, 58, 65, 72, 79, 86, 93, 100, 107, 114, 121, 128, 135, 142, 157, 164, 171, 178, 185, 192, 199, 206, 213, 220, 227, 234, 1, 8, 15, 22, 63, 77, 150, 169, 239 56, 70, 140, 162, 232 41, 48, 55, 62, 69, 76, 83, 90, 97, 104, 111, 118, 125, 132, 139, 146, 161, 168, 175, 182, 189, 196, 203, 210, 217, 224, 231, 238, 5, 12, 19, 26 Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 I/O 96 - I/O 101 I/O 102 - I/O 107 I/O 108 - I/O 113 I/O 114 - I/O 119 I/O 120 - I/O 125 I/O 126 - I/O 131 I/O 132 - I/O 137 I/O 138 - I/O 143 I/O 144 - I/O 149 I/O 150 - I/O 155 I/O 156 - I/O 161 I/O 162 - I/O 167 I/O 168 - I/O 173 I/O 174 - I/O 179 I/O 180 - I/O 185 I/O 186 - I/O 191 91, 183, Ground (GND) 84, 176, VCC No Connect Table 2 - 0002/3192 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 11 Specifications ispLSI 3192 Signal Locations and Descriptions NAME BGA BALL NUMBERS M4, P3, T3, V3, U5, U7, V8, W10, U11, V13, Y16, Y18, Y20, U20, R20, M17, J17, G18, E18, C18, D16, D14, C13, B11, D10, C8, A5, A3, C3, D1, F1, J4, GOE0 and GOE1 TOE K17 and J20 J19 Global Output Enable input pins. Test output enable pin. TOE tristates all I/O pins when a logic low is driven. RESET M1 Y0, Y1 and Y2 M3, M2, L20 Y3 and Y4 K20, K18 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells in the device. BSCAN/ispEN2 L4 Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP state machine control pins MODE, SDI, SDO and SLCK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in high-Z state. TDI/SDI2 L3 TCK/SCLK2 L2 TMS/MODE2 L1 TRST/NC1, 2 J18 TDO/SDO2 K1 Input - This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. Input - Test Reset, active low to reset the Boundary Scan State Machine. Output - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the isp data. When ispEN is high it functions as Test Data Out. GND A1, D4, D8, D13, D17, H4, H17, J9, J10, Ground (GND) J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17, U4, U8, U13, U17 VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 A12, B4, B8, B20, C1, C15, C17, D20, F2, No Connect F20, H1, K19, N20, R1, R19, U1, V4, V6, V20, W1, W13, W17, W19, Y9 VCC NC N1, R2, U2, W2, Y3, W6, W8, V10, Y12, Y14, U14, U16, W20, T18, P18, M18, H20, F19, D19, B19, A18, B15, B13, C11, A9, A7, D7, D5, B1, E3, G3, J3, N2, T1, V1, Y1, Y4, Y6, Y8, Y10, W12, W14, V15, V17, V19, T19, P19, M19, H19, E20, C20, A20, A17, A15, A13, A11, B9, B7, C6, C4, C2, E2, G2, J2, N3, P4, T4, W3, V5, V7, U9, Y11, V12, Y15, W16, W18, U19, T20, P20, M20, H18, G17, E17, A19, C16, C14, D12, A10, C9, A6, B5, B3, D2, E1, G1, J1, P1, R3, U3, Y2, W5, W7, V9, W11, U12, V14, Y17, Y19, U18, R18, N18, L19, G20, F18, D18, B18, B16, B14, C12, B10, D9, C7, A4, B2, D3, F3, H3, K2, DESCRIPTION I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 I/O 96 - I/O 101 I/O 102 - I/O 107 I/O 108 - I/O 113 I/O 114 - I/O 119 I/O 120 - I/O 125 I/O 126 - I/O 131 I/O 132 - I/O 137 I/O 138 - I/O 143 I/O 144 - I/O 149 I/O 150 - I/O 155 I/O 156 - I/O 161 I/O 162 - I/O 167 I/O 168 - I/O 173 I/O 174 - I/O 179 I/O 180 - I/O 185 I/O 186 - I/O 191 P2 T2 V2 W4 Y5 Y7 W9 V11 Y13 W15 V16 V18 T17 P17 N19 L18 G19 E19 C19 B17 A16 A14 B12 C10 A8 B6 C5 A2 E4 G4 H2 K3 Input/Output Pins - These are the general purpose I/O pins used by the logic array. Table 2 - 0002/3192.BGA 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 12 Specifications ispLSI 3192 Pin Configuration 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 I/O 168 GND I/O 167 I/O 166 I/O 165 I/O 164 I/O 163 I/O 162 VCC I/O 161 I/O 160 I/O 159 I/O 158 I/O 157 I/O 156 GND I/O 155 I/O 154 I/O 153 I/O 152 I/O 151 I/O 150 VCC I/O 149 I/O 148 I/O 147 I/O 146 I/O 145 I/O 144 GND I/O 143 I/O 142 I/O 141 I/O 140 I/O 139 I/O 138 VCC I/O 137 I/O 136 I/O 135 I/O 134 I/O 133 I/O 132 GND I/O 131 I/O 130 I/O 129 I/O 128 I/O 127 I/O 126 VCC I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 GND I/O 119 I/O 118 ispLSI 3192 240-pin PQFP ispLSI 3192 Top View 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 I/O 117 I/O 116 I/O 115 I/O 114 VCC I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 GND I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 VCC I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 TRST/NC1, 2 TOE GOE1 GOE0 Y4 GND Y3 Y2 NC1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 VCC I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O 22 I/O 23 GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 VCC I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 VCC I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 VCC I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 GND I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 VCC I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND I/O 72 I/O 169 I/O 170 I/O 171 I/O 172 I/O 173 VCC I/O 174 I/O 175 I/O 176 I/O 177 I/O 178 I/O 179 GND I/O 180 I/O 181 I/O 182 I/O 183 I/O 184 I/O 185 VCC I/O 186 I/O 187 I/O 188 I/O 189 I/O 190 I/O 191 2SDO/TDO 2MODE/TMS 2SCLK/TCK 2SDI/TDI GND 2ispEN/BSCAN RESET Y1 Y0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 VCC I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 VCC I/O 18 1/O 19 I/O 20 I/O 21 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 13 240MQFP.3192.eps Specifications ispLSI 3192 Signal Configuration ispLSI 3192 272-Ball BGA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A I/O 116 I/O 117 I/O 121 I/O 122 I/O 125 I/O 128 I/O 131 I/O NC 1 134 I/O 140 I/O 141 I/O 145 I/O 149 I/O 151 I/O 153 I/O 156 I/O 160 I/O 162 I/O GND 167 A B NC 1 I/O 115 I/O 118 I/O 119 I/O 124 I/O 127 I/O 130 I/O 133 I/O 137 I/O 138 I/O 142 I/O NC 1 146 I/O 152 I/O 155 I/O NC 1 159 I/O 165 I/O 166 I/O 169 B C I/O 110 I/O 113 I/O NC 1 114 I/O NC 1 123 I/O 129 I/O 132 I/O 136 I/O 139 I/O 143 I/O 147 I/O 154 I/O 158 I/O 161 I/O 168 I/O NC 1 170 C D NC 1 I/O 109 I/O I/O I/O I/O I/O GND VCC GND VCC 112 120 126 135 144 I/O 171 I/O 174 D E I/O 104 I/O 107 I/O 108 F NC 1 I/O 103 I/O VCC 106 G I/O 100 I/O 101 I/O 102 H I/O 97 I/O 98 I/O GND 99 J GOE1 TOE TRST /NC1 I/O 96 K Y3 NC 1 Y4 L Y2 I/O 94 M I/O 93 N I/O 150 I/O 164 I/O I/O I/O I/O GND VCC GND 148 157 163 172 I/O 111 I/O 173 I/O 175 I/O 176 I/O 177 E ispLSI 3192 VCC I/O 1 178 NC I/O 180 F Bottom View I/O 179 I/O 181 I/O 182 I/O 183 G GND I/O 184 I/O 1 185 NC H GND GND GND GND I/O 186 I/O 187 I/O 188 I/O 189 J GOE0 GND GND GND GND VCC I/O 191 I/O 190 SDO/ TDO K I/O 95 VCC GND GND GND GND ispEN/ BSCAN SDI/ TDI SCLK/ MODE TCK / TMS L I/O 92 I/O 91 I/O 90 GND GND GND GND I/O 0 Y0 Y1 RESET M NC 1 I/O 89 I/O GND 88 GND I/O 3 I/O 2 I/O 1 N P I/O 87 I/O 86 I/O 85 I/O 83 I/O 9 I/O 6 I/O 5 I/O 4 P R I/O 84 NC 1 I/O 82 VCC VCC I/O 10 I/O 7 NC 1 R T I/O 81 I/O 80 I/O 79 I/O 77 I/O 15 I/O 12 I/O 11 I/O 8 T U I/O 78 I/O 75 I/O GND 76 I/O 67 VCC V NC 1 I/O 74 I/O 71 I/O 68 I/O 65 W I/O 73 NC 1 I/O 69 NC 1 Y I/O 72 I/O 70 I/O 66 I/O 64 I/O 105 I/O GND 61 I/O 52 I/O 48 VCC I/O GND 39 I/O 30 VCC I/O GND 24 I/O 16 I/O 13 NC 1 U I/O 62 I/O 58 I/O 54 I/O 51 I/O 47 I/O 43 I/O 40 I/O 36 I/O 33 NC 1 I/O 27 NC 1 I/O 18 I/O 17 I/O 14 V I/O 63 I/O 59 I/O 56 NC 1 I/O 50 I/O 46 I/O 42 I/O 41 I/O 37 I/O 34 I/O 31 I/O 28 I/O 23 I/O 21 I/O 19 NC 1 W I/O 60 I/O 57 I/O 55 I/O 53 I/O 49 I/O 45 I/O 44 NC 1 I/O 38 I/O 35 I/O 32 I/O 29 I/O 26 I/O 25 I/O 22 I/O 20 Y 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 10 1. NC's are not to be connected to any active signals, Vcc or GND. 14 Specifications ispLSI 3192 Part Number Description ispLSI 3192 —XXX X XXXX X Device Family Grade Blank = Commercial I = Industrial Device Number Package Q = PQFP B272 = BGA Power L = Low Speed 100 = 100 MHz fmax 70 = 70 MHz fmax 0212/3192 Ordering Information COMMERCIAL Family ispLSI fmax tpd Ordering Number Package 100 10 ispLSI 3192-100LQ 240-Pin PQFP 100 10 ispLSI 3192-100LB272 272-Ball BGA 70 15 ispLSI 3192-70LQ 240-Pin PQFP 70 15 ispLSI 3192-70LB272 272-Ball BGA Table 2- 0041/3192 INDUSTRIAL Family fmax tpd Ordering Number Package ispLSI 70 15 ispLSI 3192-70LQI 240-Pin PQFP Table 2- 0042/3192 15