LATTICE ORLI10G

ORCA ORLI10G
®
Quad 2.5Gbps, 10Gbps
Quad 3.125Gbps, 12.5Gbps Line Interface FPSC
January 2005
Data Sheet
Introduction
The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic
core. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORLI10G consists
of an OIF standard compliant (OIF-SFI4-01.0) SFI-4.1 or IEEE® 802.3ae compliant XSBI, 10 Gbits/s or 12.5 Gbits/s
transmit and 10 Gbits/s or 12.5 Gbits/s receive line interface.
Both transmit and receive interfaces consist of 16-bit LVDS data at up to 850 Mbits/s, integrated transmit and
receive programmable PLLs for data rate conversions between the line-side and system-side data rates, and a programmable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with
strong FEC system device data standards. In addition to the embedded functionality, the device includes over 400k
of usable FPGA gates. The line interface includes logic to divide the data rate down to 212 MHz or less (1/4 line
rate) or 106 MHz or less (1/8 line rate) for transfer to the FPGA logic. The ORLI10G is designed to connect to a
plethora of industry standard devices on the line side. The programmable logic interface on the system side allows
direct connection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH framer/data engine, or a 10 Gbits/s/12.5
Gbits/s digital wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the Physical Coding Sublayer (PCS), interfaces to the Physical
Media Attachment (PMA), and connects to the system interface (host or switch) for the proposed IEEE 802.3ae 10
Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable device for 10 Gbits/s data solutions. It can be used as the
interface between the line interface and the system interface in a variety of emerging networks, including 10 Gbits/s
SONET/SDH (OC-192/STM-48), 10 Gbits/s Optical Transport Networks (OTN) using digital wrapper and strong
FEC, or 10 Gbits/s Ethernet. Other functions include use in quad OC-48/ STM-16 SONET/SDH systems, interfaces
between quad OC-48/STM-16 and OC-192/STM-64 components, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is received at the line interface and then sent to either a 4-bit or 8-bit
serial-to-parallel converter. On the transmit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. Thus,
the data rate at the internal FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for great flexibility in handling clock rate conversion due to differing amounts of overhead bits in various system data standards. For example, the ORLI10G can divide down the
STS-192/STM-64 SONET/SDH data line rate of 622 MHz by 4 to synchronize with a 155 MHz system clock, or the
12.5 Gbits/s Super-FEC data line rate of 781 MHz can be divided by 8 MHz to 98 MHz system clock or by 8 x 4/5 to
provide a 78 MHz system data rate.
Table 1. ORCA ORLI10G–Available FPGA Logic (equivalent to ORCA OR4E04)
Device
ORLI10G
PFU Rows
36
PFU Columns
36
FPGA Max.
Total PFUs User I/Os*
1,296
316
LUTs
10,368
EBR
Blocks
12
EBR Bits
(k)
111
FPGA System Gates
(k)
333—643
* 316 are available in the 680 PBGAM package.
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with
40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 6 PLLs.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
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ORCA ORLI10G Data Sheet
Embedded Function Features
• Provides a line-interface to system-interface with various system standards such as OC-192/STM-64
SONET/SDH, quad OC-48/STM-16 10 Gbits/s Ethernet, and 10 Gbits/s OTN (digital wrapper/strong FEC) or
12.5 Gbits/s SuperFEC.
• Embedded PLLs with programmable M/N multiplication/division values provide flexible data rate conversion
between line side and system side.
• Line-side supports 16-bit LVDS data with multiple line frequencies supported up to 850 MHz, depending on system standard.
• Line-side interface, including timing and jitter specifications, compliant to OIF 99.102.5 standard.
• Receive-side interface can be split into four separate asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic.
• Data and clock rates divided by 4 or 8 for use in FPGA logic.
• LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output
on-board termination to allow high-speed operation.
• Low-power LVDS buffers.
Programmable Features
• High-performance programmable logic:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 400k usable FPGA system gates.
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3 V) and LVCMOS (2.5 V, and 1.8 V) I/Os.
– Per pin selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
– Two slew rates supported (fast and slew limited).
– Fast-capture input latch and input Flip-Flop latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL. Programmable (on/off) internal parallel termination (100 Ω)
also supported for these I/Os.
• New capability to (de)multiplex I/O signals:
– New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, organized to allow two nibbles to act independently,
plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local set/reset,
and data selects.
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ORCA ORLI10G Data Sheet
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 : 1 MUX, new 8 : 1 MUX, and
ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing, which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PAL™-like AND-OR-INVERT (AOI) in each programmable logic cell.
• New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be configured as:
– 1—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1k x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
– 2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are builtin system registers that act as the control and status center for the device.
• Built-in testability:
– Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only.
– Programming and readback through boundary-scan port compliant to IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
• Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provides optimum clock
modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to
420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x is possible.
• New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route.
This feature also supports compliance with many setup/hold and clock-to-out I/O specifications, and may provide
reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
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ORCA ORLI10G Data Sheet
Programmable Logic System Features
• PCI local bus compliant for FPGA I/Os.
• Improved PowerPC ®/PowerQUICC 860, and PowerPC/PowerQUICC II MPC8260 high-speed synchronous
microprocessor interface can be used for configuration, readback, device control, and device status, as well as
for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface
to synchronous PowerPC processors with user-configurable address space is provided.
• New embedded AMBA™ specification 2.0 AHB system bus (ARM ® processor) facilitates communication among
the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard
cell blocks.
• Variable-size bused readback of configuration data capability with the built-in microprocessor interface and system bus.
• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
• New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200
ps for OR4E04).
• New local clock routing structures allow creation of localized clock trees.
• Two new edge clock structures allow up to six high speed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
• New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest highspeed memory interfaces.
• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced-speed internal
logic.
• ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis,
simulation, and timing analysis.
• Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-PHY3.
Also meets proposed specifications for UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces.
• Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-over-SONET as
defined by the Saturn Group.
Features of the 10G PCS IP Core
Programmable logic provides a variety of yet-to-be standardized interface functions, including the following IP core
functions (IP Cores sold separately):
• 10 Gbits/s Ethernet Physical Coding Sublayer (PCS), as defined by IEEE 802.3ae:
– XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short-reach
(typically less than 3 in.) interconnect interface.
– Elastic store buffers for clock domain transfer to/from the XGMII interface.
– X59 + X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet.
– 64b/66b encoders/decoders for 10 Gbits/s Ethernet.
– Idle insertion and deletion.
– SMI interface for control and status.
• Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/SDH MUX/deMUX functions.
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ORCA ORLI10G Data Sheet
Description
FPSC Definition
FPSCs, or Field-Programmable System Chips, are devices that combine field-programmable logic with ASIC, or
mask-programmed logic, on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the
design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the
FPGA functionality is changed; all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs,
boundary scan, etc. Columns of programmable logic are replaced on one side of the device, allowing pins from the
replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their
FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more siliconarea efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to provide a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
Series 4-based FPSCs expand this interface by providing a link between the embedded block and the multimaster
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions, including the embedded block RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing greater flexibility. Multiple embedded
core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a configured FPGA. This system
is used to map a design onto the ORCA architecture and then place and route it using ispLEVER's timing-driven
tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design
entry, synthesis, simulation, and timing analysis.
The ispLEVER development system interfaces to front-end design entry tools and provides the tools to produce a
configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow,
the design entry and the bit stream generation stage. Recent improvements in ispLEVER allow the user to provide
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ORCA ORLI10G Data Sheet
timing requirement information through logical preferences only; thus, the designer is not required to have physical
knowledge of the implementation.
Following design entry, the development system's map, place, and route tools translate the netlist into a routed
FPGA. A floor planner is available for layout feedback and control. A static timing analysis tool is provided to determine design speed, and a back-annotated netlist can be created to allow simulation and timing.
Timing and simulation output files from ispLEVER are also compatible with many third-party analysis tools. A bit
stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configuration RAM, embedded block RAM, and/or FPSC memory.
When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined
with the front-end tools, ispLEVER produces configuration data that implements the various logic and routing
options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER software and third-party synthesis
and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, Synopsys Smart Model ®, and/or compiled Verilog ®
simulation model, HSPICE ® and/or IBIS models for I/O buffers, and complete online documentation. The kit's software couples with ispLEVER software, providing a seamless FPSC design environment. More information can be
obtained by visiting the Lattice website at www.latticesemi.com or contacting a local sales office.
ORLI10G FPGA Logic Overview
The following sections provide a brief overview of the main architectural features of the ORLI10G FPGA logic. For
more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the
“Products” folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA
Data Sheet provides detailed information required for designing with the ORLI10G device. Topics covered in the
ORCA Series 4 Data Sheet include:
• FPGA Logic Architecture
• FPGA Routing Resources
• FPGA Clock Routing Resources
• FPGA Programmable Input/Output Cells (PICs)
• FPGA Embedded Block RAM (EBR)
• Microprocessor Interface (MPI)
• Phase-Locked Loops (PLLs)
• Electrical Characteristics
• FPGA Timing Characteristics
• Power-up
• Configuration
ORCA Series 4 FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce
logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades.
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ORCA ORLI10G Data Sheet
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge
of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-a-Chip integration
with true plug-and-play design implementation.
The architecture consists of four basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells
(PIOs), Embedded Block RAMs (EBRs), and system level features. These elements are interconnected with a rich
routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which
provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical
blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each
PLC contains a PFU, (Supplementary Logic Interconnect) SLIC, local routing resources, and configuration RAM.
Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform
input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals.
Large blocks of 512 x 18 quadport RAM complement the existing distributed PFU memory. The RAM blocks can be
used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the
MPI, PLLs, and the Embedded System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/Flip-Flops, and one additional Flip-Flop
that may be used independently or with arithmetic functions.
The PFU is organized in a twin-quad fashion; two sets of four LUTs and Flip-Flops that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered in the ninth Flip-Flop for pipelining. Each PFU may also be
configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The Flip-Flops (or latches) may obtain input
from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The Flip-Flops also
have programmable clock polarity, clock enables, and local set/reset.
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional
INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU
outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for realworld system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements.
I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features that
allow the user the flexibility to select new I/O types that support high-speed interfaces.
Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA
array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset,
and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast
latching of data from any pad. The combination provides very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal,
and register the signals without explicitly building a demultiplexer with a PFU.
On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can
be associated with each I/O pad. The output logic associated with each pad allows multiplexing of output signals
and other functions of two output signals.
The output Flip-Flop, in combination with output signal multiplexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output
buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In
addition, this 3-state signal can be registered or nonregistered.
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ORCA ORLI10G Data Sheet
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These
modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing
data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and
out of the I/O buffers on both edges of the clock.
The new programmable I/O cell allows designers to select I/Os which meet many new communication standards,
permitting the device to hook up directly without any external interface translation. They support traditional FPGA
standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses
with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One
PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide
high connectivity with fast software routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing are available for fast
regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can
be sourced from any I/O pin, PLLs, or the PLC logic.
The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specific pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system
bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly
tuned networking specific phase-locked loops. These functional blocks support easy glueless system interfacing
and the capability to adjust to varying conditions in today's high-speed networking systems.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-bit,
16-bit, and 32-bit interfaces with optional parity to the Motorola ® PowerPC 860 bus, it can be used for configuration
and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4
embedded system bus at 66 MHz performance.
The MPI provides, following configuration, a system-level microprocessor interface through the system bus to the
user-defined logic within the FPGA, and includes access to the embedded block RAM. The MPI supports burst
data read and write transfers, allowing short, uneven transmission of data through the interface by including data
FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16beat (16 x 1 bytes).
The 32-bit device identification code (device_id) for the ORLI10G is at system bus register address 0x0-0x3. (see
Figure 1.)
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ORCA ORLI10G Data Sheet
Figure 1. ORLI10G 32-bit Device Identification Code
0000_000101000_1_001000_00000011101_1
First OR4E04
based FPSC
40 rows (OR4E04)
FPSC identifier
Series 4
Manufacturer ID
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration
logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements.
The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is
integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from
routing, or port clock (for JTAG configuration modes). In the ORLI10G FPSC, the system bus is not connected to
the embedded core.
Phase-Locked Loops
Four user PLLs are provided for ORCA Series 4 FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks
from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x (the input clock frequency). Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input
buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.
Additional highly tuned and characterized Dedicated Phase-Locked Loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to very
tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are targeted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 systems.
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two
byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,
as well as direct connection to the high-speed system bus.
Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable
multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k, including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple
of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit
CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can
also be preloaded at device configuration time.
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ORCA ORLI10G Data Sheet
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The configuration data can reside
externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low, pin-count method
for configuring FPGAs.
The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial,
master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface
and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and
partial reconfiguration are also permitted.
Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as
well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE
1149.2) port is also available meeting in-system programming (ISP) standards (IEEE 1532 Draft).
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA and FPSC
devices, or visit our website at: http://www.latticesemi.com
10
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Overview
Device Layout
The ORLI10G FPSC provides a high-speed transmit and receive line interface combined with FPGA logic. The
device is based on the 1.5 V OR4E04 FPGA. The ORLI10G consists of an embedded backplane transceiver core
and a full OR4E04 36x36 FPGA array.
The ORLI10G is a line interface device that contains an FPGA base array, a 10 Gbits/s line interface block, and
programmable PLLs to do the overhead clock rate conversions on a single monolithic chip. The embedded portion
includes:
• Line Interface: This consists of a 16-bit LVDS receive data bus and a 16-bit LVDS transmit bus operating up to
850 Mbits/s per input/output pair. Each 4-bit LVDS I/O has a high-speed LVDS clock (operating up to 850 MHz)
associated with it. The bit order (i.e. whether bit 0 is the most significant or least significant bit) of the 16-bit transmitted and received busses can be defined separately in the user's programmable logic netlist that interfaces to
the embedded core so that any required interface standard can be met.
• MUX/deMUX: This performs the MUXing and deMUXing between the high-speed line interface data operating at
the line rate and system data operating at 1/4 or 1/8 the line rate.
• On-board PLLs: This is used to align system-side data with the line-side data, which is at a slightly higher data
bandwidth than the system data because of the addition of overhead due to encoding.
Figure 2 shows the ORLI10G block diagram.
10G Mode
The ORLI10G can operate in one of two data modes: 10G mode or Quad 2.5G mode.
In 10G (or single-channel) mode, all 16 LVDS transmit data outputs are assumed to be one data bus with one
LVDS clock provided off chip for the data. Likewise, all 16 LVDS receive data inputs are assumed to be one data
bus with one LVDS input clock provided for the data.
Transmit Path
In 10G mode, the transmit data from the FPGA logic is passed to the embedded core as a single 128- or 64-bit bus.
An off-chip transmit reference clock is divided down in the core by 8 (for 128-bit to 16-bit MUX) or by 4 (for 64-bit to
16-bit MUX). All four transmit clock outputs are therefore synchronized.
Receive Path
The 16-bit receive data is deMUXed in the embedded core to a single 128-bit or 64-bit data bus and passed to the
FPGA logic. The lowest-order LVDS input clock (rx_clk_in[0]) is used as the receive clock for all 16 data bits (the
other three LVDS input clock pairs should be left unconnected). This clock is divided down in the core by 8 (for 16bit to 128-bit deMUX) or by 4 (for 16-bit to 64-bit deMUX) and passed to the FPGA logic with the data.
The 2.5G mode in the transmit direction for the ORLI10G device transmits four independent data buses with one
output clock.
2.5G Mode
In 2.5G (or quad-channel) mode, the 16 LVDS receive data inputs are assumed to be four independent 4-bit data
buses with four LVDS asynchronous input clocks provided for each data bus. The 2.5G mode in the transmit direction for the ORLI10G device transmits four independent data buses with one output clock.
Receive Path
Each of the four 4-bit receive data buses are deMUXed in the embedded core to one of four independent 32- or 16bit data buses and passed to the FPGA logic. The four receive clock inputs are divided down in the core by 8 (for
each 4- to 32-bit deMUX) or by 4 (for each
11
Lattice Semiconductor
ORCA ORLI10G Data Sheet
4- to 16-bit deMUX), and each divided clock is passed to the FPGA logic with its associated data bus. All four data
paths act as separate data interfaces that are asynchronous to each other.
The ORLI10G supports transmit and receive data rates up to 850 Mbits/s. Therefore, the total data rate each of the
quad channels is 850 Mbits/s x 4 or 3.4 Gbits/s. Figure 2 shows a representation of the 10G and 2.5G modes in
both transmit and receive directions.
Figure 2. ORCA ORLI10G Block Diagram
EMBEDDED CORE
FPGA LOGIC
(400K GATES)
TRANSMIT
PLLs
TXCLK
64:16 MUX
OR
128:16 MUX
64-bit OR 128-bit
2
(167 MHz—78 MHz)
REFERENCE CLOCK
TRANSMIT DATA
16 x 622 OR
16 x 645 OR
16 x 667 OR
16 x 781 Mbits/s
TRANSMIT CLOCK
RECEIVE
PLLs
RECEIVE DATA
16 x 622 OR
16 x 645 OR
16 x 667 OR
16 x 781 Mbits/s
16:64 DEMUX
OR
16:128 DEMUX
SYSTEM INTERFACE:
— POS-PHY 4
— XGMII
— 156 MHz PECL
(OC-48/STM-16
SONET/SDH)
— USER DEFINED
RXCLK
2
(167 MHz—78 MHz)
64-bit OR 128-bit
FOUR 2.5 Gbit RXCLKs
12
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 3. 10G (Single-Channel) and 2.5G (Quad-Channel) Modes
10G MODE
RECEIVE PATH
CORE
LVDS DATA
16
RX_CLK_IN[0]
RX_CLK_IN[3:1]
TRANSMIT PATH
FPGA
FPGA
DATA
DATA
128 OR 64
128 OR 64
MUX
DEMUX
DIV BY 8
OR
DIV BY 4
CORE
16
TX_CLK_OUT[3:0]
RX[1:2]VCOP
2
2
DIV BY 8
DIV BY 4
TX[1:2]VCOP
UNUSED
2.5G MODE
RECEIVE PATH
CORE
LVDS CLOCK
1
DEMUX
DIV BY 8
OR
DIV BY 4
LVDS DATA
4
LVDS CLOCK
1
LVDS CLOCK
1
DIV BY 8
OR
DIV BY 4
LVDS CLOCK
1
1
32 OR 16
RX_CLK8_OUT2
1
DATA
DEMUX
DIV BY 8
OR
DIV BY 4
LVDS DATA
4
32 OR 16
RX_CLK8_OUT3
DATA
DEMUX
LVDS DATA
4
FPGA
DATA
LVDS DATA
4
LVDS
DATA
32 OR 16
RX_CLK8_OUT1
1
DATA
DEMUX
DIV BY 8
OR
DIV BY 4
13
32 OR 16
RX_CLK8_OUT0
1
TX_CLK_IN
REFERENCE
CLOCK
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Receive Path Details
In the receive path, the ORLI10G embedded core can be broken down into three sections: the high-speed line
interface, the demultiplexer, and the receive-side onboard PLLs. Note that both transmit and receive PLLs are in
addition to the four Programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
Line Interface
In the receive path, 16-bit data and associated clocks are inputs to the line interface. Typical data rates are
expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS input data bus is actually
composed of four 4-bit data buses with one clock for each 4-bit data bus. In the 10G mode, all four input clocks are
tied together internal to the device and driven by the lowest-order input clock. In 2.5G mode, the four clocks may be
asynchronous to each other. The ORLI10G uses LVDS (Low-Voltage Differential Signaling) drivers/receivers, which
are intended to provide point-to-point connection between the ORLI10G and optical transceiver (MUX/deMUX)
parts. The LVDS inputs are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS
inputs are terminated with a 100 Ω resistor to improve performance.
The receive line interface on the ORLI10G can connect to devices that are compliant to either the XSBI standard or
the SFI-4 standard. The major difference for these standards is that for XSBI (IEEE 802.3ae version 2.1), the least
significant bit [0] is received first after deserialization by the external deMUX device, whereas SFI-4 receives the
most significant bit first. In some cases, bits [15:0] on the ORLI10G should be connected to bits [0:15] on the
device to which the ORLI10G device interfaces. An example of this is the PCS IP core in the ORLI10G when the
ORLI10G is connected to an XSBI version 2.1 device.
It should be noted that IEEE 802.3ae version 3.1 to D3.4 (version D3.4 is the latest draft version of this specification as of the writing of this data sheet) swaps XSBI so that the most significant bit is received first, thus requiring
that bits [0:15] on the ORLI10G be connected directly to bits [0:15] on the XSBI device.
DeMUX
The demultiplexer takes the high-speed line data and clocks and converts the data and clock to rates appropriate
for transfer to the FPGA logic. The demultiplexer supports two modes of operation:
• Divide-by-8
– 10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to 850
Mbits/s into 128 bits at 78 Mbits/s to 106 Mbits/s. The incoming clocks are divided by 8.
– 2.5G (or quad channel): The demultiplexer converts the incoming four bits of data at 622 Mbits/s to 850
Mbits/s into 32 bits at 78 Mbits/s to 106 Mbits/s. The associated clock is also divided by 8. This is repeated
four times with each 4-bit data/clock group assumed to be asynchronous to the others.
• Divide-by-4
– 10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to
850 Mbits/s into 64 bits at 156 Mbits/s to 212 Mbits/s. The incoming clocks are divided by 4.
– 2.5G (or quad channel): The demultiplexer converts the incoming 4 bits of data at 622 Mbits/s to 850 Mbits/s
into 16 bits at 156 Mbits/s to 212 Mbits/s. The associated clock is also divided by 4. This is repeated four
times with each 4-bit data/clock group assumed to be asynchronous to the others.
Onboard Receive PLLs
The function of the onboard PLLs is to align the system data with the line data, which will be at a slightly higher rate
owing to the addition of the overhead bits. There are two PLLs on the receive path. The input to the first PLL,
RX1_PLL (see Figure 3), is the divided down lowest-order clock from the demultiplexer. The RX1_PLL generates a
clock with a user-defined frequency ratio of M/N to the divided clock. This clock would generally be used to compensate for different data rates due to overhead bits. M and N can independently be set from 1 to 40. This PLL is
suitable for low m/n ratios and has been optimized specifically for m=1 and n=1 ratios. See Lattice technical note
number TN1014, ORCA Series 4 FPGA PLL Elements, for detailed HPPLL specifications.
14
Lattice Semiconductor
ORCA ORLI10G Data Sheet
The RX2_PLL also takes its input from the divided down clock and is used to provide a balanced, divided clock
across the FPGA-embedded core interface.
The RX2_PLL has a feedback path that compensates for routing delays to the embedded core/FPGA logic interface for minimum clock skew.
In addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period.
The selection of the deMUX width (and corresponding clock division value), the RX1_PLL M and N values, and the
additional skew for RX1_PLL and RX2_PLL are specified by the user in a GUI interface provided in the ORLI10G
design kit.
A detailed block diagram of the receive path in shown in Figure 4.
Figure 4. ORLI10G Embedded Core Receive Path Diagram
ORLI10G CORE
FPGA LOGIC
DATA
RX_DAT_IN
16
CLOCK
RX_CLK_IN
4
128 TO 16 MUX
OR
64 TO 16 MUX
DIVIDE BY 8 MODE
DIVIDE BY 4 MODE
RX_DAT_OUT[127:96]
RX_DAT_OUT[111:96]
RX_DAT_OUT[95:64]
RX_DAT_OUT[79:64]
OR
RX_DAT_OUT[63:32]
RX_DAT_OUT[47:32]
RX_DAT_OUT[31:0]
RX_DAT_OUT[15:0]
RX_ENB_OUT[3:0]
RX_ENB_OUT[3:0]
10G OR
2.5G
BOTH MODES
RX_CLK8_OUT[0]
DIV BY 8
OR
DIV BY 4
DIV BY 8
OR
DIV BY 4
RX_CLK8_OUT[1]
DIV BY 8
OR
DIV BY 4
RX_CLK8_OUT[2]
DIV BY 8
OR
DIV BY 4
RX_CLK8_OUT[3]
RX1_PLL
(M/N)
RX1_VCOP (X M/N CLOCK)
RX_LOCK
RX2_PLL
(X1)
RX2_VCOP (X 1 CLOCK)
RX2_FBCKI
15
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Transmit Path Details
In the transmit path, the ORLI10G embedded core can be broken down into three sections: the multiplexer, the
transmit side onboard PLLs, and the high-speed line interface. Note that both transmit and receive PLLs are in
addition to the four Programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
MUX
The multiplexer takes data from the FPGA logic and multiplexes the data to rates for transfer by the high speed line
interface. The multiplexer supports two modes of operation:
• Multiplex-by-8
– The multiplexer converts the incoming 128 bits of data at 78 Mbits/s to 106 Mbits/s into 16 bits at 622 Mbits/s
to 850 Mbits/s. The incoming transmit reference clock is divided by 8 for connection to the internal FPGA
logic.
• Multiplex-by-4
– The multiplexer converts the incoming 64 bits of data at 156 Mbits/s to 212 Mbits/s into 16 bits at 622 Mbits
to 850 Mbits/s. The transmit reference clock is divided by 4 for connection to the internal FPGA logic.
Onboard Transmit PLLs
The function of the onboard PLLs is to align the system data with the line data, which will be at a slightly higher rate
owing to the addition of the overhead bits. There are two PLLs on the transmit path. The input to the first PLL,
TX1_PLL (see Figure 4), is the divided down transmit reference clock from the multiplexer. The TX1_PLL generates
a clock with a user-defined frequency ratio of M/N to the divided clock. This clock would generally be used to compensate for different data rates due to overhead bits. M and N can be independently set from 1 to 40. This PLL is
suitable for low m/n ratios and has been optimized specifically for m=1 and n=1 ratios. See Lattice technical note
number TN1014, ORCA Series 4 FPGA PLL Elements, for detailed HPPLL specifications.
The TX2_PLL also takes its input reference from the divided down reference clock and is used to provide a balanced divided clock across the FPGA-embedded core interface.
The TX2_PLL has a feedback path that compensates for routing delays to the embedded core/FPGA logic interface
for minimum clock skew.
In addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period.
The selection of the MUX width (and corresponding clock division value), the TX1_PLL M and N values, and the
additional skew for TX1_PLL and TX2_PLL are specified by the user in a GUI interface provided in the ORLI10G
design kit.
A detailed block diagram of the transmit path in shown in Figure 4. Either TX1_VCOP, TX1_VCO, TX2_VCOP, or
TX2_VCO must be used to clock TX_DAT_IN[127:0] that is transmitted to the embedded block since this interface
must be frequency locked to the divided version of the reference clock. These PLLs can also be bypassed, where
the divided transmit reference clock is sent directly to the FPGA. TX_CLK8_IN[3:0] can be used to clock data transmitted to the embedded block, but the preferred method is to use the internally generated clocks as described
above. If TX_CLK8_IN[3:0] are used, they must also be frequency locked to the reference clock and are thus also
required to be driven by TX1_VCOP, TX1_VCO, TX2_VCOP, or TX2_VCO.
Line Interface
In the transmit path, 16-bit data and associated clocks are outputs from the line interface. Typical data rates are
expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS output data bus is actually composed of four 4-bit data buses with one clock for each 4-bit data bus. On the transmit side, these clocks will
all be synchronized. The ORLI10G uses LVDS (Low-Voltage Differential Signaling) drivers/receivers, which are
intended to provide point-to-point connection between the ORLI10G and optical transceiver (MUX/deMUX) parts.
16
Lattice Semiconductor
ORCA ORLI10G Data Sheet
The LVDS drivers are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS drivers
are terminated with a 100 Ω resistor to improve performance.
The transmit line interface on the ORLI10G can connect to devices that are compliant to either the XSBI standard
or the SFI-4 standard. The major difference for these standards is that for XSBI, the least significant bit [0] is transferred first after serialization by the external MUX device, whereas SFI-4 transmits the most significant bit first. In
some cases, bits [15:0] on the ORLI10G should connect to bits [0:15] on the device to which the ORLI10G device
interfaces. An example of this is the PCS IP core in the ORLI10G when the ORLI10G is connected to an XSBI version 2.1 device.
It should be noted that IEEE 802.3ae version 3.1 to D3.4 (version D3.4 is the latest draft version of this specification as of the writing of this data sheet) swaps XSBI so that the most significant bit is transferred first, thus requiring
that bits [0:15] on the ORLI10G be connected directly to bits [0:15] on the XSBI device.
Figure 5. ORLI10G Embedded Core Transmit Path Diagram
FPGA LOGIC
DIVIDE BY 8 MODE
TX_DAT_IN[127:96]
ORLI10G CORE
DIVIDE BY 4 MODE
DATA
TX_DAT_OUT
TX_DAT_IN[111:96]
TX_DAT_IN[95:64]
16
TX_DAT_IN[79:64]
128 TO 16 MUX
OR
64 TO 16 MUX
OR
TX_DAT_IN[63:32]
TX_DAT_IN[47:32]
TX_DAT_IN[31:0]
TX_DAT_IN[15:0]
TX_ENB8_IN[3:0]
TX_ENB8_IN[3:0]
CLOCK
TX_CLK8_OUT
4
TRANSMIT REFERENCE
CLOCK
TX_CLK_IN
INTCLK*
EXTCLK
BOTH MODES
TX_CLK8_IN[0]
TX_CLK8_IN[1]
TX_CLK8_IN[2]
TX_CLK8_IN[3]
TX1_PLL
(M/N)
TX1_VCOP (X M/N CLOCK)
TX_LOCK
TX2_PLL
(X1)
TX2_VCOP (X 1 CLOCK)
TX2_FBCKI
Note: TX_ENB8_IN[3:0] and TX_CLK8_IN[3:0] are generally not used. See text for explanation.
* Software controlled, based on chosen mode of operation.
17
DIV BY 8
OR
DIV BY 4
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Demultiplexer (Rx) Detail
The demultiplexer module converts the incoming 16 bits of data at 622 MHz/850 MHz into 128 bits of data at 78
MHz/106 MHz or 64 bits of data at 156 MHz/212 MHz and sends it to the FPGA logic. It has been implemented in
two stages; the first stage converts each incoming bit into a byte stream and the second stage bit interleaves these
bytes into 128/64 bits, depending upon the mode of operation. The low-speed clocks are generated by this block.
These clocks are then driven back to this block from the low-speed clock tree network. Functionally, the demultiplexer architecture consists of three blocks: the serial to parallel conversion, the counters, and the interleaving.
The first stage of the line interface module (demultiplexer) converts each incoming bit of data into a byte stream on
a divided-by-8 clock. The data is first registered on the rising edge of the clock input. The clock dividers also runs
parallel to data shift (serial to parallel) on the rising edge of the input clock. An enable is created when a complete
byte is taken in. This enable signal is used to register the serial-to-parallel converted data at the high-speed input
clock. This ensures that the data can be safely transferred to the low-speed clock. This data is then transferred to
the divided clock, allowing a timing margin of approximately half the divided clock period.
The high-speed demultiplexer converts the incoming data as blocks of bytes. The byte boundaries of incoming data
are unknown and are irrelevant to this module.
This data is then interleaved to the 128/64 bits of output data, depending on the mode of operation (divide-by4/divide-by-8). In 10G mode, the output data is assigned the retimed 128/64 bits of data from the first stage of line
interface registered at the input clock [0]. In 2.5G mode, the output data is assigned four concatenated 32/16 bits of
data from the first stage of line interface registered at input clocks [0 to 3]. The interleaving is done at bit level
because the serial-to-parallel converter operates on bits of incoming data. In 10G mode, it is assumed that all the
incoming 16 bits of data are synchronized to the input clock [0]. This block also generates the clock enables used
by the output line interface (multiplexer) module for registering the data on the high-speed clock. These enables
along with the enables from other clocks are selected through the high-speed clock MUX for the output line interface block.
Figure 6 shows the valid data output bits from the demultiplexer in each of the four modes (divide-by-8, 10G and
2.5G modes, and divide-by-4, 10G and 2.5G modes). Figure 7—Figure 10 show the demultiplexer input data and
clock waveforms and output clock, enable, and data waveforms for all four modes.
18
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 6. Demultiplexer Output Data Structure
128
RX_DAT_OUT
112
16 OR 32
96
RX_DAT_IN
RX_DAT_OUT
16
RX_CLK_IN
4
4 x 4 TO 32 DEMUX
OR
4 x 4 TO 16 DEMUX
80
16 OR 32
64
RX_DAT_OUT
48
16 OR 32
32
RX_DAT_OUT
16
16 OR 32
10G 2.5G
÷8 MODE
UNDEFINED
SINGLE CHANNEL
19
10G 2.5G
÷4 MODE
0
CHANNEL 3
CHANNEL 2
CHANNEL 1
CHANNEL 0
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 7. Demultiplexer Serial-to-Parallel Conversion Divide by 8, 10G Mode
RX_CLK_IN0
RX_CLK8_OUT0
(RX_CLK8_OUT[1:3] = 0)
RX_ENB8_OUT0
(RX_ENB8_OUT[1:3] = 0)
RX_DAT_IN
0 0 4 8 C 1 9 0 8
[15:12]
0
RX_DAT_IN
0 1 5 9 D 3 B 2 A 0
[11:8]
RX_DAT_IN
0 2 6 A E 5 D 4 C 0
[7:4]
RX_DAT_IN
0 3 7 B F 7 F 6 E 0
[3:0]
RX_DAT_OUT
[127:96]
00000000
01234567
0
RX_DAT_OUT
[95:64]
00000000
89ABCDEF
0
RX_DAT_OUT
[63:32]
00000000
13579BDF
0
RX_DAT_OUT
[31:0]
00000000
02468ACE
0
20
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 8. Demultiplexer Serial-to-Parallel Conversion Divide by 4, 10G Mode
RX_CLK_IN0
RX_CLK8_OUT0
(RX_CLK8_OUT[1:3] = 0)
RX_ENB8_OUT0
(RX_ENB8_OUT[1:3] = 0)
RX_DAT_IN
[15:12]
0
0
4
8
C
1
9
0
8
0
RX_DAT_IN
[11:8]
0
1
5
9
D
3
B
2
A
0
RX_DAT_IN
[7:4]
0
2
6
A
E
5
D
4
C
0
RX_DAT_IN
[3:0]
0
3
7
B
F
7
F
6
E
0
RX_DAT_OUT
[63:32]
00000000
01234567
13579BDF
0
RX_DAT_OUT
[31:0]
00000000
89ABCDEF
02468ACE
0
21
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 9. Demultiplexer Serial-to-Parallel Conversion Divide by 8, 2.5G Mode
RX_CLK_IN[0:3]
RX_CLK8_OUT[0:3]
RX_ENB8_OUT[3:0]
RX_DAT_IN
[15:12]
0 0 1 2 3 4 5 6 7
RX_DAT_IN
[11:8]
0 8 9 A B C D E F 0
RX_DAT_IN
[7:4]
0 1 3 5 7 9 B D F 0
RX_DAT_IN
[3:0]
0 0 2 4 6 8 A C E 0
0
RX_DAT_OUT
[127:96]
00000000
01234567
0
RX_DAT_OUT
[95:64]
00000000
89ABCDEF
0
RX_DAT_OUT
[63:32]
00000000
13579BDF
0
RX_DAT_OUT
[31:0]
00000000
02468ACE
0
22
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 10. Demultiplexer Serial-to-Parallel Conversion Divide by 4, 2.5G Mode
RX_CLK_IN[3:0]
RX_CLK8_OUT[3:0]
RX_ENB8_OUT[3:0]
RX_DAT_IN
[15:12]
0
0
1
2
3
4
5
6
7
0
RX_DAT_IN
[11:8]
0
8
9
A
B
C
D
E
F
0
RX_DAT_IN
[7:4]
0
1
3
5
7
9
B
D
F
0
RX_DAT_IN
[3:0]
0
0
2
4
6
8
A
C
E
0
RX_DAT_OUT
[111:96]
0000
0123
4567
0
RX_DAT_OUT
[79:64]
0000
89AB
CDEF
0
RX_DAT_OUT
[47:32]
0000
1357
9BDF
0
RX_DAT_OUT
[15:0]
0000
0246
8ACE
0
23
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Multiplexer (Tx) Detail
The multiplexer module converts the incoming 128 bits of data from the FPGA logic at 78 MHz/106 MHz or
64 bits of data from the FPGA logic at 156 MHz/212 MHz into 16 bits of data at 622 MHz/850 MHz. It has been
implemented as two stages. The first stage deinterleaves each incoming byte into a different byte stream that can
be serially output on the output data pins. The second stage outputs these bytes into 16 bits or four groups of 4 bits,
depending upon the mode of operation. Functionally, the multiplexer architecture consists of three blocks: the parallel-to-serial conversion, the counters, and the deinterleaving.
Two options are available for the transmit clocks. The clock signals TX_CLK_IN[3:0] can be used to transfer data to
the internal core or an internal clock can be used. The preferred method is to use the internal clock. Two options
are also available for the enable signals. The enable signals TX_ENB8_IN[3:0] can be used or they can be generated internally. The preferred method is to use the internal enables.
For divide-by-8 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a
different byte stream on the 78 MHz/106 MHz (TX_CLK8_IN[3:0] or internal) clock. This data is then registered on
the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 78 MHz/106 MHz clock. The
enable inputs (TX_ENB8_IN[3:0] or internal) are used to transfer data from the low-speed clock to the high-speed
clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed
clock. Generally, these enables are generated in the embedded core and the TX_ENB8_IN[3:0] signals to the
embedded core are not used.
For divide-by-4 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a
different byte stream on the 156 MHz/212 MHz (TX_CLK8_IN[3:0] or internal) clock. This data is then registered on
the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 156 MHz/212 MHz clock.
The enable inputs (TX_ENB8_IN[3:0] or internal) are used to transfer data from the low-speed clock to the highspeed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the highspeed clock. Again, both TX_CLK8_IN[3:0] and TX_ENB8_IN[3:0] are not generally used.
The enable inputs (TX_ENB8_IN[3:0]) are required to be four (divide by 4) or eight (divide by 8) TX_CLK_IN clock
cycles wide. If they are used, they have to be synchronous to their corresponding TX_CLK8_IN[3:0] clock. Each of
these four TX_CLK8_IN[3:0] clocks must also be frequency locked to the TX_CLK_IN signal.
The TX_CLK_OUT[3:0] clock outputs from the ORLI10G are provided for transferring each 4 bits of data per clock.
All data to be transmitted to the embedded core must be frequency locked to the TX_CLK_IN signal. Thus, the
divided version of this clock found at the embedded core interface should always be used to transfer data from the
FPGA logic to the embedded core. These clock signals are available from the TX PLL outputs (TX1_VCO,
TX1_VCOP, TX2_VCO, TX2_VCOP). Figure 11 shows the valid data input bits to the multiplexer in each of the four
modes (divide-by-8 and divide-by-4 modes). Figure 12— Figure 15 show the multiplexer input transmit reference
clock, data, enable, and clock waveforms and output clock and data waveforms for all four modes.
24
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 11. Multiplexer Input Data Structure
128
112
TX_DAT_IN
96
16 OR 32
80
TX_DAT_IN
TX_DAT_OUT
64
48
32
16
0
÷8 MODE
UNDEFINED
SINGLE CHANNEL
16 OR 32
TX_DAT_IN
16 OR 32
TX_DAT_IN
16 OR 32
÷4 MODE
CHANNEL 3
CHANNEL 2
CHANNEL 1
CHANNEL 0
25
16
4 x 4 TO 32 MUX
OR
4 x 4 TO 16 MUX
TX_CLK_OUT
4
TRANSMIT
REFERENCE
CLOCK
TX_CLK_IN
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 12. Multiplexer Parallel-to-Serial Conversion Divide by 8, 10G Mode
TX_CLK_IN
TX_CLK8_OUT[3:0]
TX_ENB8_IN0
TX_DAT_IN
[127:96]
00000000
01234567
0
TX_DAT_IN
[95:64]
00000000
89ABCDEF
0
TX_DAT_IN
[63:32]
00000000
13579BDF
0
TX_DAT_IN
[31:0]
00000000
02468ACE
0
TX_DAT_OUT
[15:12]
0
0 4 8 C 1 9 0 8 0
TX_DAT_OUT
[11:8]
0
1 5 9 D 3 B 2 A 0
TX_DAT_OUT
[7:4]
0
2 6 A E 5 D 4 C 0
TX_DAT_OUT
[3:0]
0
3 7 B F 7 F 6 E 0
Note: TX_ENB8_IN0 is generally not used because the enable is created internal to the embedded core, but is shown for reference
26
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 13. Multiplexer Parallel-to-Serial Conversion Divide by 4, 10G Mode
TX_CLK_IN
TX_CLK_OUT[3:0]
TX_ENB8_IN0
TX_DAT_IN
[63:32]
00000000
01234567 13579BDF
0
TX_DAT_IN
[31:0]
00000000
89ABCDEF 02468ACE
0
TX_DAT_OUT
[15:12]
0
0 4 8 C 1 9 0 8 0
TX_DAT_OUT
[11:8]
0
1 5 9 D 3 B 2 A 0
TX_DAT_OUT
[7:4]
0
2 6 A E 5 D 4 C 0
TX_DAT_OUT
[3:0]
0
3 7 B F 7 F 6 E 0
Note: TX_ENB8_IN0 is generally not used because the enable is created internal to the embedded core, but is shown for reference
27
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 14. Multiplexer Parallel-to-Serial Conversion Divide by 8, 2.5G Mode
TX_CLK_IN
TX_CLK8_OUT[3:0]
TX_CLK8_IN[3:0]
TX_ENB8_IN[3:0]
TX_DAT_IN
[127:96]
00000000
01234567
0
TX_DAT_IN
[95:64]
00000000
89ABCDEF
0
TX_DAT_IN
[63:32]
00000000
13579BDF
0
TX_DAT_IN
[31:0]
00000000
02468ACE
0
TX_DAT_OUT
[15:12]
0
0 1 2 3 4 5 6 7
0
TX_DAT_OUT
[11:8]
0
8 9 AB C D E F
0
TX_DAT_OUT
[7:4]
0
1 3 5 7 9 B D F
0
TX_DAT_OUT
[3:0]
0
0 2 4 6 8 A C E
0
Note: TX_CLK8_IN[3:0] and TX_ENB8_IN[3:0] are generally not used because the clocks and enables are created internal to the embedded
core, but are shown for reference
28
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 15. Multiplexer Parallel-to-Serial Conversion Divide by 4, 2.5G Mode
TX_CLK_IN
TX_CLK_OUT[3:0]
TX_CLK8_IN[3:0]
TX_ENB8_IN[3:0]
TX_DAT_IN
[111:96]
0000
0123
4567
0
TX_DAT_IN
[79:64]
0000
89AB
CDEF
0
TX_DAT_IN
[47:32]
0000
1357
9BDF
0
TX_DAT_IN
[15:0]
0000
0246
8ACE
0
TX_DAT_OUT
[63:32]
0
0 1 2 3 4 5 6 7 0
TX_DAT_OUT
[31:0]
0
8 9 A B C D E F 0
TX_DAT_OUT
[63:32]
0
1 3 5 7 9 B D F 0
TX_DAT_OUT
[31:0]
0
0 2 4 6 8 A C E 0
Note: TX_CLK8_IN[3:0] and TX_ENB8_IN[3:0] are generally not used because the clocks and enables are created internal to the embedded
core, but are shown for reference
29
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Embedded PLLs
The ORLI10G embedded (transmit and receive) PLLs are based on the 4E series FPGA High-Speed Programmable PLL (HPPLL). The 4E PLL consists of a Phase/Frequency Detector (PFD), a charge pump/filter, a multitap Voltage Controlled Oscillator (VCO), a duty cycle synthesis circuitry, a power regulator, two programmable dividers,
phase shift selector multiplexers, a lock signal generator, and a current DAC. A block diagram of the programmable
PLL is shown in Figure 16. The receive path RX1_PLL and transmit path TX1_PLL, which can be programmed to
create a N/M frequency clock, are based on this design.
The receive path RX2_PLL and transmit path TX2_PLL create a X1 clock. This is essentially the same PLL without
the M and N divider.
The RCKI input to the PLLs comes from an input clock to the ORLI10G that has been divided in frequency by either
4 or 8 (programmable). As shown in Figure 4, RX1_PLL and RX2_PLL are driven by the divided version of
RX_CLK_IN0. As shown in Figure 5, TX1_PLL and TX2_PLL are driven by the divided versions of TX_CLK_IN. It
should be noted that the speed of the ORLI10G line interface is therefore either 4x or 8x the operating speed of the
embedded PLLs.
The clock feedback loops for the RX2_PLL and TX2_PLL should be routed from the clock network in the FPGA
core to compensate for the routing delays to the FPGA logic interface. The source to the TX2_FBCKI or
RX2_FBCKI inputs must come from an FPGA clock network driven by the VCO output (otherwise, any phase shifting on VCOP is removed by the feedback loops). In this way, the clock skew at the embedded core/FPGA logic
boundary is zero for the receive and transmit PLLs. The VCOP ports are available at the embedded core/FPGA
interface. The VCO ports are not available.
All PLLs include a phase shift selector which allows phase shift adjustments of each clock in increments of 1/8 the
period of the clock. This phase shifted output is available on the VCOP output of the PLL. All functions of the
embedded core PLLs are user controlled through a GUI provided with the ORLI10G design kit software.
Figure 16. ORLI10G Programmable PLL Block Diagram
RCKO
RCKI
M
DIVIDER
LOCK
GENERATOR
LOCK
VCOP
M<5:0>
PFD
N<5:0>
TX2_FBCKI
RX2_FBCKI
CHARGE PUMP
AND FILTER
VCO
PHASE
SELECT
VCO
N
DIVIDER
SEL<2:0>
BYPASS
30
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Embedded Programmable PLLs Specifications
Table 2. Programmable PLL Specifications
Parameters
VDD15
VDD33
Operating Temperature (TA)
Input Clock Frequency
Input Duty Cycle
Output Clock Frequency
Output Duty Cycle
Lock Time
Frequency Multiplication (TX1_PLL and RX1_PLL)
Frequency Division (TX1_PLL and RX1_PLL)
Duty Cycle Adjust of Output Clock(s)
Delay Adjust of Output Clock
Phase Shift Between VCO and VCOP
Min
1.425
3.0
–40
60
30
7.5
45
—
Nom
Max
1.5
1.575
3.3
3.6
—
125
—
420
—
70
—
420
50
55
<50
—
2x, 3x, 4x, 5x, 6x, 7x, 8x
1/8x, 1/7x, 1/6x, 1/5x, 1/4x, 1/3x, 1/2x
12.5, 25, 37.5, 50, 62.5, 75, 87.5
0, 45, 90, 135, 180, 225, 270, 315
0, 45, 90, 135, 180, 225, 270, 315
Unit
V
V
˚C
MHz
%
MHz
%
µs
—
—
%
degrees
degrees
Notes:
Multiplication and division values can both be used on one PLL output (example 3/4x).
For more information about the HPPLL, see the Series 4 PLL Application Note.
ORLI10G Reset Requirements
Both the embedded core portion and the FPGA portion are reset at powerup. The embedded core is also reset, as
shown in Table 3, based on other conditions. All resets to the core can either be asynchronous or asynchronous on
with a synchronous release. Asynchronous resets must be held in reset for at least 8 ns. Two signals from the
FPGA logic can also reset the embedded core: the global set/reset (GSRN) which can be inhibited, and a signal
routed from the FPGA general routing (FPGA_RESET). Both of these affect both the TX and RX reset simultaneously. Table 3 also shows the conditions upon which the I/O are 3-stated.
Reset of PLL blocks directly affects only the digital logic. For the PLL_RX2 and PLL_TX2 (x1) PLLs, the VCOP output from the PLL should be in the 3-6MHz range during reset. For PLL_RX1 and PLL_TX1 (xM/N) PLLs using the
M and N counters, the VCO will go to the low state. Coming out of reset will require about 25 microseconds for the
PLLs to become stable.
Table 3. ORLI10G Reset Requirements
Condition
Powerup
FPGA Configuration
FPGA GSRN
FPGA_RESET Signal
TS_ALL Pin = 1
RESET_TX Pin = 1
RESET_RX Pin = 1
PWRON Pin = 1
TX MUX Block
Reset
Reset
Reset
Reset
—
Reset
—
—
TX PLL
Reset
Reset
—
—
—
Reset
—
Powerdown
31
RX DeMUX Block
Reset
Reset
Reset
Reset
—
—
Reset
—
RX PLL
Reset
Reset
—
Reset
—
—
Reset
Powerdown
Embedded I/O
3-state
Active
Active
Active
3-state
Active
Active
Active
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Typically, the following reset sequence should be followed for the ORLI10G:
• Place the device in reset by driving RESET_TX = 1 and RESET_RX = 1 (or FPGA_RESET signal = 1), and by
placing the FPGA portion into reset.
• Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0 and FPGA_RESET
signal = 0).
• Release the FPGA portion from reset.
Line Interface Circuit Specifications
Power Supply Decoupling LC Circuit
The 622 MHz—850 MHz line interface macro contains both analog and digital circuitry. The line interface function,
for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop
to provide its divided clocks. The internal analog phase-locked loop contains a voltage-controlled oscillator. This circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the bandwidth of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit elements.
Additional power supply filtering in the form of an LC π filter section will be used between the power supply source
and these device pins as shown in Figure 17. The corner frequency of the LC filter is chosen based on the power
supply switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitor C1 is a large electrolytic capacitor to provide the basic cut-off frequency of the LC filter. For example, the
cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitors C2 and C3
are smaller ceramic capacitors designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the
device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended filter for
the HSI macro is shown below: L= 4.7 µH, RL < 1Ω, C1 = 4.7 µF, C2 = 0.01 µF, C3 = 0.01 µF.
Figure 17. Sample Power Supply Filter Network for Analog LI Power Supply Pins
FROM POWER
SUPPLY SOURCE
+
L
TO DEVICE
VDDA_[7:4]
C1
+
C2
+
C3
VSSA_[7:4]
32
Lattice Semiconductor
ORCA ORLI10G Data Sheet
XGMII ORCA 4E Receive Analysis
XGMII Considerations
The stringent 10 Gbit Media Independent Interface (XGMII) specifications from the IEEE 802.3ae standards are
met in the FPGA side of the ORLI10G device. This interface is implemented in the PCS IP core and targeted to the
ORLI10G FPSC. Figure 18 shows a simplified block diagram for the XGMII interface. Other I/O standards are also
possible, such as SSTL or HSTL, with a reference voltage of 1.8 V. Further details are available in the Series 4 I/O
application note and the Series 4 Fast Input DDR and Output DDR with Clock Forwarding Application Note.
The ORLI10G device meets the 480 ps input setup time and 480 ps input hold time requirements for the XGMII
receiver inputs into the FPGA side of the FPSC with the embedded I/O DDR cells on the FPGA side of the FPSC.
The PLLs are not used on input because this is a forward clocked interface. The ORLI10G meets the clock-to-out
specification on the XGMII DDR outputs by using the output shift register to produce a non-duty-cycle-dependent
output. An embedded output DDR capability is also available. The output clock is then centered around this data
eye using internal PLLs.
There are two considerations to note about the pinout location of the XGMII input clocks:
1. The XGMII input clocks must be located at the C pad of the programmable I/O cells (PICs). In the pinout tables,
the pads are labeled on a pin-by-pin basis. For example, a pin whose pad is referenced as PL1C can be used
as an XGMII input clock, but pins referenced as PL1A, PL1B, or PL1D cannot be used as an XGMII input clock.
2. The XGMII input data pins can be no further then six PICs away from the XGMII input clock pin.
Figure 18. Simplified XGMII Block Diagram
VDDIO
VDD15
CLOCK
HSTL
VDDIO = 1.5 V NOM
HSTL
VDDIO = 1.5 V NOM
CLOCK
DDR DATA
VREF
VDDIO ÷ 2
CUSTOMER DEVICE
ORLI10G
33
LINE INTERFACE
SYSTEM INTERFACE
DDR DATA
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 4. Absolute Maximum Ratings
Parameter
Storage Temperature
Power Supply Voltage with Respect to Ground
Input Signal with Respect to Ground
Signal Applied to High-impedance Output
Maximum Package Body (Soldering) Temperature
Symbol
TSTG
VDD33
VDDIO
VDD33, VDD33_A
VDD15
VIN
—
—
Min
–65
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
—
Max
150
4.2
4.2
4.2
2.0
VDDIO + 0.3
VDDIO + 0.3
220
Unit
˚C
V
V
V
V
V
V
˚C
Min
3.0
1.4
3.0
1.425
–0.3
–40
Max
3.6
3.6
3.6
1.575
VDDIO + 0.3
125
Unit
V
V
V
V
V
˚C
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Parameter
Power Supply Voltage with Respect to Ground
Input Voltages
Junction Temperature
Symbol
VDD33
VDDIO
VDD33, VDD33_A
VDD15
VIN
TJ
For FPGA Recommended Operating Conditions and Electrical Characteristics, see the Recommended Operating
Conditions and Electrical Characteristics tables in the ORCA Series 4 FPGA data sheet (OR4E04) and the ORCA
Series 4 I/O Buffer Technical Note. FPSC Standby Currents (IDDSB15 and IDDSB33) are tested with the Embedded
Core in the powered down state.
Notes:
The maximum recommended junction temperature (TJ) during operation is 125 ˚C.
Timing parameters in this data sheet are characterized under tighter voltage and temperature conditions than the recommended operating conditions in this table.
The internal PLLs operate from the VDD33 and VDD33_A power supplies. These power supplies should be well isolated from all other power supplies on the board for proper operation.
34
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Embedded Core LVDS I/O
Table 6. Driver dc Data*
Parameter
Output Voltage High, VOA or VOB
Symbol
Test Conditions
Min
Typ
Max
Unit
VOH
RLOAD = 100 Ω
—
—
1.475†
V
V
†
Output Voltage Low, VOA or VOB
VOL
RLOAD = 100 Ω
0.925
—
—
Output Differential Voltage
|VOD|
RLOAD = 100 Ω
0.25
—
0.45†
†
V
Output Offset Voltage
VOS
RLOAD = 100 Ω
1.125*
—
1.275
V
Output Impedance, Differential
RO
VCM = 1.0 V and 1.4 V
80
100
120
Ω
RO Mismatch Between A and B
∆ RO
VCM = 1.0 V and 1.4 V
—
—
25
mV
Change in Differential Voltage
Between Complementary States
|∆ VOD|
RLOAD = 100 Ω
—
—
25
mV
Change in Output Offset Voltage
Between Complementary States
∆ VOS
RLOAD = 100 Ω
—
—
25
mV
Output Current
ISA, ISB
Driver shorted to GND
—
—
24
mA
Output Current
ISAB
Drivers shorted together
—
—
12
mA
| lxa, lxb |
VDD = 0V
VPAD, VPADN = 0 V—2.5 V
—
—
10
mA
Power-off Output Leakage
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 ˚C - 125 ˚C.
† External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%
.
Table 7. Driver ac Data*
Parameter
Symbol
Test Conditions
Min
Max
Unit
tF
ZL = 100 Ω ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
100
210
ps
tR
ZL = 100 Ω ± 1%
CPAD = 3.0 pF, CPAD = 3.0 pF
100
210
ps
Differential Skew:
|tPHLA –tPLHB| or
|tPHLB – tPLHA|
tSKEW1
Any differential pair on package at
50% point of the transition
—
50
ps
Channel-to-channel Skew:
|tpDIFFm – tpDIFFn|
tSKEW2
Any two signals on package at
0 V differential
—
—
ps
VOD Fall Time, 80% to 20%
VOD Rise Time, 20% to 80%
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 ˚C - 125 ˚C.
Table 8. Receiver dc Data*
Parameter
Input Voltage Range, VIA or VIA
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
Symbol
Test Conditions
Min
Typ
Max
Unit
VI
| VGPD| < 925 mV
dc – 1 MHz
0.0
1.2
2.4
V
VIDTH
| VGPD| < 925 mV
400 MHz
–100
—
100
mV
VHYST
(+VIDTHH) – (–VIDTHL)
25
—
—†
mV
RIN
With build-in termination, centertapped
80
100
120
W
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 ˚C - 125 ˚C.
† External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%.
35
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 9. LVDS Operating Parameters
Parameter
Test Conditions
Min
Normal
Max
Unit
Transmit Termination Resistor
—
80
100
120
W
Receiver Termination Resistor
—
80
100
120
W
Temperature Range (TJ)
—
– 40
—
125
°C
Power Supply VDD33
—
3.1
—
3.5
V
Power Supply VDD15
—
1.4
—
1.6
V
Power Supply VSS
—
—
0
—
V
Note: Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time
without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage. The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
36
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Timing Characteristics
Receive Input Data Interface
Receive STS-48/STS-192 (2.5G/10G) Data Inputs
Figure 19 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are Low
Voltage Differential Signal (LVDS) input buffers. The expected clock rate is 622 MHz—850 MHz, and the receive
data is clocked on the rising edge of the clock. In 2.5G mode, each of the four channels uses one set of one
RX_CLK_INn and four RX_DAT_INn data pins. In 10G mode, only RX_CLK_IN0 is used, along with the
RX_DAT_IN[15:0] pins. The timing values for the diagram in Figure 19 are given in Table 10.
Figure 19. Receive Input Data Timing
t1
RX_CLK_IN_P[3:0]
RX_CLK_IN_N[3:0]
t2
t3
RX_DAT_IN_N[15:0]
RX_DAT_IN_P[15:0]
Table 10. Receive Data Input Timing
–1
Parameter
Clock Frequency
–2
–3
Symbol
Min
Max
Min
Max
Min
Max
Units
t1
—
667
—
790
—
850
MHz
Data Setup Time Required
t2
300
—
300
—
300
—
ps
Data Hold Time Required
t3
150
—
150
—
150
—
ps
Note: Characterized at VDD33 = 3.1V – 3.5V, VDD15 = 1.425V – 1.575V, Tj = -40° C to 125°C, clock and data minimum rise/fall time of 100ps.
Slower rise/fall times will increase setup/hold time requirements.
• It is recommended that the Rx clock be inverted by crossing the LVDS pin pair, that is, connect the
RX_CLK_IN_P[3:0] input signal on the ORLI10G to the N (i.e., complement) clock output from the transmitting
device and connect the RX_CLK_IN_N[3:0] input on the ORLI10G to the P (i.e., true) clock output from the transmitting device. This is because the embedded line interface on the ORLI10G requires the Rx data to be centered
on the Rx clock, and typically the devices that drive the ORLI10G transmit clock and data on the same clock
edge.
37
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Transmit STS-48/STS-192 (2.5G/10G) Data Outputs
Figure 20 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are
driven with Low-Voltage Differential Signal (LVDS) output buffers. The expected clock rate is 622 MHz-850 MHz
and the transmit data is clocked out on the rising edge of the clock. In 2.5G mode, each of the four channels uses
one set of TX_CLK_OUTn with four TX_DAT_OUTn data pins. In 10G mode, only TX_CLK_OUT[0] is used with the
16 TX_DAT_OUT[15:0] pins. The timing values for the diagram in Figure 20 are given in Table 11.
Figure 20. Transmit Output Data Timing
t4
TX_CLK_OUT_N[3:0]
TX_CLK_OUT_P[3:0]
t5
TX_DAT_OUT_P[15:0]
TX_DAT_OUT_N[15:0]
t6
t7
Table 11. Transmit Data Output Timing
–1
Parameter
–2
–3
Symbol
Min
Max
Min
Max
Min
Max
Unit
Clock Frequency
t4
—
667
—
790
—
850
MHz
Duty Cycle
—
45
55
45
55
45
55
%
Data Delay from Clock Edge
t5
125
450
125
450
125
450
ps
Data Rise Time: 20%—80%
t6
100
200
100
200
100
200
ps
Data Fall Time: 80%—20%
t7
100
200
100
200
100
200
ps
Note: This requirement is for all sources of the output clocks (e.g., RCLKSI, etc.). Characterized at VDD33 = 3.1V – 3.5V, VDD15 = 1.425V –
1.575V, Tj = -40°C to 125°C.
For SFI-4/XSBI applications, the TX_CLK_OUT clock should be delayed external to the device, with respect to the
TX_DAT_OUT data, by 325 ps. Delaying the TX_CLK_OUT clock will produce an SFI-4/XSBI compliant clock to
data skew relationship of +/- 200 ps.
It is recommended that the Tx clock be inverted by crossing the LVDS pin pair, that is, connect the
TX_CLK_OUT_P[3:0] output on the ORLI10G to the N (i.e., complement) clock input on the receiving device and
connect the TX_CLK_OUT_N[3:0] output on the ORLI10G to the P (i.e., true) clock input on the receiving device.
This is because the receiving device that will be driven by the ORLI10G typically requires that data be centered
around the clock, but the ORLI10G drives both the clock and data from the same clock edge.
38
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Recommended Board Level Routing For ORLI10G XSBI 10G Interface
The Transmit XSBI port sends clock and data simultaneously as shown in Figure 21.
Figure 21. Clock and Data signals from the TX
t period = 1500pS
CLOCK
DATA
N
P
N
P
The correct clock and data relation required for the XSBI receiver is to have the clock centered in the data eye (as
shown in Figure 22).
Figure 22. Clock and Data Signals at the Receiver
CLOCK
DATA
P
N
N
P
In order to achieve the needed clock and data relationship at the receiver as shown in Figure 21, it is necessary to
swap the P and N clock terminals on the board. This is illustrated in Figure 23. The board level signal swap on the
receiver clock pins effectively inverts the clock phase at the receiving chip creating the correct clock data relationship shown in Figure 22.
39
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 23. Implementing Clock Wire Swap
Wire swap
implemented on
customer board
TX
CLOCK
DATA
RX
P
P
N
N
P
P
N
N
CLOCK
DATA
The above describes standard practice for XSBI 10G Interfaces.
40
Lattice Semiconductor
ORCA ORLI10G Data Sheet
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100 Ω differential impedance, as shown below. External resistors are
not required. The differential receiver buffers include termination resistors inside the device package, as shown in
Figure 24.
Figure 24. LVDS Driver and Receiver and Associated Internal Components
LVDS DRIVER
LVDS RECEIVER
VDDD = 3.3 V
~ 14 k Ω
50 Ω
CENTER TAP
50 Ω
.01 µF
EXTERNAL
DEVICE PINS
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an
unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to
ground, the LVDS driver will not suffer permanent damage. Figure 25 illustrates the terms associated with LVDS
driver and receiver pairs.
Figure 25. LVDS Driver and Receiver
DRIVER
INTERCONNECT
RECEIVER
VOA
A
AA
VIA
VOB
B
BB
VIB
VGPD
Figure 26. LVDS Driver
CA
VOA
A
RLOAD
VOB
B
V
CB
41
VOD = (VOA – VOB)
Lattice Semiconductor
ORCA ORLI10G Data Sheet
ORLI10G Interface Timing Diagrams
This section describes the timing at the FPGA – Core boundary. There are 4 distinct timing modes available for use
with the ORLI10G device (note that for TX, 10G mode can be used for either 10G or 2.5G operation):
• 10G RX and TX with PLL used across the interface.
• 10G RX and TX with NO PLL used across the interface.
• Quad 2.5G RX with NO PLL used across the interface plus 10G TX with PLL used across the interface.
• Quad 2.5G RX with NO PLL used across the interface plus 10G TX with NO PLL used across the interface.
Figure 27 shows a simplified, single channel view of the transmit path in divide-by-four mode. The divide-by-8
mode timing is similar, where the slow speed clocks are 1/8th the fast clock speed. PLL_TX2 is used to align clocks
across the Embedded Line Interface – FPGA boundary. The PLL_TX1 macro can optionally be used for phase control or to adjust the m/n ratios. The PLLs in the embedded line interface can be bypassed via the PLL_BYPASS
external FPSC pin. The feedback loop shown is connected up automatically by the design kit software.
Figure 27. Single Channel Tx Divide-by-4 Diagram (-1 Speed Grade)
Optional*
*See Onboard Transmit PLLs in Transmit
Path Details section for detailed information.
PLL_TX1
TX2_VCOP
161 MHz
3ns
PLL_TX2
TX_CLK_IN[P/N]
Clock
Divider
/4
644MHz
TX2_FBCKI
Primary
FPGA Clock
Tree
Core Clock
Trees
TX_CLK_OUT
[0][P/N]
TX_DAT_IN[15:0]
data
D
Q
TX_DAT_OUT
[3:0][P/N]
Low Speed
Q
High Speed
Multiplexer Block
FPGA
Embedded Line Interface Core
42
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 28 shows the Transmit (FPGA to embedded Line Interface) timing for 10G mode where PLL_TX2 is used to
align clocks across the FPGA - Core boundary. The 1.9 ns hold time shown is an approximate hold time value for
the embedded line interface. Consult the ispLEVER software, via the static timing analysis tool TRACE, for the
exact timing values. Figure 28. shows a full cycle transfer. Designers should make sure to satisfy the hold requirement.
Figure 28. Transmit Timing for 10G Mode with PLL for Clock Alignment (-1 Speed Grade)
TX_CLK_IN
(644 MHz)
TX_DAT_IN
Q
D
TX_CLK8_IN_BUF
1.6ns
Primary
FPGA Clock
Tree
0.5ns
TX2_VCOP
3ns
PLL_TX2
TX2_FBCKI
FPGA
Embedded Line Interface Core
0.0ns
3.1ns
6.2ns
9.3ns
12.4ns
0.0ns
3.1ns
6.2ns
9.3ns
12.4ns
TX2_FBCKI
(Reference Clock)
FPGA Clock
Launch
1.1ns
4.2ns
7.3ns
TX_CLK8_IN_BUF
10.4ns
Capture
Data
Valid Data Window
0.0ns Setup
1.9ns Hold
43
13.5ns
Clock
Divider
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 29 shows the Transmit (FPGA to embedded Line Interface) timing for 10G mode where PLL_TX2 is
bypassed via the PLL_BYPASS external FPSC pin. The 0.4 ns setup time and the 1.1 ns hold time shown are
approximate values for the embedded line interface. Consult the ispLEVER software, via the static timing analysis
tool TRACE, for the exact timing values. Figure 29 shows a half cycle transfer. Designers should make sure to satisfy the hold requirement. A full cycle transfer is also possible for this scenario when the clock period is 10 ns or
longer (< 100 MHz).
Figure 29. Transmit Timing for 10G Mode with PLL Bypassed (-1 Speed Grade)
TX_CLK_IN
(644 MHz)
TX_DAT_IN
Q
D
TX_CLK8_IN_BUF
1.6ns
Primary
FPGA Clock
Tree
1.3ns
TX2_VCOP
3ns
PLL_TX2
(Bypass Mode)
FPGA
0.0ns
Embedded Line Interface Core
3.1ns
6.2ns
9.3ns
12.4ns
TX2_VCOP
(Reference Clock)
-0.1ns
FPGA Clock
3.0ns
6.1ns
9.2ns
12.3ns
Launch
0.3ns
3.4ns
6.5ns
TX_CLK8_IN_BUF
9.6ns
Capture
Data
0.4ns Setup
1.1ns Hold
44
12.7ns
Clock
Divider
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 30 shows a simplified, single channel view of the receive path in divide-by-four mode. The divide-by-8 mode
timing is similar, where the slow speed clocks are 1/8th the fast clock speed. If a primary clock is used in the FPGA,
PLL_RX2 is used to align clocks across the embedded ASIC – FPGA boundary. If the secondary clock is used in
the FPGA, PLL_RX2 is not and there is a 1.0 ns to 3.5 ns clock insertion delay incurred on the secondary clocks.
The quad 2.5 G mode requires four secondary clocks to be used, one for each 2.5 G channel. The PLL_RX1 macro
can optionally be used for phase control or to adjust the m/n ratios. The PLLs in the embedded line interface can be
bypassed via the PLL_BYPASS external FPSC pin. The feedback loop shown is connected up automatically by the
design kit software. The Mode select on the clock multiplexer in the embedded line interface is also connected up
automatically by the design kit software. If in 10G mode, one clock is used and corresponds to the RX_CLK_IN[0]
external device pin.
Figure 30. Single-Channel Rx Divide-by-4 Diagram (-1 Speed Grade)
*See Onboard Receive PLLs in Receive
Path Details section for detailed information.
Optional*
PLL_RX1
RX2_VCOP
RX_CLK_IN
[3:0] [P/N]
Clock
Divider
/4
644 MHz
3ns
161 MHz
PLL_RX2
RX2_FBCKI
4
Quad 2.5G or
Single 10G
Mode
Primary
FPGA Clock
Tree
Secondary
FPGA Clock
Core Clock
Trees
1.0 ns
RX_DAT_IN
[3:0][P/N]
D
High Speed
data
to 3.5 ns
RX_DAT_IN[15:0]
Q
Low Speed
D
Demultiplexer Block
Embedded Line Interface Core
FPGA
45
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 31 shows the Receive (Embedded Line Interface to FPGA) timing for 10G mode where PLL_RX2 is used to
align clocks across the FPGA - Core boundary. The 0.9 ns minimum propagation delay and 2.7 ns maximum propagation delay shown are approximate values for the embedded line interface. In the waveform shown, data will be
time shifted at the FPGA capture register due to FPGA data path delay. Consult the ispLEVER software, via the
static timing analysis tool TRACE, for the exact timing values. Figure 31 shows a full cycle transfer.
Figure 31. Receive Timing for 10G Mode with PLL for Clock Alignment (-1 Speed Grade)
RX_CLK_IN[0]
(644 MHz)
RX_DAT_IN
D
Q
RX_CLK8_IN_MUX1
1.4ns
Primary
FPGA Clock
Tree
RX2_VCOP
3ns
PLL_RX2
RX2_FBCKI
FPGA
Embedded Line Interface Core
0.0ns
3.1ns
6.2ns
9.3ns
0.0ns
3.1ns
6.2ns
9.3ns
12.4ns
RX2_FBCKI
(Reference Clock)
FPGA Clock
Capture
Hold
1.4ns
RX_CLK8_IN_MUX1
12.4ns
4.5ns
7.6ns
Launch
Data
0.9 ns Tpd_min
2.7 ns Tpd_max
46
10.7ns
13.8ns
Clock
Divider
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 32 shows the Receive (Embedded Line Interface to FPGA) timing for 10G mode where PLL_RX2 is
bypassed via the PLL_BYPASS external FPSC pin. The 0.7 ns minimum propagation delay and 1.9 ns maximum
propagation delay shown are approximate values for the embedded line interface in this scenario. In the waveform
shown, data will be time shifted at the FPGA capture register due to FPGA data path delay. Consult the ispLEVER
software, via the static timing analysis tool TRACE, for the exact timing values. Figure 32 shows a half cycle transfer; note the inversion bubble on the FPGA capture register. This half cycle transfer negates possible hold timing
issues. If a full cycle transfer is used with the receive PLL bypassed, check for hold violations with the static timing
analysis tool TRACE. In 2.5G mode, RX_CLK must be routed on secondary clock resources. Primary clock routing
will induce undesirable clock insertion delays.
Figure 32. Receive Timing for 10G Mode with PLL Bypassed (-1 Speed Grade)
RX_CLK_IN[0]
(100 MHz)
RX_DAT_IN
D
Q
RX_CLK8_IN_MUX1
1.4ns
Primary
FPGA Clock
Tree
RX2_VCOP
3ns
0.8ns
PLL_RX2
(Bypass Mode)
FPGA
Embedded Line Interface Core
5.0ns
0.0ns
10.0ns
15.0ns
20.0ns
RX2_VCOP
(Reference Clock)
0.6ns
RX_CLK8_IN_MUX1
5.6ns
Launch
3.0ns
FPGA Clock
10.6ns
15.6ns
20.6ns
Hold
8.0ns
13.0ns
Capture
Data
0.7 ns Tpd_min
1.9 ns Tpd_max
47
18.0ns
Clock
Divider
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 33 shows the Receive (Embedded Line Interface to FPGA) timing for 2.5G mode where PLL_RX2 is
bypassed via the PLL_BYPASS external FPSC pin. The 0.9 ns minimum propagation delay and 2.7 ns maximum
propagation delay shown are approximate values for the embedded line interface in this scenario. In the waveform
shown, data will be time shifted at the FPGA capture register due to FPGA data path delay. Consult the ispLEVER
software, via the static timing analysis tool TRACE, for the exact timing values. The FPGA data path delay needs to
increase together with clock skew to avoid hold issues. The FPGA design should be checked for hold violations
with TRACE.
Figure 33. Receive Timing for 2.5G Mode with PLL Bypassed (-1 Speed Grade)
RX_CLK_IN[0]
(644 MHz)
RX_DAT_IN
D
Q
RX_CLK8_IN_MUX1
FPGA Clock
Long Skew
3.5ns
D
Q
Secondary
Clock
1.4ns
RX_CLK_IN_BUF
0.5ns
FPGA Clock
Short Skew
FPGA
Embedded Line Interface Core
0.0ns
3.1ns
6.2ns
9.3ns
12.4ns
RX_CLK_IN_BUF
(Reference Clock)
1.4ns
RX_CLK8_IN_MUX1
4.5ns
10.7ns
13.8ns
Launch
0.5ns
FPGA Clock
Short Skew
7.6ns
3.6ns
6.7ns
9.8ns
12.9ns
Capture
Hold
Data
0.9 ns Tpd_min
Potential hold violation.
2.7 ns Tpd_max
7.1ns
4.0ns
FPGA Clock Long Skew
10.2ns
13.3ns
Capture
Hold
48
Clock
Divider
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration. The pin descriptions in Table 12 and throughout this data sheet show active-low signals with an
overscore. The package pinout tables that follow show this as a signal ending with _N. Therefore, LDC and LDC_N
are equivalent.
Table 12. Pin Descriptions
Symbol
I/O
Description
VDD33
—
3.3 V positive power supply. This power supply is used for 3.3 V configuration RAMs and internal
PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on
the board for proper operation.
VDD15
—
1.5 V positive power supply for internal logic.
VDDIO
—
Positive power supply used by I/O banks.
Ground.
Dedicated Pins
VSS
—
PTEMP
I
Temperature sensing diode pin. Dedicated input.
RESET
I
During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC
latches/Flip-Flops to be asynchronously set/reset.
O
In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration
data in.
I
In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or
D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or
system bus modes.
I
As an input, a low level on DONE delays FPGA start-up after configuration.*
O
As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
I
PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan
circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high. This pin always
has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states
all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on
RD_CFG will initiate readback of the configuration data, including PFU output states, starting with
frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data
out. If used in boundary-scan, TDO is test data out.
CFG_IRQ/MPI_IR
Q
O
During JTAG, slave, master, and asynchronous peripheral configuration, assertion on this CFG_IRQ
(active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt
request output, when the MPI is used.
LVDS_R
—
Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs.
CCLK
DONE
PRGM
*The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all
other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
49
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information (continued)
Table 12. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins
M[3:0]
I
During powerup and initialization, M0—M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O.*
PLL_CK[0:7][TC]
P[TBLR]CLK[1:0][T
C]
TDI, TCK, TMS
I
Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull-up.
I/O These pins are user-programmable I/O pins if not used by PLLs after configuration.
I
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
I/O After configuration, these pins are user-programmable I/O, if not used for clock inputs.
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O if boundary scan is not used.*
RDY/BUSY/RCLK
O
During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external memory.
This output is not normally used.
I/O After configuration, this pin is a user-programmable I/O pin.*
HDC
O
High during configuration is output high until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
I/O After configuration, this pin is a user-programmable I/O pin.*
LDC
O
Low during configuration is output low until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
I/O After configuration, this pin is a user-programmable I/O pin.*
INIT
CS0, CS1
INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT
I/O is held low during power stabilization and internal clearing of memory. As an active-low input, INIT
holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pullup is enabled.
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a
status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready,
and a low indicates busy.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all
other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
50
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information (continued)
Table 12. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to
the FPGA.
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
PPC_A[14:31]
I
During MPI mode, the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master
utilizing the least-significant bits of the PowerPC 32-bit address.
MPI_BURST
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates
that the current transfer is not a burst.
MPI_BDIP
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the
second beat in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[0:1]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for
the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
O
During master parallel mode, A[21:0] address the configuration EPROMs up to 4 Mbytes.
A[21:0]
MPI_ACK
I/O If not used for MPI, these pins are user-programmable I/O pins after configuration.*
O
In MPI mode, this is driven low indicating the MPI received the data on the write cycle or returned data
on a read cycle.
I/O If not used for MPI, these pins are user-programmable I/O pins after configuration.*
MPI_CLK
I
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a
source of the clock for the embedded system bus. If MPI is used, this will be the AMBA bus clock.
I/O If not used for MPI, these pins are user-programmable I/O pins after configuration.*
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal
system bus for the current transaction.
I/O If not used for MPI, these pins are user-programmable I/O pins after configuration.*
MPI_RTRY
O
I/O If not used for MPI, these pins are user-programmable I/O pins after configuration.*
I/O
D[0:31]
This pin requests the MPC860 relinquish the bus and retry the cycle.
Selectable data bus width from 8-, 16-, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction.
I
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration
modes when WR is low and each pin has a pull-up enabled. During serial configuration modes, D0 is
the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.*
DP[0:3]
Selectable parity bus width in MPI mode from 1-, 2-, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for
I/O D[16:23], and DP[3] for D[24:31].
After configuration, if MPI is not used, the pins are user-programmable I/O pin.*
* The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration
pins (and the activation of all user I/Os) is controlled by a second set of options.
51
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information (continued)
Table 12. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
DIN
I
During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a
pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
DOUT
TESTCFG
O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave
devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin.*
During configuration this pin should be held high, to allow configuration to occur. A pull-up is enabled
I
during configuration.
I/O After configuration, TESTCFG is a user-programmable I/O pin.*
* The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration
pins (and the activation of all user I/Os) is controlled by a second set of options.
52
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information (continued)
This table describes the I/O signal ports on the embedded core portion of the device.
Table 13. FPSC Function Pin Description
Symbol
I/O
Description
Control and Global Pins
PLL_BYPASS
I
PWRDN
I
3.3 V active-high. Enables the bypass mode for both receive and both transmit
PLLs.
3.3 V active-high. Power down all LVDS links and both receive and both transmit PLLs.
3.3 V active-high. Resets the receive PLLs and the demultiplexer block.
3.3 V active-high. Resets the transmit PLLs and the multiplexer block.
RESET_RX
I
RESET_TX
I
Receive I/O Pins
RX_DAT_IN_N<15:0>
I
RX_DAT_IN_P<15:0>
I
RX_CLK_IN_N<3:0>
I
RX_CLK_IN_P<3:0>
I
Transmit I/O Pins
TX_DAT_OUT_N<15:0>
O
TX_DAT_OUT_P<15:0>
O
TX_CLK_OUT_N<3:0>
O
TX_CLK_OUT_P<3:0>
O
TX_CLK_IN_N
I
TX_CLK_IN_P
I
LVDS Input Reference Pins
LV_REF10
—
LV_REF14
—
LV_RESHI
—
LV_RESLO
—
LVCTAP_[6:1]
—
LVDS data input for receive side.
LVDS data input for receive side.
LVDS clock inputs for receive side.
LVDS clock inputs for receive side.
LVDS data outputs on transmit side.
LVDS data outputs on transmit side.
LVDS clock outputs on transmit side.
LVDS clock outputs on transmit side.
LVDS transmit reference clock input.
LVDS transmit reference clock input.
LVDS reference voltage: 1.0 V ± 3%.
LVDS reference voltage: 1.4 V ± 3%.
LVDS resistor high pin (use 100 Ω to LV_RESLO pin).
LVDS resistor low pin (use 100 Ω to LV_RESHI pin).
LVDS input centertap (use 0.01 µF to GRD).
53
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Information (continued)
In Table 14, an output refers to a signal flowing into the FGPA logic (out of the embedded core) and an input refers
to a signal flowing out of the FPGA logic (into the embedded core).
Table 14. Embedded Core/FPGA Interface Signal Description
Symbol
Receive Signals
RX_DAT_OUT<127:0>
RX_CLK8_OUT<3:0>
RX_ENB8_OUT<3:0>
RX1_VCOP
RX2_VCOP
I/O
Description
O
O
O
O
O
Data from demultiplexer on receive side.
Divided down clocks on receive side.
Data enables on receive side.
RX1_PLL output clock on receive side (M/N clock) after phase select.
RX2_PLL output clock on receive side (x1 clock) before phase select.
PLL feedback input to RX2_PLL. This allows for the removal of the FPGA clock routing
delay. Connection set by ispLEVER Module Manager software. Not to be connected
manually by user.
Lock the signal for RX1_PLL and RX2_PLL. This signal is a logical OR of the lock signal from both PLLs. It is not integrated; thus, small glitches can occur on this signal during normal PLL operation. RX_LOCK “1” = LOCKED.
RX2_FBCKI
I
RX_LOCK
O
Transmit Signals
TX_DAT_IN<127:0>
TX_CLK8_IN<3:0>
TX_ENB8_IN<3:0>
TX1_VCOP
TX2_VCOP
I
I
I
O
O
TX2_FBCKI
I
TX_LOCK
O
VSS_A<7:4>
VDD33_A<7:4>
—
—
Data to multiplexer on transmit side.
Clocks to multiplexer on transmit side.
Data enables on transmit side.
TX1_PLL output clock on transmit side (M/N clock) after phase select.
TX2_PLL output clock on transmit side (x1 clock) after phase select.
PLL feedback input to TX2 PLL. This allows for the removal of the FPGA clock routing
delay. Connection set by ispLEVER Module Manager software. Not to be connected
manually by user.
Lock signal for TX1_PLL and TX2_PLL. This signal is a logical OR of the lock signal
from both PLLs. It is not integrated; thus, small glitches can occur on this signal during
normal operation. TX_LOCK “1” = LOCKED.
Analog ground for the embedded line interface PLLs.
Analog power supply for the embedded line interface PLLs.
Miscellaneous Signals
FPGA_RESET
I
A logic ‘1’ resets all receive and transmit logic, excluding PLLs.
54
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Package Pinouts
Table 15 provides the number of user-programmable I/Os available for each available package. Table 16 provides
the package pin and pin function for the ORLI10G FPSC and packages. The bond pad name is identified in the PIO
nomenclature used in the ispLEVER design editor. The bank column provides information as to which output voltage level bank the given pin is in. The group column provides information as to the group of pins the given pin is in.
This is used to show which VREF pin is used to provide the reference voltage for single-ended limited-swing I/Os. If
none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the VREF pin is available as
an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
Table 15. ORCA Programmable I/Os Summary
Device
User programmable I/O
Available programmable differential pair
pins
FPGA configuration pins
FPGA dedicated function pins
Core function pins
VDD15
VDD33_A
VDD33
VDDIO
VSS
VSS_A
LVCTAP for dedicated differential channels
Core LV_REF pins
Total package pins
680 PBGAM
316
272
7
2
86
86
4
28
44
95
4
6
4
680
The built-in MicroProcessor Interface (MPI) cannot be fully utilized in the 680-pin PBGA package because the
implementation of the XGMII interface limits the number of available address and data pins.
As shown in the Pair columns in Table 16, differential pairs and physical locations are numbered within each bank
(e.g., L19C_A0 is the nineteenth pair in an associated bank). A C indicates complementary differential, whereas a
T indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:
• _A1 indicates one ball between pairs.
• _A2 indicates two balls between pairs.
• _D0 indicates balls are diagonally adjacent.
• _D1 indicates balls are diagonally adjacent separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 16, are associated to the bank and group
(e.g., VREF_TL_01 is the VREF for group one of the Top Left (TL) bank).
55
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Pin Configuration
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
A1
—
—
VSS
VSS
—
—
E5
—
—
VDD33
VDD33
—
—
E4
—
—
O
PRD_DATA
RD_DATA/TDO
—
—
—
—
VDD15
VDD15
—
—
C1
—
—
I
PRESET_N
RESET_N
—
D1
—
—
I
PRD_CFG_N
RD_CFG_N
—
E2
—
—
I
PPRGRM_N
PRGRM_N
—
A2
0 (TL)
—
VDDIO0
VDDIO0
—
—
F4
0 (TL)
7
IO
PL2D
PLL_CK0C/HPPLL
L21C_A0
F3
0 (TL)
7
IO
PL2C
PLL_CK0T/HPPLL
L21T_A0
A3
0 (TL)
—
VDDIO0
VDDIO0
—
—
G5
0 (TL)
7
IO
PL3D
—
L22C_A0
F5
0 (TL)
7
IO
PL3C
VREF_0_07
L22T_A0
A18
—
—
VSS
VSS
—
—
G4
0 (TL)
7
IO
PL4D
D5
L23C_D1
F2
0 (TL)
7
IO
PL4C
D6
L23T_D1
B1
0 (TL)
—
VDDIO0
VDDIO0
—
—
H5
0 (TL)
8
IO
PL4B
—
L24C_D1
G3
0 (TL)
8
IO
PL4A
VREF_0_08
L24T_D1
F1
0 (TL)
8
IO
PL5D
HDC
L25C_A0
G2
0 (TL)
8
IO
PL5C
LDC_N
L25T_A0
A33
—
—
VSS
VSS
—
—
H4
0 (TL)
8
IO
PL5B
—
L26C_A0
J5
0 (TL)
8
IO
PL5A
—
L26T_A0
H3
0 (TL)
9
IO
PL6D
TESTCFG
L27C_D1
G1
0 (TL)
9
IO
PL6C
D7
L27T_D1
B3
0 (TL)
—
VDDIO0
VDDIO0
—
—
J4
0 (TL)
9
IO
PL7D
VREF_0_09
L28C_D1
H2
0 (TL)
9
IO
PL7C
A17/PPC_A31
L28T_D1
A34
—
—
VSS
VSS
—
—
K5
0 (TL)
9
IO
PL8D
CS0_N
L29C_D1
J3
0 (TL)
9
IO
PL8C
CS1
L29T_D1
C2
0 (TL)
—
VDDIO0
VDDIO0
—
—
H1
0 (TL)
10
IO
PL9D
—
L30C_A0
J2
0 (TL)
10
IO
PL9C
—
L30T_A0
B2
—
—
VSS
VSS
—
—
K4
0 (TL)
10
IO
PL9A
—
—
L5
0 (TL)
10
IO
PL10D
INIT_N
L31C_D1
K3
0 (TL)
10
IO
PL10C
DOUT
L31T_D1
—
—
—
VDD15
VDD15
—
—
J1
0 (TL)
10
IO
PL11D
VREF_0_10
L32C_A0
K2
0 (TL)
10
IO
PL11C
A16/PPC_A30
L32T_A0
56
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
B33
—
—
VSS
VSS
—
—
K1
M5
L4
L1
M4
N5
L3
0 (TL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
10
1
1
—
1
1
1
IO
IO
IO
VDDIO7
IO
IO
IO
PL11A
PL12D
PL12C
VDDIO7
PL12B
PL12A
PL13D
—
A15/PPC_A29
A14/PPC_A28
—
—
—
VREF_7_01
—
L1C_A0
L1T_A0
—
L2C_A0
L2T_A0
L3C_A0
L2
B34
N4
P5
M2
M1
M3
N3
N2
C3
P4
P3
R3
R5
N1
P2
C13
R4
P1
R2
—
T2
R1
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
1
—
2
2
2
2
—
2
2
—
3
3
—
3
3
3
—
3
3
3
—
3
3
IO
VSS
IO
IO
IO
IO
VDDIO7
IO
IO
VSS
IO
IO
VDDIO7
IO
IO
IO
VSS
IO
IO
IO
VDD15
IO
IO
PL13C
VSS
PL13B
PL13A
PL14D
PL14C
VDDIO7
PL15D
PL15C
VSS
PL16D
PL16C
VDDIO7
PL16A
PL17D
PL17C
VSS
PL17A
PL18D
PL18C
VDD15
PL18B
PL18A
D4
—
—
—
L3T_A0
—
L4C_A0
L4T_A0
L5C_A0
L5T_A0
—
L6C_A0
L6T_A0
—
L7C_A0
L7T_A0
—
—
L8C_A0
L8T_A0
—
—
L9C_A0
L9T_A0
—
L10C_A0
L10T_A0
T5
T4
C22
U5
T3
T1
U3
U1
U4
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
4
4
—
4
4
4
4
—
4
IO
IO
VSS
IO
IO
IO
IO
VDDIO7
IO
PL19D
PL19C
VSS
PL19B
PL19A
PL20D
PL20C
VDDIO7
PL20B
57
RDY/BUSY_N/RCLK
VREF_7_02
—
A13/PPC_A27
A12/PPC_A26
—
—
—
—
—
A11/PPC_A25
VREF_7_03
—
—
—
—
—
—
—
RD_N/MPI_STRB_N
VREF_7_04
—
—
—
PLCK0C
PLCK0T
—
—
L11C_A0
L11T_A0
—
L12C_D1
L12T_D1
L13C_D1
L13T_D1
—
L14C_A1
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
U2
7 (CL)
—
C32
V1
V2
D4
V3
V4
—
—
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
V5
W4
—
W3
W2
D30
Y1
W5
Y4
W1
Y2
Y5
AA3
D31
AA2
AA1
AB1
Y3
AA4
AB2
AB3
AA5
AB4
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
AC2
AC1
AC3
AB5
AC4
D33
AD2
AC5
AD3
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
7 (CL)
7 (CL)
7 (CL)
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
4
IO
—
—
5
5
—
5
5
VDD15
VSS
IO
IO
VSS
IO
IO
PL20A
—
L14T_A1
VDD15
VSS
PL21D
PL21C
VSS
PL21B
PL21A
—
—
A10/PPC_A24
A9/PPC_A23
—
—
—
—
—
L15C_A0
L15T_A0
—
L16C_A0
L16T_A0
5
5
—
5
5
—
5
6
6
—
6
6
6
—
6
6
6
—
7
7
7
7
7
IO
IO
VDD15
IO
IO
VSS
IO
IO
IO
VDDIO7
IO
IO
IO
VSS
IO
IO
IO
VDDIO7
IO
IO
IO
IO
IO
PL22D
PL22C
VDD15
PL23D
PL23C
VSS
PL23A
PL24D
PL24C
VDDIO7
PL24A
PL25D
PL25C
VSS
PL25A
PL26D
PL26C
VDDIO7
PL26B
PL27D
PL27C
PL27B
PL27A
A8/PPC_A22
VREF_7_05
—
—
—
—
—
PLCK1C
PLCK1T
—
—
VREF_7_06
A7/PPC_A21
—
—
A6/PPC_A20
A5/PPC_A19
—
—
WR_N/MPI_RW
VREF_7_07
—
—
L17C_A0
L17T_A0
—
L18C_A0
L18T_A0
—
—
L19C_A0
L19T_A0
—
—
L20C_D1
L20T_D1
—
—
L21C_A0
L21T_A0
—
—
L22C_A0
L22T_A0
L23C_D0
L23T_D0
8
8
—
8
8
—
8
8
8
IO
IO
VDDIO7
IO
IO
VSS
IO
IO
IO
PL28D
PL28C
VDDIO7
PL29D
PL29C
VSS
PL29A
PL30D
PL30C
A4/PPC_A18
VREF_7_08
—
A3/PPC_A17
A2/PPC_A16
—
—
A1/PPC_A15
A0/PPC_A14
L24C_A0
L24T_A0
—
L25C_D0
L25T_D0
—
—
L26C_D1
L26T_D1
58
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
AE1
7 (CL)
8
IO
PL31D
DP0
L27C_A0
AE2
E34
AF1
AD5
AD4
AK4
AE3
7 (CL)
—
7 (CL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
8
—
8
1
1
—
1
IO
VSS
IO
IO
IO
VDDIO6
IO
PL31C
VSS
PL31A
PL32D
PL32C
VDDIO6
PL32A
DP1
—
—
D8
VREF_6_01
—
—
L27T_A0
—
—
L1C_A0
L1T_A0
—
—
AE5
AE4
F33
AF2
AG1
AK5
AF3
AF5
H34
AG2
AF4
AH1
AG3
AL1
AH2
AJ1
AG4
J33
AH3
AG5
AJ2
AL3
AK1
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
1
1
—
2
2
—
2
2
—
3
3
3
3
—
3
3
4
—
4
4
4
—
4
IO
IO
VSS
IO
IO
VDDIO6
IO
IO
VSS
IO
IO
IO
IO
VDDIO6
IO
IO
IO
VSS
IO
IO
IO
VDDIO6
IO
PL33D
PL33C
VSS
PL34D
PL34C
VDDIO6
PL34B
PL34A
VSS
PL35B
PL35A
PL36D
PL36C
VDDIO6
PL36B
PL36A
PL37D
VSS
PL37B
PL37A
PL38C
VDDIO6
PL38B
D9
D10
—
—
VREF_6_02
—
—
—
—
D11
D12
—
—
—
VREF_6_03
D13
—
—
—
VREF_6_04
—
—
—
L2C_A0
L2T_A0
—
L3C_A0
L3T_A0
—
L4C_A1
L4T_A1
—
L5C_D1
L5T_D1
L6C_D1
L6T_D1
—
L7C_A0
L7T_A0
—
—
L8C_D1
L8T_D1
—
—
—
AH4
AJ3
AK2
L34
AH5
AJ4
N13
AK3
AM1
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
—
—
6 (BL)
4
4
4
—
4
4
—
—
—
IO
IO
IO
VSS
IO
IO
VSS
I
VDDIO6
PL38A
PL39D
PL39C
VSS
PL39B
PL39A
VSS
PTEMP
VDDIO6
—
—
L9C_A0
L9T_A0
—
L10C_A0
L10T_A0
—
—
—
59
PLL_CK7C/HPPLL
PLL_CK7T/HPPLL
—
—
—
—
PTEMP
—
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
—
—
—
VDD15
VDD15
—
—
AN1
AJ5
N14
AL5
—
AM5
AN4
—
—
—
—
—
6 (BL)
6 (BL)
—
—
—
—
—
5
5
IO
VDD33
VSS
VDD33
VDD15
IO
IO
LVDS_R
VDD33
VSS
VDD33
VDD15
PB2A
PB2B
LVDS_R
—
—
—
—
DP2
—
—
—
—
—
—
L11T_A0
L11C_A0
AM2
AK6
AL6
AK7
N15
AN5
AM6
AN6
AP5
AM4
AL7
AM7
N20
AN7
AP6
AK8
AL8
AN3
AM8
AK9
AP7
N21
AL9
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
—
5
5
5
—
5
5
5
5
—
6
6
—
6
6
6
6
—
7
7
7
—
7
VDDIO6
IO
IO
IO
VSS
IO
IO
IO
IO
VDDIO6
IO
IO
VSS
IO
IO
IO
IO
VDDIO6
IO
IO
IO
VSS
IO
VDDIO6
PB2C
PB2D
PB3A
VSS
PB3C
PB3D
PB4A
PB4B
VDDIO6
PB4C
PB4D
VSS
PB5C
PB5D
PB6A
PB6B
VDDIO6
PB6C
PB6D
PB7A
VSS
PB7C
—
PLL_CK6T/PPLL
PLL_CK6C/PPLL
—
—
—
—
VREF_6_05
DP3
—
—
—
—
VREF_6_06
D14
—
—
—
D15
D16
—
—
D17
—
L12T_A0
L12C_A0
—
—
L13T_A0
L13C_A0
L14T_A0
L14C_A0
—
L15T_A0
L15C_A0
—
L16T_A0
L16C_A0
L17T_A0
L17C_A0
—
L18T_D1
L18C_D1
—
—
L19T_A0
AK10
AN8
AP2
AM9
AL10
AP8
N22
AL11
AK11
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
7
7
—
7
7
8
—
8
8
IO
IO
VDDIO6
IO
IO
IO
VSS
IO
IO
PB7D
PB8A
VDDIO6
PB8C
PB8D
PB9A
VSS
PB9C
PB9D
D18
—
—
VREF_6_07
D19
—
—
D20
D21
L19C_A0
—
—
L20T_A0
L20C_A0
—
—
L21T_A0
L21C_A0
60
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
AM10
6 (BL)
—
AN9
AP9
AM11
AK12
P13
AN10
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
AP10
AL12
AK13
AP3
AN11
AN12
AK14
AL13
P14
AP12
AN13
AL14
AK15
—
AP13
AP14
AN14
P15
AM14
AL15
AN15
AM16
AL16
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
AP15
P20
AN16
AP16
AK16
—
AL17
AK17
—
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
—
VREF
Group
I/O
Pin Description
8
IO
PB10A
—
—
—
8
8
9
9
—
9
VDD15
IO
IO
IO
IO
VSS
IO
VDD15
PB10C
PB10D
PB11A
PB11B
VSS
PB11C
—
VREF_6_08
D22
—
—
—
D23
—
L22T_A0
L22C_A0
L23T_D1
L23C_D1
—
L24T_A0
9
9
9
—
9
9
9
9
—
10
10
10
10
—
10
10
11
—
11
11
11
11
11
IO
IO
IO
VDDIO6
IO
IO
IO
IO
VSS
IO
IO
IO
IO
VDDIO6
IO
IO
IO
VSS
IO
IO
IO
IO
IO
PB11D
PB12A
PB12B
VDDIO6
PB12C
PB12D
PB13A
PB13B
VSS
PB13C
PB13D
PB14A
PB14B
VDDIO6
PB14C
PB14D
PB15A
VSS
PB15C
PB15D
PB16A
PB16C
PB16D
D24
—
—
—
VREF_6_09
D25
—
—
—
D26
D27
—
—
—
VREF_6_10
D28
—
—
D29
D30
—
VREF_6_11
D31
L24C_A0
L25T_A0
L25C_A0
—
L26T_A0
L26C_A0
L27T_A0
L27C_A0
—
L28T_A0
L28C_A0
L29T_A0
L29C_A0
—
L30T_A0
L30C_A0
—
—
L31T_A0
L31C_A0
—
L32T_A0
L32C_A0
1
—
1
1
1
—
1
1
—
IO
VSS
IO
IO
IO
VDD15
IO
IO
VDD15
PB17A
VSS
PB17C
PB17D
PB18A
VDD15
PB18C
PB18D
VDD15
—
—
—
—
—
—
VREF_5_01
—
—
—
—
L1T_A0
L1C_A0
—
—
L2T_A0
L2C_A0
—
61
Additional Function
BM680 Pair
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
P21
—
—
VSS
VSS
—
—
AM17
AN17
P22
AP18
AM18
AN18
AL18
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
2
2
—
2
2
2
2
IO
IO
VSS
IO
IO
IO
IO
PB19A
PB19B
VSS
PB19C
PB19D
PB20A
PB20B
—
—
—
PBCK0T
PBCK0C
—
—
L3T_A0
L3C_A0
—
L4T_A1
L4C_A1
L5T_A1
L5C_A1
AM12
AN19
AK18
AM19
AP20
—
AL19
AN20
AP21
P34
AL20
AK19
AN21
AM15
AK20
AM21
AP22
R13
AL21
AN22
AP23
AM20
AN23
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
2
2
2
2
—
3
3
3
—
3
3
3
—
3
3
3
—
4
4
4
—
4
VDDIO5
IO
IO
IO
IO
VDD15
IO
IO
IO
VSS
IO
IO
IO
VDDIO5
IO
IO
IO
VSS
IO
IO
IO
VDDIO5
IO
VDDIO5
PB20C
PB20D
PB21A
PB21B
VDD15
PB21C
PB21D
PB22A
VSS
PB22C
PB22D
PB23A
VDDIO5
PB23C
PB23D
PB24A
VSS
PB24C
PB24D
PB25A
VDDIO5
PB25C
—
VREF_5_02
—
—
—
—
—
VREF_5_03
—
—
—
—
—
—
PBCK1T
PBCK1C
—
—
—
—
—
—
—
—
L6T_D2
L6C_2
L7T_D1
L7C_D1
—
L8T_D1
L8C_D1
—
—
L9T_A0
L9C_A0
—
—
L10T_D1
L10C_D1
—
—
L11T_D1
L11C_D1
—
—
L12T_A0
AN24
AK21
AL22
R14
AP25
AM24
AK22
AL23
AM23
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
4
4
4
—
5
5
5
5
—
IO
IO
IO
VSS
IO
IO
IO
IO
VDDIO5
PB25D
PB26A
PB26B
VSS
PB26C
PB26D
PB27A
PB27B
VDDIO5
VREF_5_04
—
—
—
—
VREF_5_05
—
—
—
L12C_A0
L13T_A0
L13C_A0
—
L14T_D1
L14C_D1
L15T_A0
L15C_A0
—
62
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
AN25
5 (BC)
5
IO
PB27C
—
L16T_D1
AL24
AP26
R15
AM25
AK23
AN26
AL25
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5
6
—
6
6
6
6
IO
IO
VSS
IO
IO
IO
IO
PB27D
PB28A
VSS
PB28C
PB28D
PB29A
PB29C
—
—
—
—
VREF_5_06
—
—
L16T_D1
—
—
L17T_D1
L17C_D1
—
L18T_A0
AK24
AP27
R20
AM26
AN27
AP11
AP28
AM27
R21
AL26
AK25
AP17
AN28
AP29
R22
AP19
T16
T17
A31
AL27
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
5 (BC)
—
—
—
—
6
7
—
7
7
—
7
7
—
7
7
—
8
8
—
—
—
—
—
—
IO
IO
VSS
IO
IO
VDDIO5
IO
IO
VSS
IO
IO
VDDIO5
IO
IO
VSS
VDDIO5
VSS
VSS
VDD15
I
PB29D
PB30A
VSS
PB30C
PB30D
VDDIO5
PB31C
PB31D
VSS
PB32C
PB32D
VDDIO5
PB33C
PB33D
VSS
VDDIO5
VSS
VSS
VDD15
—
—
—
—
—
—
VREF_5_07
—
—
—
—
—
—
VREF_5_08
—
—
—
—
—
—
L18C_A0
—
—
L19T_A0
L19C_A0
—
L20T_D1
L20C_D1
—
L21T_A0
L21C_A0
—
L22T_A0
L22C_A0
—
—
—
—
—
L1_A0
AM28
—
—
I
RX_DAT_IN_10_N/RX_DAT_IN_0_
N
—
L1_A0
C30
AN29
—
—
—
—
VDD15
I
VDD15
—
—
—
L2_A0
AP30
—
—
I
RX_DAT_IN_11_N/RX_DAT_IN_1_
N
—
L2_A0
—
AL28
—
—
—
—
VDD33
I
VDD33
—
—
—
L3_A0
AM29
—
—
I
RX_DAT_IN_12_N/RX_DAT_IN_2_
N
—
L3_A0
Y34
—
—
VSS
VSS
—
—
RX_DAT_IN_10_P/RX_DAT_IN_0_
P
RX_DAT_IN_11_P/RX_DAT_IN_1_
P
RX_DAT_IN_12_P/RX_DAT_IN_2_
P
63
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
AN30
—
—
VDD33
VDD33
—
—
AK27
—
—
I
RX_DAT_IN_13_P/RX_DAT_IN_3_
P
—
L4_A0
AK28
—
—
I
RX_DAT_IN_13_N/RX_DAT_IN_3_
N
—
L4_A0
AL29
AM30
AN31
AP32
AK30
AA13
AA14
C33
AK31
AJ30
AK32
AJ31
AA15
AH30
C34
AK33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
VSSA_4
RX_CLK_IN_0_P
RX_CLK_IN_0_N
LVCTAP_1
VSSA_4
VDD33A_4
VSS
VSS
VDD15
VDD33A_5
VDD33
VSSA_5
LVCTAP_2
VSS
VDD33
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L5_A0
L5_A0
—
—
—
—
—
—
—
—
—
—
—
—
—
L6_A0
AJ32
—
—
I
RX_DAT_IN_20_N/RX_DAT_IN_4_
N
—
L6_A0
AH31
—
—
I
RX_DAT_IN_21_P/RX_DAT_IN_5_
P
—
L7_A0
AG30
—
—
I
RX_DAT_IN_21_N/RX_DAT_IN_5_
N
—
L7_A0
AA20
AF30
—
—
—
—
VSS
I
VSS
—
—
—
L8_A0
AG31
—
—
I
RX_DAT_IN_22_N/RX_DAT_IN_6_
N
—
L8_A0
AK34
—
—
I
RX_DAT_IN_23_P/RX_DAT_IN_7_
P
—
L9_A0
AJ33
—
—
I
RX_DAT_IN_23_N/RX_DAT_IN_7_
N
—
L9_A0
D28
AA21
AH32
AE30
AA22
D32
AG32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VSS
VDD33
I
VSS
VDD15
I
VDD15
VSS
VDD33
LVCTAP_3
VSS
VDD15
RX_CLK_IN_1_P
—
—
—
—
—
—
—
—
—
—
—
—
—
L10_A0
VDD33A_4
VSS
VSS
VDD15
VDD33A_5
VDD33
VSSA_5
I
VSS
VDD33
VDD15
I
Pin Description
RX_DAT_IN_20_P/RX_DAT_IN_4_
P
RX_DAT_IN_22_P/RX_DAT_IN_6_
P
64
Additional Function
BM680 Pair
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
AF31
—
AF32
AB13
AC30
—
—
—
AD30
I/O
Pin Description
Additional Function
BM680 Pair
—
I
—
—
—
VDD33
VSS
I
RX_CLK_IN_1_N
—
L10_A0
VDD33
VSS
—
—
—
—
—
L11_A0
—
—
I
RX_DAT_IN_30_N/RX_DAT_IN_8_
N
—
L11_A0
D34
AE31
—
—
—
—
VDD15
I
VDD15
—
—
—
L12_A0
AE32
—
—
I
RX_DAT_IN_31_N/RX_DAT_IN_9_
N
—
L12_A0
AB14
AF33
AD31
—
—
—
—
—
—
VSS
VDD33
I
VSS
VDD33
—
—
—
—
—
L13_A0
AD32
—
—
I
RX_DAT_IN_32_N/RX_DAT_IN_10
_N
—
L13_A0
F34
AB30
AC31
—
—
—
—
—
—
VDD15
I
I
VDD15
LVCTAP_4
—
—
—
—
—
L14_A0
AC32
—
—
I
RX_DAT_IN_33_N/RX_DAT_IN_11
_N
—
L14_A0
AC33
AB15
AB31
AB32
AA30
G33
AB33
AB20
AA31
Y30
AA32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD33
VSS
I
I
I
VDD15
VDD33
VSS
I
I
I
VDD33
VSS
RX_CLK_IN_2_P
RX_CLK_IN_2_N
LVCTAP_5
VDD15
VDD33
VSS
RX_CLK_IN_3_P
RX_CLK_IN_3_N
—
—
—
—
—
—
—
—
—
—
—
—
—
L15_A0
L15_A0
—
—
—
—
L16_A0
L16_A0
L17_A0
AA33
—
—
I
RX_DAT_IN_40_N/RX_DAT_IN_12
_N
—
L17_A0
AB21
G34
Y31
—
—
—
—
—
—
VSS
VDD15
I
VSS
VDD15
—
—
—
—
—
L18_A0
Y32
—
—
I
—
L18_A0
RX_DAT_IN_30_P/RX_DAT_IN_8_
P
RX_DAT_IN_31_P/RX_DAT_IN_9_
P
RX_DAT_IN_32_P/RX_DAT_IN_10
_P
RX_DAT_IN_33_P/RX_DAT_IN_11
_P
RX_DAT_IN_40_P/RX_DAT_IN_12
_P
RX_DAT_IN_41_P/RX_DAT_IN_13
_P
RX_DAT_IN_41_N/RX_DAT_IN_13
_N
65
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
W30
—
—
VDD33
VDD33
—
—
AB22
Y33
J34
W31
—
—
—
—
—
—
—
—
VSS
VDD33
VDD15
I
VSS
VDD33
VDD15
—
—
—
—
—
—
—
L19_A0
W32
—
—
I
RX_DAT_IN_42_N/RX_DAT_IN_14
_N
—
L19_A0
AC34
K33
V30
—
—
—
—
—
—
VSS
VDD15
I
VSS
VDD15
—
—
—
—
—
L20_A0
V31
—
—
I
RX_DAT_IN_43_N/RX_DAT_IN_15
_N
—
L20_A0
W33
AE33
V32
V33
U33
U31
AF34
U30
K34
U32
T33
AH33
T32
T31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD33
VSS
I
I
I
I
VSS
VDD33
VDD15
O
O
VSS
VDD33
O
VDD33
VSS
LV_REF10
LV_REF14
LV_RESHI
LV_RESLO
VSS
VDD33
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L21_A0
L21_A0
—
—
L22_A0
T30
—
—
O
TX_DAT_OUT_10_N/TX_DAT_OUT_0_
N
—
L22_A0
AJ34
R33
—
—
—
—
VSS
O
VSS
—
—
—
L23_A0
R32
—
—
O
TX_DAT_OUT_11_N/TX_DAT_OUT_1_
N
—
L23_A0
M34
R31
—
—
—
—
VDD15
O
VDD15
—
—
—
L24_A0
R30
—
—
O
TX_DAT_OUT_12_N/TX_DAT_OUT_2_
N
—
L24_A0
AL2
—
P33
—
—
—
—
—
—
VSS
VDD33
VDD33
VSS
VDD33
VDD33
—
—
—
—
—
—
RX_DAT_IN_42_P/RX_DAT_IN_14
_P
RX_DAT_IN_43_P/RX_DAT_IN_15
_P
TX_CLK_OUT_0_P
TX_CLK_OUT_0_N
VSS
VDD33
TX_DAT_OUT_10_P/TX_DAT_OUT_0_
P
TX_DAT_OUT_11_P/TX_DAT_OUT_1_
P
TX_DAT_OUT_12_P/TX_DAT_OUT_2_
P
66
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
N33
—
—
O
TX_DAT_OUT_13_P/TX_DAT_OUT_3_
P
—
L25_A0
P32
—
—
O
TX_DAT_OUT_13_N/TX_DAT_OUT_3_
N
—
L25_A0
P30
P31
AL4
N32
—
—
—
—
—
—
—
—
O
O
VSS
O
TX_CLK_OUT_1_P
—
—
—
—
L26_A0
L26_A0
—
L27_A0
N31
—
—
O
TX_DAT_OUT_20_N/TX_DAT_OUT_4_
N
—
L27_A0
N16
N30
M33
—
—
—
—
—
—
VDD15
VDD33
O
VDD15
VDD33
—
—
—
—
—
L28_A0
M32
—
—
O
TX_DAT_OUT_21_N/TX_DAT_OUT_5_
N
—
L28_A0
AL30
M31
—
—
—
—
VSS
O
VSS
—
—
—
L29_A0
M30
—
—
O
TX_DAT_OUT_22_N/TX_DAT_OUT_6_
N
—
L29_A0
L33
N17
L32
—
—
—
—
—
—
VDD33
VDD15
O
VDD33
VDD15
—
—
—
—
—
L30_A0
K32
—
—
O
TX_DAT_OUT_23_N/TX_DAT_OUT_7_
N
—
L30_A0
AL31
L30
L31
N18
J31
—
—
—
—
—
—
—
—
—
—
VSS
O
O
VDD15
O
VSS
—
—
—
—
—
—
L31_A0
L31_A0
—
L32_A0
K31
—
—
O
TX_DAT_OUT_30_N/TX_DAT_OUT_8_
N
—
L32_A0
TX_CLK_OUT_1_N
VSS
TX_DAT_OUT_20_P/TX_DAT_OUT_4_
P
TX_DAT_OUT_21_P/TX_DAT_OUT_5_
P
TX_DAT_OUT_22_P/TX_DAT_OUT_6_
P
TX_DAT_OUT_23_P/TX_DAT_OUT_7_
P
TX_CLK_OUT_2_P
TX_CLK_OUT_2_N
VDD15
TX_DAT_OUT_30_P/TX_DAT_OUT_8_
P
K30
—
—
VDD33
VDD33
—
—
AM3
H33
—
—
—
—
VSS
O
VSS
—
—
—
L33_A0
J32
—
—
O
TX_DAT_OUT_31_N/TX_DAT_OUT_9_
N
—
L33_A0
H32
H31
J30
N19
G32
—
—
—
—
—
—
—
—
—
—
VDD33
I
I
VDD15
I
VDD33
TX_CLK_IN_P
TX_CLK_IN_N
VDD15
LVCTAP_6
—
—
—
—
—
—
L34_A0
L34_A0
—
—
TX_DAT_OUT_31_P/TX_DAT_OUT_9_
P
67
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
AM13
—
—
G31
—
—
F32
—
N34
H30
E33
Pin Description
Additional Function
VSS
VSS
—
—
O
TX_DAT_OUT_32_P/TX_DAT_OUT_10
_P
—
L35_A0
—
O
TX_DAT_OUT_32_N/TX_DAT_OUT_10
_N
—
L35_A0
—
—
—
—
—
—
VDD15
VDD33
O
VDD15
VDD33
—
—
—
—
—
L36_A0
E32
—
—
O
TX_DAT_OUT_33_N/TX_DAT_OUT_11
_N
—
L36_A0
AM22
F31
E31
G30
P16
F30
E30
B32
C31
AM32
AN2
E29
E28
A32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
O
O
VDD33
VDD15
VDD33
VSSA_6
VDD33
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L37_A0
L37_A0
—
—
—
—
—
—
—
—
—
—
L38_A0
B31
—
—
O
TX_DAT_OUT_40_P/TX_DAT_OUT_12
_P
—
L38_A0
E27
—
—
O
TX_DAT_OUT_41_N/TX_DAT_OUT_13
_N
—
L39_A0
E26
—
—
O
TX_DAT_OUT_41_P/TX_DAT_OUT_13
_P
—
L39_A0
B30
P17
D29
—
—
—
—
—
—
VDD33
VDD15
O
VDD33
VDD15
—
—
—
—
—
L40_A0
C29
—
—
O
TX_DAT_OUT_42_P/TX_DAT_OUT_14
_P
—
L40_A0
AN33
C28
—
—
—
—
VSS
O
VSS
—
—
—
L41_A0
D27
—
—
O
TX_DAT_OUT_43_P/TX_DAT_OUT_15
_P
—
L41_A0
A30
E25
B29
—
—
—
—
—
—
I
I
I
PWRDN
RESET_RX
RESET_TX
—
—
—
—
—
—
VDD33A_6
VSS
VSS
VDD33A_7
VSSA_7
O
TX_DAT_OUT_33_P/TX_DAT_OUT_11
_P
TX_CLK_OUT_3_P
TX_CLK_OUT_3_N
VDD33
VDD15
VDD33
VSSA_6
VDD33
VDD33A_6
VSS
VSS
VDD33A_7
VSSA_7
TX_DAT_OUT_40_N/TX_DAT_OUT_12
_N
TX_DAT_OUT_42_N/TX_DAT_OUT_14
_N
TX_DAT_OUT_43_N/TX_DAT_OUT_15
_N
68
BM680 Pair
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
A29
—
T18
T19
A11
U16
A17
C27
D26
—
—
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
U17
B28
A28
A19
B27
U18
C26
B26
A27
—
E24
D25
D24
C25
U19
B25
A26
E23
D23
A24
C24
A25
E22
E21
U34
B24
D22
B23
A23
C12
D21
B22
I/O
Pin Description
Additional Function
BM680 Pair
—
I
PLL_BYPASS
—
—
—
—
—
—
—
9
9
VSS
VSS
VDDIO1
VSS
VDDIO1
IO
IO
VSS
VSS
VDDIO1
VSS
VDDIO1
PT32D
PT32C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
10
10
—
10
—
10
10
10
—
10
10
1
1
—
1
1
1
1
—
1
1
2
VSS
IO
IO
VDDIO1
IO
VSS
IO
IO
IO
VDD15
IO
IO
IO
IO
VSS
IO
IO
IO
IO
VDDIO1
IO
IO
IO
VSS
PT31D
PT31C
VDDIO1
PT30D
VSS
PT30A
PT29D
PT29C
VDD15
PT29B
PT29A
PT28D
PT28C
VSS
PT28B
PT28A
PT27D
PT27C
VDDIO1
PT27B
PT27A
PT26D
—
—
VREF_1_10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VREF_1_01
—
—
—
—
—
—
L1C_A0
L1T_A0
—
—
—
—
L2C_A0
L2T_A0
—
L3C_A0
L3T_A0
L4C_A0
L4T_A0
—
L5C_A0
L5T_A0
L6C_A0
L6T_A0
—
L7C_D1
L7T_D1
L8C_A0
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
2
—
2
2
2
2
—
3
3
IO
VSS
IO
IO
IO
IO
VDDIO1
IO
IO
PT26C
VSS
PT26B
PT26A
PT25D
PT25C
VDDIO1
PT24D
PT24C
VREF_1_02
—
—
—
—
—
—
—
VREF_1_03
L8T_A0
—
L9C_D1
L9T_D1
L10C_A0
L10T_A0
—
L11C_D1
L11T_D1
69
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
V16
—
—
A22
D20
E20
C15
C21
B21
A21
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
3
3
3
—
3
3
3
V17
B20
C19
A20
—
D19
E19
V18
B19
B18
C20
D18
E18
V19
—
B17
C17
W16
D17
C18
A16
B16
E17
—
1 (TC)
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
—
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
C16
D16
W17
A15
B15
D15
C23
A14
E16
1 (TC)
1 (TC)
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
Pin Description
Additional Function
BM680 Pair
VSS
VSS
—
—
IO
IO
IO
VDDIO1
IO
IO
IO
PT24A
PT23D
PT23C
VDDIO1
PT23A
PT22D
PT22C
—
—
—
—
—
—
—
—
L12C_A0
L12T_A0
—
—
L13C_A0
L13T_A0
—
3
4
4
—
4
4
—
4
4
—
4
4
—
—
5
5
—
5
5
5
5
5
VSS
IO
IO
IO
VDD15
IO
IO
VSS
IO
IO
VDDIO1
IO
IO
VSS
VDD15
IO
IO
VSS
IO
IO
IO
IO
IO
VSS
PT22A
PT21D
PT21C
VDD15
PT20D
PT20C
VSS
PT19D
PT19C
VDDIO1
PT19B
PT19A
VSS
VDD15
PT18D
PT18C
VSS
PT18B
PT18A
PT17D
PT17C
PT17A
—
—
—
—
—
—
—
—
—
VREF_1_04
—
—
—
—
—
PTCK1C
PTCK1T
—
—
—
PTCK0C
PTCK0T
—
—
—
L14C_D1
L14T_D1
—
L15C_A0
L15T_A0
—
L16C_A0
L16T_A0
—
L17C_A0
L17T_A0
—
—
L18C_A0
L18T_A0
—
L19C_A0
L19T_A0
L20C_A0
L20T_A0
—
5
5
—
5
6
6
—
6
6
IO
IO
VSS
IO
IO
IO
VDDIO1
IO
IO
PT16D
PT16C
VSS
PT16A
PT15D
PT15C
VDDIO1
PT15A
PT14D
VREF_1_05
—
—
—
—
—
—
—
—
L21C_A0
L21T_A0
—
—
L22C_A1
L22T_A1
—
—
L23C_D1
70
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
C14
1 (TC)
6
IO
PT14C
VREF_1_06
L23T_D1
W18
B14
E15
D14
C4
A13
B13
—
1 (TC)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
6
1
1
—
1
1
VSS
IO
IO
IO
VDDIO0
IO
IO
VSS
PT14A
PT13D
PT13C
VDDIO0
PT13B
PT13A
—
—
MPI_RTRY_N
MPI_ACK_N
—
—
VREF_0_01
—
—
L1C_A0
L1T_A0
—
L2C_A0
L2T_A0
A12
B12
W19
D13
E14
B11
A10
D2
E13
D12
C11
B10
—
A9
D11
B9
Y13
A8
E12
C10
D3
D10
C9
0 (TL)
0 (TL)
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
0 (TL)
0 (TL)
0 (TL)
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
1
1
—
2
2
2
2
—
2
2
3
3
—
3
3
3
—
3
3
3
—
4
4
IO
IO
VSS
IO
IO
IO
IO
VDDIO0
IO
IO
IO
IO
VDD15
IO
IO
IO
VSS
IO
IO
IO
VDDIO0
IO
IO
PT12D
PT12C
VSS
PT12B
PT12A
PT11D
PT11C
VDDIO0
PT11B
PT11A
PT10D
PT10C
VDD15
PT10A
PT9D
PT9C
VSS
PT9A
PT8D
PT8C
VDDIO0
PT7D
PT7C
M0
M1
—
MPI_CLK
M2
M3
—
VREF_0_02
MPI_TEA_N
—
—
—
—
VREF_0_03
—
—
—
D0
TMS
—
A20/MPI_BDIP_N
A19/MPI_TSZ1
L3C_A0
L3T_A0
—
L4C_A0
L4T_A0
L5C_A0
L5T_A0
—
L6C_A0
L6T_A0
L7C_A0
L7T_A0
—
—
L8C_D1
L8T_D1
—
—
L9C_D1
L9T_D1
—
L10C_A0
L10T_A0
Y14
E11
D9
E1
A7
B8
E10
C8
Y15
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
—
4
4
—
4
4
5
5
—
VSS
IO
IO
VDDIO0
IO
IO
IO
IO
VSS
VSS
PT6D
PT6C
VDDIO0
PT6B
PT6A
PT5D
PT5C
VSS
—
A18/MPI_TSZ0
D3
—
VREF_0_04
—
D1
D2
—
—
L11C_D1
L11T_D1
—
L12C_A0
L12T_A0
L13C_D1
L13T_D1
—
71
A21/MPI_BURST_N
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
B7
0 (TL)
5
IO
A6
D8
B6
E3
C7
A5
C6
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
5
5
5
—
5
5
6
IO
IO
IO
VDDIO0
IO
IO
IO
B5
Y20
E9
D7
C5
D6
E8
E7
A4
B4
—
E6
D5
Y21
AK26
P18
—
P19
R16
R17
R18
R19
R34
0 (TL)
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
6
6
6
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T13
T14
T15
T20
T21
T22
T34
U13
U14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Additional Function
BM680 Pair
PT5B
—
L14C_A0
PT5A
PT4D
PT4C
VDDIO0
PT4B
PT4A
PT3D
VREF_0_05
TDI
TCK
—
—
—
—
L14T_A0
L15C_D1
L15T_D1
—
L16C_D1
L16T_D1
L17C_A0
IO
VSS
IO
IO
IO
IO
IO
IO
O
IO
VDD15
IO
VDD33
VSS
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
PT3C
VSS
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PCFG_MPI_IRQ
PCCLK
VDD15
PDONE
VDD33
VSS
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VREF_0_06
—
—
—
PLL_CK1C/PPLL
PLL_CK1T/PPLL
—
—
CCLK
—
DONE
—
—
—
—
—
—
—
—
—
—
—
L17T_A0
—
L18C_D1
L18T_D1
L19C_A0
L19T_A0
L20C_A0
L20T_A0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
72
CFG_IRQ_N/MPI_IRQ_N
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
U15
—
—
VDD15
VDD15
—
—
U20
U21
U22
V13
V14
V15
V20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V21
V22
V34
W13
W14
W15
W20
W21
W22
W34
Y16
Y17
Y18
Y19
AA16
AA17
AA18
AA19
AA34
AB16
AB17
AB18
AB19
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AB34
AD33
AD34
AE34
AG33
AG34
AH34
AK29
AL32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
73
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 16. PBGA Pinout Table
BM68
0
VDDIO
Bank
VREF
Group
I/O
Pin Description
Additional Function
BM680 Pair
AL33
—
—
VDD15
VDD15
—
—
AL34
AM31
AM33
AM34
AN32
AP31
AN34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VSS
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AP1
AP4
AP33
AP34
Y22
AP24
AD1
—
—
—
—
—
5 (BC)
7 (CL)
—
—
—
—
—
—
—
VSS
VSS
VSS
VSS
VSS
VDDIO5
VDDIO7
VSS
VSS
VSS
VSS
VSS
VDDIO5
VDDIO7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: The pin descriptions for RX_DAT_IN* and TX_DAT_OUT show both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid
depending on the mode of operation.
74
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all the
parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials,
the amount of copper in the test board or system board, and system airflow.
ΘJA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.):
J – TA
Θ JA = T
-------------------
Q
Where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest, and
the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The
package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip’s heater resistor, the chip’s
temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note
that ΘJA is expressed in units of °C/W.
ψJC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal
resistance, and it is defined by:
ψ JC = T J – T C
------------------Q
Where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the ΘJA measurements described above, besides the other parameters measured, an additional temperature
reading, TC, is made with a thermocouple attached at top-dead-center of the case. ψJC is also expressed in units of
°C/W.
ΘJC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of
the package. It is defined by:
J – TC
Θ JC = T
-------------------
Q
The parameters in this equation have been defined above. However, the measurements are performed with the
case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the
top of the package. It is this difference in the measurement process that differentiates ΘJC from ψJC. ΘJC is a true
thermal resistance and is expressed in units of °C/W.
ΘJB
This is the thermal resistance from junction to board (ΘJL). It is defined by:
J – TB
Θ JB = T
-------------------
Q
Where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters
on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads.
Note that ΘJB is expressed in units of °C/W, and that this parameter and the way it is measured are still in JEDEC
committee.
75
Lattice Semiconductor
ORCA ORLI10G Data Sheet
FPSC Maximum Junction Temperature
Once the power dissipated by the FPSC has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the
device from the 85 ˚C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in ˚C), the maximum junction temperature is approximated by:
TJmax = TAmax + (Q * ΘJA)
Table 17 lists the thermal characteristics for all packages used with the ORCA ORLI10G FPSC.
Package Thermal Characteristics
Table 17. ORCA ORLI10G Plastic Package Thermal Guidelines
ΘJA (˚C/W)
Package
680-Pin PBGAM
Max Power
0 fpm
200 fpm
500 fpm
T = 70 ˚C Max
TJ = 125 ˚C Max
0 fpm (W)
13.4
11.5
10.5
4.10
Note: The 680-Pin PBGAM package includes a 2 oz. copper plate.
The ORLI10G in a 680 PBGAM1T package has ΘJC of 3.5 deg C/W.
Heat Sink Vendors for BGA Packages
The estimated worst-case power requirements for the ORLI10G with a programmable XGMII to XSBI interface for
10 Gbits/s Ethernet applications is 4 W to 5 W. Consequently, for most applications an external heat sink will be
required. Below, in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the BGA market.
Table 18. Heat Sink Vendors
Vendor
Location
Phone
Aavid Thermalloy
Chip Coolers (Tyco Electronics)
IERC (CTS Corp.)
R-Theta
Sanyo Denki
Wakefield Thermal Solutions
Concord, NH
Harrisburg, PA
Burbank, CA
Buffalo, NY
Torrance, CA
Pelham, NH
(603) 224-9988
(800) 468-2023
(818) 842-7277
(800) 388-5428
(310) 783-5400
(603) 635-2800
Package Coplanarity
The coplanarity limits of the packages are as follows:
• PBGAM: 8.0 mils
76
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the
package parasitics. Table 19 lists eight parasitics associated with the ORCA packages. These parasitics represent
the contributions of all components of a package, which include the bond wires, all internal package routing, and
the external leads.
Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual
inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and
inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed
to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading
effect of the lead. Resistance values are in mΩ.
The parasitic values in Table 19 are for the circuit model of bond wire and package lead parasitics. If the mutual
capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be
added to each of the C1 and C2 capacitors.
Table 19. ORCA ORLI10G Package Parasitics
Package Type
680-Pin PBGAM
LSW
LMW
RW
C1
C2
CM
LSL
LML
3.80
1.30
250
0.50
1.0
0.30
2.8—5.0
0.5—1.50
Figure 34. Package Parasitics
LSW
LSL
RW
CIRCUIT
BOARD PAD
PAD N
C1
LMW CM
C2
LML
PAD N + 1
LSW
LSL
RW
C1
C2
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by
the application of the allowance and the tolerance.
Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance.
Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified
or repeated basic size if a tolerance is not specified.
Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is
a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.
77
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Package Outline Diagrams (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00
+ 0.70
30.00 – 0.00
A1 BALL
IDENTIFIER ZONE
35.00
+ 0.70
30.00 – 0.00
1.170
0.61 ± 0.08
SEATING PLANE
0.20
SOLDER BALL
0.50 ± 0.10
2.51 MAX
33 SPACES @ 1.00 = 33.00
AP
AN
AM
AL
AK
AJ
AH
AG
AF
0.64 ± 0.15
AE
AD
AC
AB
AA
Y
W
33 SPACES
@ 1.00 = 33.00
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 BALL
CORNER
1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25 27 29 31 33
10 12 14 16 18 20 22 24 26 28 30 32 34
5-4406(F)
78
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Ordering Information
Figure 35. Part Number Description
ORLI10G - X XXX XXX X
Device Family
ORLI10G
Grade
C = Commercial
I = Industrial
Speed Grade
3 = Fastest
2=
1 = Slowest
Ball Count
Package Type
BM = Fine-Pitch Plastic Ball Grid Array (PBGAM)
BMN = Lead-Free Fine-Pitch Plastic Ball Grid Array (PBGAM)
Table 20. Device Type Options
Device
ORLI10G
Voltage
1.5 V internal
3.3 V/2.5 V/1.8 V/1.5 V I/O
Table 21. Temperature Range
Symbol
C
I
Description
Commercial
Industrial
Ambient Temperature
0 ˚C to +70 ˚C
–40 ˚C to +85 ˚C
Junction Temperature
0 ˚C to +85 ˚C
–40 ˚C to +100 ˚C
Table 22. Conventional Packaging – Commercial Ordering Information1
Device Family
ORLI10G
Part Number
ORLI10G-3BM680C
ORLI10G-2BM680C
ORLI10G-1BM680C
Speed
Grade
3
2
1
Package Type
PBGAM (fpBGA)
PBGAM (fpBGA)
PBGAM (fpBGA)
Ball
Count
680
680
680
Grade
C
C
C
Ball
Count
680
680
Grade
I
I
Table 23. Conventional Packaging – Industrial Ordering Information1
Device Family
ORLI10G
Part Number
ORLI10G-2BM680I
ORLI10G-1BM680I
Speed
Grade
2
1
Package Type
PBGAM (fpBGA)
PBGAM (fpBGA)
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed
grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
Table 24. Lead-Free Packaging – Commercial Ordering Information1
Device Family
ORLI10G
Part Number
ORLI10G-3BMN680C
ORLI10G-2BMN680C
ORLI10G-1BMN680C
Speed
Grade
3
2
1
79
Package Type
Lead-Free PBGAM (fpBGA)
Lead-Free PBGAM (fpBGA)
Lead-Free PBGAM (fpBGA)
Ball
Count
680
680
680
Grade
C
C
C
Lattice Semiconductor
ORCA ORLI10G Data Sheet
Table 25. Lead-Free Packaging – Industrial Ordering Information1
Device Family
ORLI10G
Part Number
ORLI10G-2BMN680I
ORLI10G-1BMN680I
Speed
Grade
2
1
Package Type
Lead-Free PBGAM (fpBGA)
Lead-Free PBGAM (fpBGA)
Ball
Count
680
680
Grade
I
I
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed
grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
80