LTC2704 Quad 12-, 14- and 16-Bit Voltage Output SoftSpan DACs with Readback U FEATURES DESCRIPTIO ■ The LTC®2704-16/LTC2704-14/LTC2704-12 are serial input, 12-, 14- or 16-bit, voltage output SoftSpan™ DACs that operate from 3V to 5V logic and ±5V to ±15V analog supplies. SoftSpan offers six output spans—two unipolar and four bipolar—fully programmable through the 3-wire SPI serial interface. INL is accurate to 1LSB (2LSB for the LTC2704-16). DNL is accurate to 1LSB for all versions. ■ ■ ■ ■ ■ ■ ■ ■ Six Programmable Output Ranges: Unipolar: 0V to 5V, 0V to 10V Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V Serial Readback of All On-Chip Registers 1LSB INL and DNL Over the Industrial Temperature Range (LTC2704-14/LTC2704-12) Force/Sense Outputs Enable Remote Sensing Glitch Impulse: < 2nV-sec Outputs Drive ±5mA Pin Compatible 12-, 14- and 16-Bit Parts Power-On and Clear to Zero Volts 44-Lead SSOP Package Readback commands allow verification of any on-chip register in just one 24- or 32- bit instruction cycle. All other commands produce a “rolling readback” response from the LTC2704, dramatically reducing the needed number of instruction cycles. U APPLICATIO S ■ ■ ■ ■ A Sleep command allows any combination of DACs to be powered down. There is also a reset flag and an offset adjustment pin for each channel. Process Control and Industrial Automation Direct Digital Waveform Generation Software Controlled Gain Adjustment Automated Test Equipment , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. W W SI PLIFIED BLOCK DIAGRA AGND V+ 1 32 42 V– REFM1 REFG1 REF1 REF2 REFG2 REFM2 V+2 1,8,15,22,31,36 44 2 43 24 21 23 LTC2704-16 Integral Nonlinearity (INL) 25 VOSB 40 C1B 39 RFBB 37 DAC C DAC B OUTB 38 27 VOSC 1.0 28 C1C 0.8 30 RFBC 0.6 26 AGNDC VOSA 4 19 VOSD INL (LSB) –1 –1 0.2 0 –0.2 C1A 5 18 C1D –0.4 RFBA 7 16 RFBD –0.6 DAC A DAC D 17 OUTD OUTA 6 AGNDA 3 20 AGNDD 33 34 GND VDD 10 13 11 14 CS/LD SCK SDI CLR 9 35 12 LDAC RFLAG SRO ALL 4 DACS SUPERIMPOSED 0.4 29 OUTC AGNDB 41 V+/V – = ±15V VREF = 5V ±10V RANGE –0.8 –1.0 0 16384 32768 CODE 49152 65535 2704 BD 2704 TA01b 2704f 1 LTC2704 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Total Supply Voltage V+1, V+2 to V – ........... –0.3V to 36V V+1, V+2, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx to GND, AGND, AGNDx, C1x, REFG1, REFG2 ................................... 18V GND, AGND, AGNDx, C1x, REFG1, REFG2 to V+1, V+2, V –, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx ............................................................... 18V OUTA, RFBA, VOSA, OUTB, RFBB, VOSB, REF1, REFM1 to GND, AGND ............... V– – 0.3V to V+1 + 0.3V OUTC, RFBC, VOSC, OUTD, RFBD, VOSD, REF2, REFM2 to GND, AGND ........................... V– – 0.3V to V+2 + 0.3V VDD, Digital Inputs/Outputs to GND ............. –0.3V to 7V Digital Inputs/Outputs to VDD ................................. 0.3V GND, AGNDx, REFG1, REFG2 to AGND ................ ±0.3V C1x to AGNDx ....................................................... ±0.3V V– to Any Pin .......................................................... 0.3V Maximum Junction Temperature ......................... 150°C Operating Temperature Range LTC2704C ............................................... 0°C to 70°C LTC2704I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW V– 1 44 REFM1 REFG1 2 43 REF1 AGNDA 3 42 V+1 VOSA 4 41 AGNDB C1A 5 40 VOSB OUTA 6 39 C1B RFBA 7 38 OUTB V– 8 37 RFBB LDAC 9 36 V– CS/LD 10 35 RFLAG SDI 11 34 VDD SRO 12 33 GND SCK 13 32 AGND CLR 14 31 V– V– LTC2704CGW-16 LTC2704IGW-16 LTC2704CGW-14 LTC2704IGW-14 LTC2704CGW-12 LTC2704IGW-12 15 30 RFBC RFBD 16 29 OUTC OUTD 17 28 C1C C1D 18 27 VOSC VOSD 19 26 AGNDC 25 V+2 AGNDD 20 REFG2 21 24 REF2 V – 22 23 REFM2 GW PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 80°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER Accuracy Resolution Monotonicity INL Integral Nonlinearity DNL Differential Nonlinearity GE Gain Error Gain Temperature Coefficient VOS Unipolar Zero-Scale Error LTC2704-12 MIN TYP MAX CONDITIONS ● ● VREF = 5V VREF = 5V VREF = 5V ∆Gain/∆Temperature Span = 0V to 5V, TA = 25°C Span = 0V to 10V, TA = 25°C Span = 0V to 5V Span = 0V to 10V 12 12 14 14 ● ● ● ±0.5 ±2 ● ● ±80 ±100 ±140 ±150 ● LTC2704-14 MIN TYP MAX ±1 ±1 ±2 ±200 ±300 ±400 ±600 LTC2704-16 MIN TYP MAX 16 16 ±1 ±2 ±80 ±100 ±140 ±150 ±1 ±1 ±5 ±200 ±300 ±400 ±600 ±4 ±2 ±80 ±100 ±140 ±150 ±2 ±1 ±20 ±200 ±300 ±400 ±600 UNITS Bits Bits LSB LSB LSB ppm/°C µV µV µV µV 2704f 2 LTC2704 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER VOS Temperature Coefficient BZE Bipolar Zero Error PSRR Power Supply Rejection Ratio CONDITIONS 0V to 5V Range 0V to 10V Range All Bipolar Ranges ● ● ● VDD = 5V ±10% (Note 3) VDD = 3V ±10% (Note 3) 0V to 10V Range, Code = 0 ● V+/V– = ±15V ±10% (Note 2) V+/V– = ±5V ±10%, VREF = 2V (Note 2) ● LTC2704-12 MIN TYP MAX ±2 ±2 ±0.25 ±1 ±2 ±0.003 ±0.006 LTC2704-14 MIN TYP MAX ±2 ±2 ±0.5 ±2 ±2.5 ±0.013 ±0.025 ±0.001 ±0.06 ±0.002 ±0.05 ±0.005 ±0.25 ±0.01 ±0.13 Analog Outputs (Note 4) Settling Time ISC SR 0V to 5V Range, 5V Step, to ±1LSB 0V to 10V or ±5V Range, 10V Step, to ±1LSB ±10V Range, 20V Step, to ±1LSB Output Swing V+/V– = ±15V, VREF = ±7.25V, 0V to 10V Range, ILOAD = ±3mA (Note 2) V+/V– = ±5V, VREF = ±2.25V, 0V to 10V Range, ILOAD = ±3mA (Note 2) Load Current V+/V– = ±10.8V to ±16.5V, VREF = ±5V, 0V to 10V Range, VOUT = ±10V (Note 2) V+/V– = ±4.5V to ±16.5V, VREF = ±2V, 0V to 10V Range, VOUT = ±4V (Note 2) Load Regulation V+/V– = ±15V, VREF = 5V, 0V to 10V Range, Code = 0, ±5mA Load (Note 2) V+/V– = ±5V, VREF = 2V, 0V to 10V Range, Code = 0, ±3mA Load (Note 2) Output VREF = 5V, 0V to 10V Range, Impedance Code = 0, ±5mA Load Short-Circuit V+/V– = ±16.5V, VREF = 5V, ±10V Range Current Code = 0, VOUT Shorted to V+ (Note 2) Code = Full Scale, VOUT Shorted to V– V+/V– = ±5.5V, VREF = 2V, ±10V Range Code = 0, VOUT Shorted to V+ (Note 2) Code = Full Scale, VOUT Shorted to V– Slew Rate RL= 2k, V+/V– = ±15V (Note 2) RL= 2k, V+/V– = ±5V (Note 2) Capacitive Load Within Maximum Load Current Driving LTC2704-16 MIN TYP MAX ±2 ±2 ±2 ±8 ±10 ±0.05 ±0.1 UNITS µV/°C µV/°C LSB LSB LSB/V LSB/V ±0.02 ±0.04 LSB/V LSB/V ±1 ±0.5 3 3.5 4 µs 5 8 5.5 9 6 10 ● –14.5 14.5 –14.5 14.5 –14.5 14.5 µs µs V ● –4.5 4.5 –4.5 4.5 –4.5 4.5 V ● ±5 ±5 ±5 mA ● ±3 ±3 ±3 mA ● ±0.005 ±0.01 ±0.04 LSB/mA ● ±0.01 ±0.013 ±0.05 LSB/mA ● 0.015 0.006 0.006 Ω 38 mA mA 38 mA mA V/µs V/µs pF ● ● ● ● ● ● 38 –36 38 –36 –36 38 –36 2.2 2.0 3 2.8 1000 38 –36 2.2 2.0 3 2.8 1000 –36 2.2 2.0 3 2.8 1000 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER Reference Inputs REF1, REF2 Input Voltage Resistances RREF1, RREF2 Reference Input Resistance RFBx Output Feedback Resistance RVOSX Offset Adjust Input Resistance CONDITIONS V+/V– = ±15V, 0V to 5V Span (Note 2) MIN ● –14.5 ● 5 7 700 ● ● TYP 7 10 1000 MAX UNITS 14.5 V kΩ kΩ kΩ 2704f 3 LTC2704 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER AC Performance (Note 4) Glitch Impulse Crosstalk Digital Feedthrough Multiplying Feedthrough Error Multiplying Bandwidth Output Noise Voltage Density Output Noise Voltage Power Supply IDD Supply Current, VDD IS Supply Current, V+/V– VDD Logic Supply Voltage V+1/V+2 Positive Analog Supply Voltage V– Negative Analog Supply Voltage Digital Inputs/Outputs VIH Digital Input High Voltage VIL Digital Input Low Voltage VOH VOL IIN CIN Digital Output High Voltage Digital Output Low Voltage Digital Input Current Digital Input Capacitance CONDITIONS MIN 0V to 5V Range, Midscale Transition 10V Step on VOUTA DAC B: 0V to 5V Range, Full Scale DAC B: 0V to 10V Range, Full Scale ±10V Range, Midscale 0V to 10V Range, VREF = ±5V, 10kHz Sine Wave Span = 0V to 5V, Full Scale Span = 0V to 10V, Full Scale 10kHz Span = 0V to 5V, Midscale Span = 0V to 10V, Midscale 0.1Hz to 10Hz Span = 0V to 5V, Midscale Span = 0V to 10V, Midscale Digital Inputs = 0V or VDD V+/V– = ±15V, ±10%; VREF = 5V, VOUT = 0V (Note 2) V+/V– = ±5V, ±10%; VREF = 2V, VOUT = 0V (Note 2) Sleep Mode—All DACs (Note 4) ● ● 2.7 4.5 –16.5 ● ● 2.4 2.0 nV-s nV-s nV-s nV-s mVP-P kHz kHz 30 50 nV/√Hz nV/√Hz 0.8 1.2 µVRMS µVRMS ● ● 2 20 18 1 5.5 16.5 – 4.5 0.6 0.8 ● VCC – 0.4 ● ● VIN = 0V (Note 3) UNITS 2 3 0.2 0.35 300 250 0.5 17.5 17.0 ● ● ● ● WU TI I G CHARACTERISTICS MAX 2 ● VDD = 2.7V to 5.5V VDD = 2.7V to 3.3V VDD = 2.7V to 5.5V VDD = 4.5V to 5.5V IOH = 200µA IOL = 200µA TYP 0.001 ● 0.4 ±1 5 µA mA mA mA V V V V V V V V V µA pF The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER VDD = 4.5V to 5.5V t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold t3 SCK High Time t4 SCK Low Time t5 CS/LD Pulse Width t6 LSB SCK High to CS/LD High t7 CS/LD Low to SCK Positive Edge t8 CS/LD High to SCK Positive Edge t9 SRO Propagation Delay t10 CLR Pulse Width CONDITIONS MIN ● ● ● ● ● ● ● ● CLOAD = 10pF MAX 7 7 11 11 9 0 12 12 ● ● TYP 18 50 UNITS ns ns ns ns ns ns ns ns ns ns 2704f 4 LTC2704 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL t11 t12 t13 PARAMETER LDAC Pulse Width CLR Low to RFLAG Low CS/LD High to RFLAG High SCK Frequency VDD = 2.7V to 3.3V t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold t3 SCK High Time t4 SCK Low Time t5 CS/LD Pulse Width t6 LSB SCK High to CS/LD High t7 CS/LD Low to SCK Positive Edge t8 CS/LD High to SCK Positive Edge t9 SRO Propagation Delay t10 CLR Pulse Width t11 LDAC Pulse Width t12 CLR Low to RFLAG Low t13 CS/LD High to RFLAG High SCK Frequency CONDITIONS MIN 15 ● ● CLOAD = 10pF (Note 3) CLOAD = 10pF (Note 3) 50% Duty Cycle (Note 5) ● ● ● ● ● ● ● ● ● ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 26 ● 90 20 ● ● CLOAD = 10pF CLOAD = 10pF 50% Duty Cycle (Note 5) UNITS ns ns ns MHz 9 9 15 15 12 0 12 12 ● CLOAD = 10pF MAX 50 40 40 ● Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The notation V+ is used to denote both V+1 and V+2 when the same voltage is applied to both pins. Note 3: Guaranteed by design, not subject to test. TYP 70 60 25 ● ● Note 4: Measured in unipolar 0V to 5V mode. Note 5: When using SRO, maximum SCK frequency fMAX is limited by SRO propagation delay as follows: ⎛ ⎞ 1 fMAX = ⎜ ⎟ , where ts is the setup time of the receiving ⎝ 2 (t 9 + t S)⎠ device. U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16 Differential Nonlinearity (DNL) INL vs VREF V+/V – = ±15V 0.8 VREF = 5V ±10V RANGE 0.6 V+/V– = ±15V 0.8 VREF = 5V ±10V RANGE 0.6 1.0 0.4 0.4 0.4 0.2 0.2 0.2 1.0 0 –0.2 V+/V– = ±15V 0.8 ±5V RANGE 0.6 INL (LSB) DNL (LSB) INL (LSB) Integral Nonlinearity (INL) 1.0 0 –0.2 0 –0.4 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 16384 32768 CODE 49152 65535 2704 G01 0 16384 32768 CODE 49152 65535 2704 G02 MIN MAX MIN –0.2 –0.6 0 MAX –1.0 –10 –8 –6 –4 –2 0 2 VREF (V) 4 6 8 10 2704 G03 2704f 5 LTC2704 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16 DNL vs Temperature INL vs Temperature 0.8 0.6 V+/V– = ±15V 1.0 V+/V– = ±15V VREF = 5V ±10V RANGE 0.8 VREF = 5V ±10V RANGE 0.6 0.2 0 MIN –0.2 0.2 0 –0.4 –O.6 –O.6 –0.8 –0.8 –30 30 50 –10 10 TEMPERATURE (°C) 70 90 MAX MIN –0.2 –0.4 –1.0 –50 400 0.4 MAX DNL (LSB) INL (LSB) 0.4 Offset vs Temperature 600 OFFSET (µV) 1.0 –1.0 –50 –30 30 50 –10 10 TEMPERATURE (°C) 70 –600 –50 90 –30 30 50 –10 10 TEMPERATURE (°C) 2704 G05 70 90 2704 G06 Gain Error vs Temperature V+/V– = ±15V 16 VREF = 5V ±10V RANGE 12 V+/V– = ±15V VREF = 5V ±10V RANGE 8 GAIN ERROR (LSB) 4 2 LSB 0 –400 Bipolar Zero vs Temperature 6 200 –200 2704 G04 8 V+/V– = ±15V VREF = 5V 0V TO 10V RANGE 0 –2 4 0 –4 –4 –8 –6 –12 –8 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 –16 –50 90 –30 30 50 –10 10 TEMPERATURE (°C) 2704 G07 Settling 0V to 5V Settling ±10V VOUT 5V/DIV VOUT 10V/DIV VOUT 1mV/DIV VOUT 1mV/DIV VOUT 1mV/DIV CS/LD 5V/DIV CS/LD 5V/DIV CS/LD 5V/DIV 2.5µs/DIV 2704 G18 90 2704 G08 Settling 0V to 10V VOUT 5V/DIV 70 2.5µs/DIV 2704 G19 2.5µs/DIV 2704 G20 2704f 6 LTC2704 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-14 Integral Nonlinearity (INL) 1.0 1.0 V+/V– = ±15V VREF = 5V ±10V RANGE 0.8 0.6 V+/V– = ±15V VREF = 5V ±10V RANGE 0.8 0.6 0.4 0.4 0.2 0.2 LSB LSB Differential Nonlinearity (DNL) 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 4096 8192 CODE 12288 0 16383 4096 8192 CODE 2704 G09 12288 16383 2704 G10 LTC2704-12 Integral Nonlinearity (INL) V+/V– = ±15V 1.0 0.8 VREF = 5V ±10V RANGE 0.8 0.6 V+/V– = ±15V VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.2 LSB LSB Differential Nonlinearity (DNL) 1.0 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 512 1536 1024 2048 2560 3072 3584 4095 CODE 0 512 1536 1024 2048 2560 3072 3584 4095 CODE 2704 G11 2704 G12 LTC2704-16/LTC2704-14/LTC2704-12 Positive Slew Midscale Glitch Negative Slew CS/LD 5V/DIV 5V/DIV 5V/DIV VOUT 2mV/DIV V+/V– = ±15V VREF = 5V ±10V RANGE 20V STEP 2.5µs/DIV 2704 G13 V+/V– = ±15V VREF = 5V ±10V RANGE 20V STEP 2.5µs/DIV 2704 G14 2.5µs/DIV 2704 G15 2704f 7 LTC2704 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16/LTC2704-14/LTC2704-12 VCC Supply Current vs Logic Voltage 0.1Hz to 10Hz Noise 3.5 3.0 VDD = 5V SCK, SDI, CS/LD, LDAC CLR TIED TOGETHER 2.5 ICC (mA) 1µV/DIV 2.0 1.5 1.0 V+/V– = ±15V VREF = 5V 0V TO 5V RANGE CODE = 0 1s/DIV 2704 G16 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC VOLTAGE (V) 2704 G17 U U U PI FU CTIO S V– (Pins 1, 8, 15, 22, 31, 36): Analog Negative Supply, Typically –15V. –4.5V to –16.5V Range. LDAC (Pin 9): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated. REFG1 (Pin 2): Reference 1 Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. CS/LD (Pin 10): Synchronous Chip Select and Load Pin. AGNDA (Pin 3): DAC A Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. SRO (Pin 12): Serial Readback Data Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the last address bit A0 is clocked in. VOSA (Pin 4): Offset Adjust for DAC A. Nominal input range is ±5V. VOS(DAC A) = –0.01• V(VOSA) [0V to 5V, ±2.5V modes]. See Operation section. SCK (Pin 13): Serial Clock. C1A (Pin 5): Feedback Capacitor Connection for DAC A Output. This pin provides direct access to the negative input of the channel A output amplifier. OUTA (Pin 6): DAC A Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBA as close to the load as possible. RFBA (Pin 7): DAC A Output Feedback Resistor Pin. SDI (Pin 11): Serial Data Input. Data is clocked in on the rising edge of the serial clock when CS/LD is low. CLR (Pin 14): Asynchronous Clear Pin. When this pin is low, all code and span B2 registers are cleared to zero. All DAC outputs are cleared to zero volts. RFBD (Pin 16): DAC D Voltage Output Feedback Resistor Pin. OUTD (Pin 17): DAC D Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBD as close to the load as possible. 2704f 8 LTC2704 U U U PI FU CTIO S C1D (Pin 18): Feedback Capacitor Connection for DAC D Output. This pin provides direct access to the negative input of the channel D output amplifier. RFBC (Pin 30): DAC C Output Feedback Resistor Pin. AGND (Pin 32): Analog Ground Pin. Tie to clean analog ground. VOSD (Pin 19): Offset Adjust for DAC D. Nominal input range is ±5V. VOS(DAC D) = –0.01• V(VOSD) [0V to 5V, ±2.5V modes]. See Operation section. GND (Pin 33): Ground Pin. Tie to clean analog ground. AGNDD (Pin 20): DAC D Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. RFLAG (Pin 35): Reset Flag Pin. An active low output is asserted when there is a power on reset or a clear event. Returns high when an update command is executed. REFG2 (Pin 21): Reference 2 Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. RFBB (Pin 37): DAC B Output Feedback Resistor Pin. REFM2 (Pin 23): Reference 2 Inverting Amp Output. The gain from REF2 to REFM2 is –1. Can swing to within 0.5V of the analog supplies V+/V–. VDD (Pin 34): Logic Supply. 2.7V to 5.5V Range. OUTB (Pin 38): DAC B Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBB as close to the load as possible. REF2 (Pin 24): DAC C and DAC D Reference Input. C1B (Pin 39): Feedback Capacitor Connection for DAC B Output. This pin provides direct access to the negative input of the channel B output amplifier. V+2 (Pin 25): Analog Positive Supply for DACs C and D. Typically 15V. 4.5V to 16.5V Range. Can be different from V +1. VOSB (Pin 40): Offset Adjust for DAC B. Nominal input range is ±5V. VOS(DAC B) = –0.01 • V(VOSB) [0V to 5V, ±2.5V modes]. See Operation section. AGNDC (Pin 26): DAC C Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. AGNDB (Pin 41): DAC B Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. VOSC (Pin 27): Offset Adjust for DAC C. Nominal input range is ±5V. VOS(DAC C) = –0.01• V(VOSC) [0V to 5V, ±2.5V modes]. See Operation section. V+1 (Pin 42): Analog Positive Supply for DACs A DND B. Typically 15V. 4.5V to 16.5V Range. Can be different from V +2. C1C (Pin 28): Feedback Capacitor Connection for DAC C Output. This pin provides direct access to the negative input of the channel C output amplifier. REF1 (Pin 43): DAC A and DAC B Reference Input. OUTC (Pin 29): DAC C Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBC as close to the load as possible. REFM1 (Pin 44): Reference 1 Inverting Amp Output. The gain from REF1 to REFM1 is –1. Can swing to within 0.5V of the analog supplies V+/V–. 2704f 9 LTC2704 W BLOCK DIAGRA 42 V– 1,8,15,22,31,36 V+1 43 REF1 32 25 AGND V+2 REF2 27 40 38 41 C1C RFBB RFBC OUTB AGNDB OUTC DAC C DAC B + – + – + AGNDC 7 6 3 44 2 29 26 19 C1A C1D RFBA RFBD OUTA AGNDA 30 VOSD VOSA 4 5 28 – + 37 C1B – 39 24 VOSC VOSB OUTD DAC D DAC A + – + – AGNDD REFM1 REFM2 REFG1 REFG2 COMMAND DECODE INPUT SHIFT REGS CS/LD SCK SDI 10 13 11 DAC BUFFERS SRO READBACK SHIFT REGS CLR LDAC 14 9 RFLAG 35 VDD GND 33 34 18 16 17 20 23 21 12 POR 2704 BD WU W TI I G DIAGRA t1 t2 t3 1 SCK 2 t6 t4 31 32 t8 SDI LSB t5 t7 CS/LD t11 LDAC t9 SRO Hi-Z LSB 2704 TD 2704f 10 LTC2704 U OPERATIO SERIAL INTERFACE When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock signal (SCK pin). The minimum (24-bit wide) loading sequence required for the LTC2704 is a 4-bit command word (C3 C2 C1 C0), followed by a 4-bit address word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB first. Figure 1 shows the SDI input word syntax to use when writing a code or span. If a 32-bit input sequence is needed, the first eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. Figure 2 shows the input and readback sequences for both 24-bit and 32-bit operations. When CS/LD is low, the Serial Readback Output (SRO) pin is an active output. The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted into SDI. For a 24-bit load sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. For a 32-bit load sequence, add 8 to these clock cycle counts; see Figure 2b. When CS/LD is high, the SRO pin presents a high impedance (three-state) output. At the beginning of a load sequence, when CS/LD is taken low, SRO outputs a logic low until the readback data begins. When the asynchronous load pin, LDAC, is taken low, all DACs are updated with code and span data (data in B1 buffers is copied into B2 buffers). CS/LD must be high during this operation. The use of LDAC is functionally identical to the “Update B1→B2” commands. The codes for the command word (C3-C0) are defined in Table 1; Table 2 defines the codes for the address word (A3-A0). READBACK Each DAC has two pairs of double-buffered digital registers, one pair for DAC code and the other for the output span (four buffers per DAC). Each double-buffered pair comprises two registers called buffer 1 (B1) and buffer 2 (B2). B1 is the holding buffer. When data is shifted into B1 via a write operation, DAC outputs are not affected. The contents of B2 can only be changed by copying the contents of B1 into B2 via an update operation (B1 and B2 can be changed together, see commands 0110-1001 in Table 1). The contents of B2 (DAC code or DAC span) directly control the DAC output voltage or the DAC output range. Additionally each DAC has one readback register associated with it. When a readback command is issued to a DAC, the contents of one of its four buffers is copied into its readback register and serially shifted out onto the SRO pin. Figure 2 shows the loading and readback sequences. In the 16-bit data field (D15-D0 for the LTC2704-16, see Figure 2a) of any write or update command, the readback pin (SRO) shifts out the contents of the buffer which was specified in the preceding command. This “rolling readback” mode of operation can be used to reduce the number of operations, since any command can be verified during succeeding commands with no additional overhead. Table 1 shows the location (readback pointer) of the data which will be output from SRO during the next instruction. For readback commands, the data is shifted out during the readback instruction itself (on the 16 falling SCK edges immediately after the last address bit is shifted in on SDI). When programming the span of a DAC, the span bits are the last four bits shifted in; and when checking the span of a DAC using SRO, the span bits are likewise the last four bits shifted out. Table 3 shows the span codes. When span information is read back on SRO, the sleep status of the addressed DAC is also output. The sleep status bit, SLP, occurs sequentially just before the four span bits. The sequence is shown in Figures 2a and 2b. See Table 4 for SLP codes. Note that SLP is an output bit only; sleep is programmed by using command code 1110 along with the desired address. Any update command, including the use of LDAC, wakes the addressed DAC(s). 2704f 11 LTC2704 U OPERATIO OUTPUT RANGES The LTC2704 is a quad DAC with software-programmable output ranges. SoftSpan provides two unipolar output ranges (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and – 2.5V to 7.5V). These ranges are obtained when an external precision 5V reference and analog supplies of ±12V to ±15V are used. When a reference voltage of 2V and analog supplies of ±5V are used, the SoftSpan ranges become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to 3V. The output ranges are linearly scaled for references other than 2V and 5V (appropriate analog supplies should be used within the range ±5V to ±15V). Each of the four DACs can be programmed to any one of the six output ranges. DAC outputs can swing to ±10V on ±10.8V supplies (±12V supplies with ±10% tolerance) while sourcing or sinking 5mA of load current. Table 1. Command Codes C3 CODE C2 C1 C0 COMMAND READBACK POINTER— CURRENT INPUT WORD W0 READBACK POINTER— NEXT INPUT WORD W+1 0 0 1 0 Write to B1 Span DAC n Set by Previous Command B1 Span DAC n 0 0 1 1 Write to B1 Code DAC n Set by Previous Command B1 Code DAC n 0 1 0 0 Update B1→B2 DAC n Set by Previous Command B2 Span DAC n 0 1 0 1 Update B1→B2 All DACs Set by Previous Command B2 Code DAC A 0 1 1 0 Write to B1 Span DAC n Update B1→B2 DAC n Set by Previous Command B2 Span DAC n 0 1 1 1 Write to B1 Code DAC n Update B1→B2 DAC n Set by Previous Command B2 Code DAC n 1 0 0 0 Write to B1 Span DAC n Update B1→B2 All DACs Set by Previous Command B2 Span DAC n 1 0 0 1 Write to B1 Code DAC n Update B1→B2 All DACs Set by Previous Command B2 Code DAC n 1 0 1 0 Read B1 Span DAC n B1 Span DAC n 1 0 1 1 Read B1 Code DAC n B1 Code DAC n 1 1 0 0 Read B2 Span DAC n B2 Span DAC n 1 1 0 1 Read B2 Code DAC n 1 1 1 0 Sleep DAC n (Note 1) Set by Previous Command B2 Span DAC n 1 1 1 1 No Operation Set by Previous Command B2 Code DAC n B2 Code DAC n Codes not shown are reserved and should not be used. Note 1: Normal operation can be resumed by issuing any update B1→B2 command to the sleeping DAC. Table 3. Span Codes Table 2. Address Codes A3 A2 A1 A0 n READBACK POINTER n S3 S2 S1 S0 SPAN 0 0 0 0 DAC A DAC A 0 0 0 0 Unipolar 0V to 5V 0 0 1 0 DAC B DAC B 0 0 0 1 Unipolar 0V to 10V 0 1 0 0 DAC C DAC C 0 0 1 0 Bipolar –5V to 5V 0 1 1 0 DAC D DAC D 0 0 1 1 Bipolar –10V to 10V 1 1 1 1 All DACs DAC A 0 1 0 0 Bipolar – 2.5V to 2.5V 0 1 0 1 Bipolar –2.5V to 7.5V Codes not shown are reserved and should not be used. Codes not shown are reserved and should not be used. 2704f 12 SDI C3 C3 LTC2704-12 LTC2704-14 LTC2704-16 (WRITE SPAN) C3 LTC2704-14 (WRITE CODE) LTC2704-12 (WRITE CODE) C3 LTC2704-16 (WRITE CODE) C1 C1 C1 C1 CONTROL WORD C2 CONTROL WORD C2 CONTROL WORD C2 CONTROL WORD C2 C0 C0 C0 C0 A3 A3 A3 A3 A1 A1 A1 A1 ADDRESS WORD A2 ADDRESS WORD A2 ADDRESS WORD A2 ADDRESS WORD A2 A0 A0 A0 A0 0 D11 MSB D13 MSB D15 MSB 0 D9 D11 D13 0 D8 D10 D12 0 D7 D9 D11 D6 D8 D10 D5 0 12 ZEROS 0 D7 D6 0 D4 0 D3 D5 16-BIT CODE D8 14-BIT CODE D7 D9 12-BIT CODE Figure 1. Input Words 0 D10 D12 D14 0 D2 D4 D6 0 D1 D3 D5 0 D0 LSB D2 D4 S3 0 D1 D3 0 S1 SPAN S2 0 D0 LSB S0 0 2 ZEROS 0 D1 4 ZEROS 0 D0 LSB D2 2704 F01 LTC2704 U OPERATIO 2704f 13 14 0 0 0 3 0 0 0 0 0 8 ZEROS 0 4 C1 3 0 5 0 0 0 6 0 0 0 0 0 7 0 0 C0 4 0 0 0 8 0 0 A3 A2 6 A1 7 0 0 C3 C2 10 0 0 C1 11 0 0 A0 8 0 0 0 0 CONTROL WORD 9 0 0 ADDRESS WORD 5 0 0 C0 12 0 D15 D15 9 0 D13 D13 11 0 D12 D12 12 0 D11 D11 13 0 D10 D10 14 D8 16 0 D9 0 D8 A1 15 0 0 0 0 ADDRESS WORD A2 14 0 0 A0 16 0 D15 D15 17 0 D14 D14 18 32-BIT DATA STREAM D6 D15 SRO t1 0 D11 D11 21 0 D6 D15 0 D12 D12 20 0 D7 t3 17 0 D10 t2 22 0 D5 D9 23 21 24 S3 D3 D3 D8 SLEEP STATUS SLP D4 D4 20 D7 25 t8 0 t4 D9 D14 D14 0 D8 18 0 D7 23 S1 D1 D1 D6 26 SPAN S2 D2 D2 22 0 D6 DAC CODE OR DAC SPAN 19 D5 D10 18 SDI SCK 0 D13 D13 19 Figure 2b. 32-Bit Load Sequence 0 0 A3 13 D7 17 DAC CODE OR DAC SPAN D9 15 Figure 2a. 24-Bit Load Sequence 0 D14 D14 10 0 D5 D5 27 SLP D4 D4 28 29 S3 D3 D3 2704 F02a SLEEP STATUS S0 D0 D0 24 31 S1 D1 D1 SPAN S2 D2 D2 30 S0 D0 D0 32 2704 F02b U OPERATIO READBACK SPAN 0 READBACK SPAN Hi-Z 0 0 0 2 0 C2 READBACK CODE 0 Hi-Z 0 1 Hi-Z READBACK CODE Hi-Z SRO 0 0 SRO SDI SCK CS/LD SRO SRO C3 SDI 2 CONTROL WORD 1 SCK CS/LD 24-BIT DATA STREAM LTC2704 2704f LTC2704 U OPERATIO Examples 1. Using a 24-bit loading sequence, load DAC A with the unipolar range of 0V to 10V, output at zero volts and all other DACs with the bipolar range of ±10V, outputs at zero volts. Note all DAC outputs should change at the same time. a) CS/LD↓ b) Clock SDI = 0010 1111 0000 0000 0000 0011 c) CS/LD↑ B1-Range of all DACs set to bipolar ±10V. d) CS/LD↓ Clock SDI = 0010 0000 0000 0000 0000 0001 e) CS/LD↑ B1-Range of DAC A set to unipolar 0V to 10V. f) CS/LD↓ Clock SDI = 0011 1111 1000 0000 0000 0000 g) CS/LD↑ B1-Code of all DACs set to midscale. h) CS/LD↓ Clock SDI = 0011 0000 0000 0000 0000 0000 i) CS/LD↑ B1-Code of DAC A set to zero code. j) CS/LD↓ Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX k) CS/LD↑ Update all DACs B1s into B2s for both Code and Range. l) Alternatively steps j and k could be replaced with LDAC . 2. Using a 32-bit load sequence, load DAC C with bipolar ±2.5V and its output at zero volts. Use readback to check B1 contents before updating the DAC output (i.e., before copying B1 contents into B2). a) CS/LD↓ (Note that after power-on, the Code in B1 is zero) b) Clock SDI = 0000 0000 0011 0100 1000 0000 0000 0000 c) CS/LD↑ B1-Code of DAC C set to midscale setting. d) CS/LD↓ Clock SDI = 0000 0000 0010 0100 0000 0000 0000 0100 e) Read Data out on SRO = 1000 0000 0000 0000 Verifies that B1-Code DAC C is at midscale setting. f) CS/LD↑ B1-Range of DAC C set to Bipolar ±2.5V range. g) CS/LD↓ Clock SDI = 0000 0000 1010 0100 xxxx xxxx xxxx xxxx Data Out on SRO = 0000 0000 0000 0100 Verifies that B1-Range of DAC C set to Bipolar ±2.5V Range. CS/LD↑ h) CS/LD↓ Clock SDI = 0000 0000 0100 0100 xxxx xxxx xxxx xxxx i) CS/LD↑ Update DAC C B1 into B2 for both Code and Range j) Alternatively steps h and i could be replaced with LDAC . 2704f 15 LTC2704 U OPERATIO System Offset Adjustment Many systems require compensation for overall system offset, which may be an order of magnitude or more greater than the excellent offset of the LTC2704. The LTC2704 has individual offset adjust pins for each of the four DACs. VOSA, VOSB, VOSC and VOSD are referred to their corresponding signal grounds, AGNDA, AGNDB, AGNDC and AGNDD. For noise immunity and ease of adjustment, the control voltage is attenuated to the DAC output: VOS = –0.01 • V(VOSx) [0V to 5V, ±2.5V spans] VOS = –0.02 • V(VOSx) [0V to 10V, ±5V, –2.5V to 7.5V spans] VOS = –0.04 • V(VOSx) [±10V span] The nominal input range of these pins is ±5V; other reference voltages of up to ±15V may be used if needed. The VOSx pins have an input impedance of 1MΩ. To preserve the settling performance of the LTC2704, these pins should be driven with a Thevenin-equivalent impedance of 10kΩ or less. If not used, they should be shorted to their respective signal grounds, AGNDx. POWER-ON RESET AND CLEAR When power is first applied to the LTC2704, all DACs power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC outputs are zero volts. When the CLR pin is taken low, a system clear results. The command and address shift registers, and the code and configuration B2 buffers, are reset to 0; the DAC outputs are all reset to zero volts. The B1 buffers are left intact, so that any subsequent “Update B1→B2” command (including the use of LDAC) restores the addressed DACs to their respective previous states. If CLR is asserted during an operation, i.e., when CS/LD is low, the operation is aborted. Integrity of the relevant input (B1) buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear, or if the logic supply VDD dips below approximately 2V; and stays asserted until any valid update command is executed. SLEEP MODE When a sleep command (C3 C2 C1 C0 = 1110) is issued, the addressed DAC or DACs go into power-down mode. DACs A and B share a reference inverting amplifier as do DACs C and D. If either DAC A or DAC B (similarly for DACs C and D) is powered down, its shared reference inverting amplifier remains powered on. When both DAC A and DAC B are powered down together, their shared reference inverting amplifier is also powered down (similarly for DACs C and D). To determine the sleep status of a particular DAC, a direct read span command is performed by addressing the DAC and reading its status on the readback pin SRO. The fifth LSB is the sleep status bit (see Figures 2a and 2b). Table 4 shows the sleep status bit’s functionality. Table 4. Readback Sleep Status Bit SLP STATUS 0 DAC n Awake 1 DAC n in Sleep Mode 2704f 16 LTC2704 U W U U APPLICATIO S I FOR ATIO Overview The LTC2704 is a highly integrated device, greatly simplifying design and layout as compared to a design using multiple current output DACs and separate amplifiers. A similar design using four separate current output DACs would require six precision op amps, compensation capacitors, bypass capacitors for each amplifier, several times as much PCB area and a more complicated serial interface. Still, it is important to avoid some common mistakes in order to achieve full performance. DC752A is the evaluation board for the LTC2704. It is designed to meet all data sheet specifications, and to allow the LTC2704 to be integrated into other prototype circuitry. All force/ sense lines are available to allow the addition of current booster stages or other output circuits. The DC752A design is presented as a tutorial on properly applying the LTC2704. This board shows how to properly return digital and analog ground currents, and how to compensate for small differences in ground potential between the two banks of two DACs. There are other ways to ground the LTC2704, but the one requirement is that analog and digital grounds be connected at the LTC2704 by a very low impedance path. It is NOT advisable to split the ground plane and connect them with a jumper or inductor. When in doubt, use a single solid ground plane rather than separate planes. The LTC2704 does allow the ground potential of the DACs to vary by ±300mV with respect to analog ground, allowing compensation for ground return resistance. Power Supply Grounding and Noise LTC2704 V+ and V– pins are the supplies to all of the output amplifiers, ground sense amplifiers and reference inversion amplifiers. These amplifiers have good power supply rejection, but the V+ and V– supplies must be free from wideband noise. The best scheme is to prefilter low noise regulators such as the LT®1761 (positive) and LT1964 (negative). Refer to Linear Technology Application Note 101, Minimizing Switching Regulator Residue in Linear Regulator Outputs. The LTC2704 VDD pin is the supply for the digital logic and analog DAC switches and is very sensitive to noise. It must be treated as an analog supply. The evaluation board uses an LT1790 precision reference as the VDD supply to minimize noise. The GND pin is the return for digital currents and the AGND pin is a bias point for internal analog circuitry. Both of these pins must be tied to the same point on a quiet ground plane. Each DAC has a separate ground sense pin that can be used to compensate for small differences in ground potential within a system. Since DACs A and B are associated with REF1 and DACs C and D are associated with REF2, the grounds must be grouped together as follows: AGNDA, AGNDB and REFG1 tied together (“GND1” on DC752A) AGNDC, AGNDD and REFG2 tied together (“GND2” on DC752A) This scheme allows compensation for ground return IR drops, as long as the resistance is shared by both DACs in a group. This implies that the ground return for DACs A and B must be as close as possible, and GND1 must be connected to this point through a low current, low resistance trace. (Similar for DACs C and D.) Figure 3 shows the top layer of the evaluation board. The GND1 trace connects REFG1, AGNDA, AGNDB and the ground pin of the LT1236 precision reference (U4.) This point is the ground reference for DACs A and B. The GND2 trace connects REFG2, AGNDC, AGNDD and the ground pin of the other LT1236 precision reference (U5). This point is the ground reference for DACs C and D. Voltage Reference A high quality, low noise reference such as the LT1236 or LT1027 must be used to achieve full performance. The ground terminal of this reference must be connected directly to the common ground point. If GND1 and GND2 are separate, then two references must be used. 2704f 17 LTC2704 U W U U APPLICATIO S I FOR ATIO Voltage Output/Feedback and Compensation The LTC2704 provides separate voltage output and feedback pins for each DAC. This allows compensation for resistance between the output and load, or a current boosting stage such as an LT1970 may be inserted without affecting accuracy. When OUTx is connected directly to RFBx and no additional capacitance is present, the internal frequency compensation is sufficient for stability and is optimized for fast settling time. If a low bandwidth booster stage is used, then a compensation capacitor from OUTx to C1x may be required. Similarly, extra compensation may be required to drive a heavy capacitive load. POWER AND LOAD RETURN CURRENTS FLOW IN THIS REGION EXPOSED GROUND PLANE AROUND EDGE ALLOWS GROUNDING TO PROTOTYPE CIRCUITS VOUTA AND VOUTB LOAD RETURN CURRENTS FLOW IN THIS REGION WHEN JP8 IS SET TO “TIE” VOUTC AND VOUTD LOAD RETURN CURRENTS FLOW IN THIS REGION WHEN JP9 IS SET TO “TIE” 2704 F03 GND1 TRACE, SEPARATED FROM AGND UNDER LTC2704 GND2 TRACE, SEPARATED FROM AGND UNDER LTC2704 2704 F05 DIGITAL RETURN CURRENTS FLOW IN THIS REGION Figure 3. DC752 Top Layer Figure 5. DC752A Load Return, Power Return and Digital Return 2704 F04 CUTOUT PREVENTS DIGITAL RETURN CURRENTS FROM COUPLING INTO ANALOG GROUND PLANE. NOTE THAT THERE IS A PLANE IN THIS REGION ON LAYER 3 Figure 4. DC752 Analog Ground Layer. No Currents are Returned to this Plane, so it May be Used as a Reference Point for Precise Voltage Measurements 2704 F06 SMALL GROUND POUR ALLOWS LOW IMPEDANCE BYPASSING OF V+ AND V – Figure 6. DC752A Routing, Bypass 2704f 18 LTC2704 U PACKAGE DESCRIPTIO GW Package 44-Lead Plastic SSOP (Wide .300 Inch) (Reference LTC DWG # 05-08-1642) 44 23 1.40 ±0.127 17.73 – 17.93* (.698 – .706) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 10.804 MIN 7.75 – 8.258 10.11 – 10.55 (.398 – .415) 1 0.520 ±0.0635 22 0.800 BSC RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 0.254 – 0.406 × 45° (.010 – .016) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0.355 REF 2.286 – 2.388 (.090 – .094) 2.44 – 2.64 (.096 – .104) 0° – 8° TYP 0.231 – 0.3175 (.0091 – .0125) 0.40 – 1.27 (.015 – .050) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.800 (.0315) BSC 0.28 – 0.51 (.011 – .02) TYP 0.1 – 0.3 (.004 – .0118) G44 SSOP 0204 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 2704f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2704 U TYPICAL APPLICATIO Evaluation Board Schematic. Force/Sense Lines Allow for Remote Sensing and Optimal Grounding VDD OUTA BAV99LT1 1 10k 9 LDAC CS/LD VDD SPI INTERFACE VDD 10k 1k SDI SRO SCK 10 11 12 13 14 CLR 35 RFLAG LDAC VOSA CS/LD C1A SDI RFBA SRO OUTA SCK AGNDA RFLAG VOSB C1B REMOTE 20k VOSx REFMx 5V 2 GND1 2 REF1 3 5VREF1 43 REFM1 44 REFG1 RFBB REF1 OUTB REFM1 AGNDB 3 5 REMOTE 7 OUTSA 6 OUTA 3 GND1 40 TIE 2 VOSA CLR REFx 1 4 OUTB BAV99LT1 1 2 VOSB 3 39 TIE REMOTE 37 OUTSB 38 OUTB 41 GND1 LTC2704 OFFSET ADJUSTMENT FOR VOSA, VOSB, VOSC, VOSC REMOTE 5V 21 1 GND2 2 REF2 3 5VREF2 24 REFM2 23 REFG2 VOSC REF2 C1C REFM2 RFBC BAT54S VDD 3 OUTC AGNDC REF REGULATOR 1 1 2 14 5V 33 0.1µF 32 VS 15V 7V 1 1 VDD VOSD GND C1D 2 GND 0.1µF OUTD AGNDD V+1 V+2 GND 1 2 25 4.7µF 15V –15V 4.7µF 25V 4.7µF 25V 5VREF1 VS 0.1µF 2 LT1236ACS8-5 6 VOUT VIN 5 TRIM GND 0.1µF 42 OUTSC 29 OUTC 26 OUTC 1 GND2 19 2 VOSD 18 4 4 GND1 GND2 TIE REMOTE OUTSD 17 OUTD 20 OUTD 1 GND2 V– 2 1,8,15,22,31,36 1µF BAV99LT1 3 TIE REMOTE 1µF GND1 1 5VREF2 2 LT1236ACS8-5 6 VOUT VIN 5 TRIM GND BAV99LT1 3 16 –15V 1µF VS 4.7µF 30 15V 1µF 15V RFBD AGND 4 LT1790ACS6-5 6 VIN VOUT 2 VOSC 28 VDD 2 VDD 3 27 3 1 2 2 3 GND2 1 TIE 3 REMOTE 1 2 2 3 TIE REMOTE 4.7µF GND1 –15V BAT54S GND2 BAT54S RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT 1019 Precision Reference Ultralow Drift, 3ppm/°C, 0.05% Accuracy LT1236 Precision Reference Ultralow Drift, 10ppm/°C, 0.05% Accuracy LTC1588/LTC1589 LTC1592 12-/14-/16-Bit, Serial, SoftSpan IOUT DACs Software-Selectable Spans, ±1LSB INL/DNL LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors LTC1650 16-Bit Serial VOUT DAC Low Power, Low Gritch, 4-Quadrant Multiplication LTC1857/LTC1858 LTC1859 12-/14-/16-Bit, Serial 100ksps SoftSpan ADC Software-Selectable Spans, 40mW, Fault Protected to ±25V LT1970 500mA Power Op Amp Adjustable Sink/Source Current Limits ® 2704f 20 Linear Technology Corporation LT/LWI 0806 • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006