TLV320AIC23 Stereo Audio CODEC, 8Ć to 96ĆkHz, With Integrated Headphone Amplifier Data Manual July 2001 Digital Audio Products SLWS106C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Analog Line Input to Line Output . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Stereo Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Analog Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Digital-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Audio Interface (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Audio Interface (Slave-Mode) . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Three-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 Two-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Use the AIC23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Microphone Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Line Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Analog Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Sidetone Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1–1 1–1 1–3 1–4 1–4 1–5 2–1 2–1 2–1 2–2 2–2 2–3 2–3 2–4 2–4 2–4 2–4 2–5 2–5 2–6 2–7 2–7 3–1 3–1 3–1 3–1 3–2 3–5 3–5 3–5 3–6 3–6 3–7 3–7 iii 3.3 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 3.3.1 Digital Audio-Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . 3–7 3.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 iv List of Illustrations Figure Title 2–1 System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . 2–5 Two-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . 3–1 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 2-Wire I2C Compatible Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Analog Line Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Microphone Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Right-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Left-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 I2S Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 DSP Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Digital De-Emphasis Filter Response – 441 kHz Sampling . . . . . . . . . . . . . 3–10 Digital De-Emphasis Filter Response – 48 kHz Sampling . . . . . . . . . . . . . 3–11 ADC Digital Filter Response I: TI DSP and Normal Modes (Group Delay = 12 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12 ADC Digital Filter Ripple I: TI DSP and Normal Modes (Group Delay = 20 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 ADC Digital Filter Response II: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . 3–14 ADC Digital Filter Ripple II: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . . . . 3–15 ADC Digital Filter Response III: TI DSP and Normal Modes (Group Delay = 3 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 ADC Digital Filter Ripple III: TI DSP and Normal Modes . . . . . . . . . . . . . . . 3–17 ADC Digital Filter Response IV: TI DSP Mode Only . . . . . . . . . . . . . . . . . . 3–18 ADC Digital Filter Ripple IV: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . . . . 3–19 DAC Digital Filter Response I: TI DSP and Normal Modes . . . . . . . . . . . . 3–20 DAC Digital Filter Ripple I: TI DSP and Normal Modes . . . . . . . . . . . . . . . . 3–21 DAC Digital Filter Response II: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . 3–22 DAC Digital Filter Ripple II: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . . . . 3–23 DAC Digital Filter Response III: TI DSP and Normal Modes . . . . . . . . . . . 3–24 DAC Digital Filter Ripple III: TI DSP and Normal Modes . . . . . . . . . . . . . . . 3–25 DAC Digital Filter Response IV: TI DSP Mode Only . . . . . . . . . . . . . . . . . . 3–26 DAC Digital Filter Ripple IV: TI DSP Mode Only . . . . . . . . . . . . . . . . . . . . . . Page 2–5 2–5 2–6 2–7 2–7 3–1 3–2 3–5 3–6 3–7 3–8 3–8 3–8 3–12 3–12 3–13 3–13 3–14 3–14 3–15 3–15 3–16 3–16 3–17 3–17 3–18 3–18 3–19 3–19 3–20 3–20 v vi 1 Introduction The TLV320AIC23 is a high-performance stereo audio codec with highly integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23 use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling high-quality digital audio-playback capability, while consuming less than 23 mW during playback only. The TLV320AIC23 is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder applications, such as MP3 digital audio players. Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule biasing. The AIC23 has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the output signals if a sidetone is required. While the TLV320AIC23 supports the industry-standard oversampling rates of 256 fs and 384 fs, unique oversampling rates of 250 fs and 272 fs are provided, which optimize interface considerations in designs using TI C54x digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A single 12-MHz crystal can supply clocking to the DSP, USB, and codec. The TLV320AIC23 features an internal oscillator that, when connected to a 12-MHz external crystal, provides a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz, using an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1 kHz are supported directly from a 12-MHz master clock with 250 fs and 272 fs oversampling rates. Low power consumption and flexible power management allow selective shutdown of codec functions, thus extending battery life in portable applications. This design solution, coupled with the industry’s smallest package, the TI proprietary MicroStar Junior using only 25 mm2 of board area, makes powerful portable stereo audio designs easily realizable in a cost-effective, space-saving total analog I/O solution: the TLV320AIC23. 1.1 Features • High-Performance Stereo Codec – – – – – • Software Control Via TI McBSP-Compatible Multiprotocol Serial Port – – • 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz) 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz) 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages 8-kHz – 96-kHz Sampling-Frequency Support I2C-Compatible and SPI-Compatible Serial-Port Protocols Glueless Interface to TI McBSPs Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface – – – I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC Standard I2S, MSB, or LSB Justified-Data Transfers 16/20/24/32-Bit Word Lengths MicroStar Junior is a trademark of Texas Instruments. 1–1 – – – • Integrated Total Electret-Microphone Biasing and Buffering Solution – – – • Low-Noise MICBIAS pin at 3/4 AVDD for Biasing of Electret Capsules Integrated Buffer Amplifier With Tunable Fixed Gain of 1 to 5 Additional Control-Register Selectable Buffer Gain of 0 dB or 20 dB Stereo-Line Inputs – – Integrated Programmable Gain Amplifier Analog Bypass Path of Codec • ADC Multiplexed Input for Stereo-Line Inputs and Microphone • Stereo-Line Outputs – Analog Stereo Mixer for DAC and Analog Bypass Path • Analog Volume Control With Mute • Highly Efficient Linear Headphone Amplifier – • • 23-mW Power Consumption During Playback Mode Standby Power Consumption <150 µW Power-Down Power Consumption <15 µW Industry’s Smallest Package: 32-Pin TI Proprietary MicroStar Junior – – • 30 mW into 32 Ω From a 3.3-V Analog Supply Voltage Flexible Power Management Under Total Software Control – – – 1–2 Audio Master/Slave Timing Capability Optimized for TI DSPs (250/272 fs), USB mode Industry-Standard Master/Slave Support Provided Also (256/384 fs), Normal mode Glueless Interface to TI McBSPs 25 mm2 Total Board Area 28-Pin TSSOP Also Is Available (62 mm2 Total Board Area) Ideally Suitable for Portable Solid-State Audio Players and Recorders 1.2 Functional Block Diagram VADC AVDD 1.0X 50 kΩ DSPcodec TLV320AIC23 VDAC VMID 1.0X VMID 50 kΩ 1.0X AGND CS Control Interface 1.5X MICBIAS SDIN SCLK MODE 12 to –34.5 dB, 1.5 dB Steps Σ–∆ ADC 2:1 MUX Line Mute RLINEIN Bypass Mute, Mute 0 dB, 20 dB 50 kΩ 10 kΩ VADC MICIN VMID 12 to –34 dB, 1.5 dB Steps HPVDD HPGND Headphone Driver 6 to –73 dB, 1 dB Steps Σ–∆ ADC 2:1 MUX Line Mute LLINEIN Side Tone Mute BVDD DGND Bypass Mute Σ RHPOUT DVDD Digital Filters Σ–∆ DAC ROUT VDAC LOUT Σ LHPOUT Headphone Driver 6 to –73 dB, 1 dB Steps Σ–∆ DAC CLKIN Divider (1x, 1/2x) LRCIN XTI/MCLK XTO OSC CLKOUT Divider (1x, 1/2x) CLKOUT Digital Audio Interface DIN LRCOUT DOUT BCLK NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other. 1–3 1.3 Terminal Assignments NC XTO DVDD DGND BVDD CLKOUT BCLK DIN NC GQE PACKAGE (TOP VIEW) 25 24 23 22 21 20 19 18 17 28 14 SDIN HPVDD 29 13 MODE LHPOUT 30 12 CS RHPOUT 31 11 LLINEIN HPGND 32 10 RLINEIN 1 2 3 4 5 6 7 8 9 NC LRCOUT MICIN SCLK MICBIAS 15 VMID 27 AGND DOUT AVDD XTI/MCLK ROUT 16 LOUT 26 NC LRCIN NC – No internal connection PW PACKAGE (TOP VIEW) BVDD CLKOUT BCLK DIN LRCIN DOUT LRCOUT HPVDD LHPOUT RHPOUT HPGND LOUT ROUT AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DGND DVDD XTO XTI/MCLK SCLK SDIN MODE CS LLINEIN RLINEIN MICIN MICBIAS VMID AGND 1.4 Ordering Information PACKAGE 1–4 TA 32-Pin MicroStar Junior GQE 28-Pin TSSOP PW –10°C to 70°C TLV320AIC23GQE TLV320AIC23PW –40°C to 85°C TLV320AIC23IGQE TLV320AIC23IPW 1.5 Terminal Functions TERMINAL NAME NO. DESCRIPTION I/O GQE PW AGND 5 15 AVDD 4 14 BCLK 23 3 BVDD 21 1 CLKOUT 22 2 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Bit 07 in the sample rate control register controls frequency selection. CS 12 21 I Control port input latch/address select. For SPI control mode this input acts as the data latch control. For I2C control mode this input defines the seventh bit in the device address field. See Section 3.1 for details. DIN 24 4 I I2S format serial data input to the sigma-delta stereo DAC DGND 20 28 DOUT 27 6 O Digital supply return I2S format serial data output from the sigma-delta stereo ADC DVDD 19 27 Digital supply input. Voltage range is 3.3 V nominal. HPGND 32 11 Analog headphone amplifier supply return HPVDD 29 8 LHPOUT 30 9 O Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of –73 dB to 6 dB is provided in 1-dB steps. LLINEIN 11 20 I Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB steps. LOUT 2 12 O LRCIN 26 5 I/O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS. I2S DAC-word clock signal. In audio master mode, the AIC23 generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. LRCOUT 28 7 I/O I2S ADC-word clock signal. In audio master mode, the AIC23 generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. MICBIAS 7 17 O Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4 AVDD nominal. MICIN 8 18 I Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a default gain of 5 is provided. See Section 2.3.1.2 for details. 13 22 I Serial-interface-mode input. See Section 3.1 for details. MODE NC Analog supply return I/O Analog supply input. Voltage level is 3.3 V nominal. I2S serial-bit clock. In audio master mode, the AIC23 generates this signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. Buffer supply input. Voltage range is from 2.7 V to 3.6 V. Analog headphone amplifier supply input. Voltage level is 3.3 V nominal. 1, 9 17, 25 Not Used—No internal connection RHPOUT 31 10 O Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of –73 dB to 6 dB is provided in 1-dB steps. RLINEIN 10 19 I Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB steps. ROUT 3 13 O SCLK 15 24 I Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS. Control-port serial-data clock. For SPI and I2C control modes this is the serial-clock input. See Section 3.1 for details. SDIN 14 23 I Control-port serial-data input. For SPI and I2C control modes this is the serial-data input and also is used to select the control protocol after reset. See Section 3.1 for details. VMID 6 16 I Midrail voltage decoupling input. 10-µF and 0.1-µF capacitors should be connected in parallel to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal. XTI/MCLK 16 25 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23. XTO 18 26 O Crystal output. Connect to external crystal for applications where the AIC23 is the audio timing master. Not used in applications where external clock source is used. 1–5 1–6 2 Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 3.63 V Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 3 .63 V Input voltage range, all input signals: Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: DVDD may not exceed BVDD + 0.3V; BVDD may not exceed AVDD + 0.3V or HPVDD + 0.3. 2.2 Recommended Operating Conditions MIN NOM MAX 2.7 3.3 3.6 V Digital buffer supply voltage, BVDD (see Note 2) 2.7 3.3 3.6 V Digital core supply voltage, DVDD (see Note 2) 1.42 1.5 3.6 V Analog supply voltage, AVDD, HPVDD (see Note 2) Analog input voltage, full scale – 0dB (AVDD = 3.3 V) Stereo-line output load resistance Headphone-amplifier output load resistance 1 UNIT 10 VRMS kΩ 0 Ω CLKOUT digital output load capacitance 20 pF All other digital output load capacitance 10 pF Stereo-line output load capacitance 50 XTI master clock Input ADC or DAC conversion rate Operating free-air temperature, TA –10 NOTE 2: Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND. pF 18.43 MHz 96 kHz 70 °C 2–1 2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/MCLK = 256fs, fs = 48 kHz (unless otherwise stated) 2.3.1 ADC 2.3.1.1 Line Input to ADC PARAMETER TEST CONDITIONS MIN Input signal level (0 dB) TYP MAX 1 fs = 48 kHz (3.3 V) fs = 48 kHz (2.7 V) Signal-to-noise ratio,, A-weighted, (see Notes 3 g g , 0-dB gain g ( and 4) 85 90 dB 90 Dynamic y range, g , A-weighted, g , –60-dB full-scale input ((see Note 4) AVDD = 3.3 V AVDD = 2.7 V distortion –1-dB 1 dB input, input 0-dB 0 dB gain Total harmonic distortion, AVDD = 3.3 V AVDD = 2.7 V Power supply rejection ratio 1 kHz, 100 mVpp 50 dB ADC channel separation 1 kHz input tone 90 dB Programmable gain 1 kHz input tone, RSOURCE < 50 Ω Programmable gain step size Monotonic 1.5 dB Mute attenuation 0 dB, 1 kHz input tone 80 dB Input resistance 85 UNIT VRMS 90 dB 90 –80 dB 80 –34.5 12 dB Input gain 10 0 dB input gain 30 Input capacitance 12 20 35 10 dB kΩ pF NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. 4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 2.3.1.2 Microphone Input to ADC, 0-dB Gain, fs = 8 kHz (40-KΩ Source Impedance, see Section 1.2, Functional Block Diagram) PARAMETER TEST CONDITIONS MIN Input signal level (0 dB) TYP 1.0 UNIT VRMS Signal to noise ratio, Signal-to-noise ratio A-weighted, A weighted 0-dB 0 dB gain (see Notes 3 and 4) AVDD = 3.3 V AVDD = 2.7 V 80 Dynamic range, range A-weighted, A weighted –60-dB 60 dB full-scale full scale input (see Note 4) AVDD = 3.3 V AVDD = 2.7 V 80 Total harmonic distortion, distortion –1-dB 1 dB input, input 0-dB 0 dB gain AVDD = 3.3 V AVDD = 2.7 V Power supply rejection ratio 1 kHz, 100 mVpp 50 dB Programmable gain boost 1 kHz input tone, RSOURCE < 50 Ω 20 dB Microphone-path gain MICBOOST = 0, RSOURCE < 50 Ω 14 dB Mute attenuation 0 dB, 1 kHz input tone 60 80 dB 8 14 kΩ 10 pF Input resistance Input capacitance 85 MAX 84 85 84 –60 –60 dB dB dB NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. 4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 2–2 2.3.1.3 Microphone Bias PARAMETER TEST CONDITIONS Bias voltage MIN TYP MAX 3/4 AVDD – 100 m 3/4 AVDD 3/4 AVDD + 100 m V 3 mA Bias-current source Output noise voltage 2.3.2 1 kHz to 20 kHz UNIT 25 nV/√Hz DAC 2.3.2.1 Line Output, Load = 10 kΩ, 50 pF PARAMETER TEST CONDITIONS MIN TYP 90 100 0-dB full-scale output voltage (FFFFFF) 1.0 Signal to noise ratio, Signal-to-noise ratio A-weighted, A weighted 0-dB 0 dB gain (see Notes 3, 3 4, 4 and 5) AVDD = 3.3 V AVDD = 2.7 V Dynamic range, range A-weighted A weighted (see Note 4) AVDD = 3.3 V AVDD = 2.7 V 3V AVDD = 3 3.3 Total harmonic distortion AVDD = 2 2.7 7V Power supply rejection ratio MAX fs = 48kHz fs = 48 kHz VRMS dB 100 85 90 dB TBD 1 kHz, 0 dB –88 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –85 1 kHz, –3 dB –88 1 kHz, 100 mVpp DAC channel separation UNIT dB dB 50 dB 100 dB NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. 4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 5. Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz to 20-kHz bandwidth. 2.3.3 Analog Line Input to Line Output (Bypass) PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage Signal to noise ratio, Signal-to-noise ratio A-weighted, A weighted 0-dB 0 dB gain (see Notes 3 and 4) TYP MAX 1.0 AVDD = 3.3 V AVDD = 2.7 V AVDD = 3 3.3 3V Total harmonic distortion AVDD = 2 2.7 7V 90 UNIT VRMS 95 dB 95 1 kHz, 0 dB –86 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –86 1 kHz, –3 dB –92 dB dB Power supply rejection ratio 1 kHz, 100 mVpp 50 dB DAC channel separation (left to right) 1 kHz, 0 dB 80 dB NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. 4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 2–3 2.3.4 Stereo Headphone Output PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage TYP MAX 1.0 Maximum output power, PO Signal-to-noise ratio, A-weighted (see Note 4) RL = 32 Ω 30 RL = 16 Ω 40 AVDD = 3.3 V 90 AVDD = 3.3 V,, 1 kHz output Power supply rejection ratio 1 kHz, 100 mVpp Programmable gain 97 dB 1 kHz output 0.1 1.0 50 1 kHz output % dB –73 6 Programmable-gain step size Mute attenuation mW PO = 10 mW PO = 20 mW Total harmonic distortion UNIT VRMS dB 1 dB 80 dB NOTE 4: All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 2.3.5 Analog Reference Levels PARAMETER MIN TYP Reference voltage AVDD/2 – 50 mV Divider resistance 40 2.3.6 VIL VIH Input low level VOL VOH Output low level MIN V 60 kΩ TYP MAX UNIT 0.3 × BVDD V 0.7 × BVDD Input high level V 0.1 × BVDD 0.9 × BVDD Output high level V V Supply Current Total T t l supply l current, t No in ut signal input MIN TYP Record and playback (all active) 23 Record and playback (osc, clk, and MIC output powered down) 18 Line playback only 7 Record only 13 Analog bypass (line in to line out) 4 Power down 2–4 AVDD/2 + 50 mV 50 PARAMETER ITOT UNIT Digital I/O PARAMETER 2.3.7 MAX Oscillator enabled 1.5 Oscillator disabled 0.01 MAX UNIT mA 2.4 Digital-Interface Timing PARAMETER MIN High 18 Low 18 tw(1) tw(2) System clock pulse duration, System-clock duration MCLK/XTI tc(1) System-clock period, MCLK/XTI MAX Propagation delay, CLKOUT UNIT ns 54 Duty cycle, MCLK/XTI tpd(1) TYP ns 40/60% 60/40% 0 10 ns tc(1) tw(1) tw(2) MCLK/XTI tpd(1) CLKOUT CLKOUT (Div 2) Figure 2–1. System-Clock Timing Requirements 2.4.1 Audio Interface (Master Mode) PARAMETER MIN TYP MAX UNIT tpd(2) tpd(3) Propagation delay, LRCIN/LRCOUT 0 10 ns Propagation delay, DOUT 0 10 ns tsu(1) th(1) Setup time, DIN 10 ns Hold time, DIN 10 ns BCLK tpd(2) LRCIN LRCOUT tpd(3) DOUT DIN tsu(1) th(1) Figure 2–2. Master-Mode Timing Requirements 2–5 2.4.2 Audio Interface (Slave-Mode) PARAMETER tw(3) tw(4) Pulse duration duration, BCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(2) tpd(4) Clock period, BCLK 50 tsu(2) th(2) Setup time, DIN 10 ns Hold time, DIN 10 ns tsu(3) th(3) Setup time, LRCIN 10 ns Hold time, LRCIN 10 ns Propagation delay, DOUT 0 tc(2) tw(4) tw(3) BCLK LRCIN LRCOUT tsu(2) th(3) tsu(3) DIN tpd(2) th(2) DOUT Figure 2–3. Slave-Mode Timing Requirements 2–6 ns 10 ns 2.4.3 Three-Wire Control Interface (SDIN) PARAMETER tw(5) tw(6) Clock pulse duration, duration SCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(3) tsu(4) Clock period, SCLK 80 ns Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) th(4) Setup time, SDIN to SCLK 20 ns 20 ns tw(7) tw(8) Hold time, SCLK to SDIN Pulse duration, duration CS High 20 Low 20 ns tw(8) CS tc(3) tw(5) tw(6) tsu(4) SCLK tsu(5) th(4) DIN LSB Figure 2–4. Three-Wire Control Interface Timing Requirements 2.4.4 Two-Wire Control Interface (I2C) PARAMETER tw(9) duration SCLK Clock pulse duration, tw(10) MIN TYP MAX UNIT High 1.3 µs Low 600 ns f(sf) Clock frequency, SCLK th(5) tsu(6) Hold time (start condition) 600 0 400 Setup time (start condition) 600 th(6) tsu(7) Data hold time tr tf Rise time, SDIN, SCLK 300 ns Fall time, SDIN, SCLK 300 ns tsu(8) Setup time (stop condition) ns ns 900 Data setup time 100 600 tw(9) kHz ns ns ns tw(10) SCLK th(5) th(6) tsu(7) tsu(8) DIN Figure 2–5. Two-Wire Control Interface Timing Requirements 2–7 2–8 3 How to Use the TLV320AIC23 3.1 Control Interfaces The TLV320AIC23 has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (three-wire operation) and I2C (two-wire operation) specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level. MODE 3.1.1 0 INTERFACE I2C 1 SPI SPI In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the TLV320AIC23. The interface is compatible with microcontrollers and DSPs with an SPI interface. A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising edge on CS after the 16th rising clock edge latches the data word into the AIC (see Figure 3-1). The control word is divided into two parts. The first part is the address block, the second part is the data block: B[15:9] B[8:0] Control Address Bits Control Data Bits CS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SCLK SDIN B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 MSB B4 B3 B2 B1 B0 LSB Figure 3–1. SPI Timing 3.1.2 I2C In I2C mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start condition is a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine which device on the I2C bus receives the data. R/W determines the direction of the data transfer. The TLV320AIC23 is a write only device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting the state of the CS pin as follows. CS STATE (Default = 0) ADDRESS 0 0011010 1 0011011 3–1 The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2). The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block: B[15:9] B[8:0] Control Address Bits Control Data Bits Start Stop 1 SCLK 7 ADDR SDI 8 9 1 8 9 R/W ACK B15 – B8 ACK 1 8 9 B7 – B0 ACK Figure 3–2. 2-Wire I2C Compatible Timing 3.1.3 Register Map The TLV320AIC23 has the following set of registers, which are used to program the modes of operation. ADDRESS REGISTER 0000000 Left line input channel volume control 0000001 Right line input channel volume control 0000010 Left channel headphone volume control 0000011 Right channel headphone volume control 0000100 Analog audio path control 0000101 Digital audio path control 0000110 Power down control 0000111 Digital audio interface format 0001000 Sample rate control 0001001 Digital interface activation 0001111 Reset register Left line input channel volume control (Address: 0000000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function LRS LIM X X LIV4 LIV3 LIV2 LIV1 LIV0 Default 0 1 0 0 1 0 1 1 1 LRS LIM LIV[4:0] X 3–2 Left/right line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Left line input mute 0 = Normal 1 = Muted Left line input volume control (10111 = 0 dB default) 11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps Reserved Right Line Input Channel Volume Control (Address: 0000001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0 Default 0 1 0 0 1 0 1 1 1 RLS Right/left line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Right line input mute 0 = Normal 1 = Muted Right line input volume control (10111 = 0 dB default) 11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps Reserved RIM RIV[4:0] X Left Channel Headphone Volume Control (Address: 0000010) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 Default 0 1 1 1 1 1 0 0 1 LRS Left/right headphone channel simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Left-channel zero-cross detect Zero-cross detect 0 = Off 1 = On Left Headphone volume control (1111001 = 0 dB default) 1111111 = +6 dB down to 0000000 = –73 dB in 1-dB steps LZC LHV[6:0] Right Channel Headphone Volume Control (Address: 0000011) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 Default 0 1 1 1 1 1 0 0 1 RLS Right/left headphone channel simultaneous volume/mute Update Simultaneous update 0 = Disabled 1 = Enabled Right-channel zero-cross detect Zero-cross detect 0 = Off 1 = On Right headphone volume control (1111001 = 0 dB default) 1111111 = +6 dB down to 0000000 = –73 dB in 1-dB steps RZC RHV[6:0] Analog Audio Path Control (Address: 0000100) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X STA1 STA0 STE DAC BYP INSEL MICM MICB Default 0 0 0 0 1 0 0 1 0 STA[1:0] STE DAC BYP INSEL MICM MICB Sidetone attenuation Sidetone enable DAC select Bypass Input select for ADC Microphone mute Microphone boost X Reserved 00 = –6 dB 0 = Disabled 0 = DAC off 0 = Disabled 0 = Line 0 = Normal 0=OdB 01 = –9 dB 10 = –12 dB 1 = Enabled 1 = DAC selected 1 = Enabled 1 = Microphone 1 = Muted 1 = 20dB 11 = –15 dB 3–3 Digital Audio Path Control (Address: 0000101) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X DACM DEEMP1 DEEMP0 ADCHP Default 0 0 0 0 0 0 1 0 0 DACM DEEMP[1:0] ADCHP X DAC soft mute De-emphasis control ADC high-pass filter Reserved 0 = Disabled 00 = Disabled 0 = Disabled 1 = Enabled 01 = 32 kHz 1 = Enabled 10 = 44.1 kHz 11 = 48 kHz Power Down Control (Address: 0000110) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X OFF CLK OSC OUT DAC ADC MIC LINE Default 1 0 0 0 0 0 1 1 1 OFF CLK OSC OUT DAC ADC MIC LINE X Device power Clock Oscillator Outputs DAC ADC Microphone input Line input Reserved 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off Digital Audio Interface Format (Address: 0000111) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0 Default 0 0 0 0 0 0 0 0 1 MS LRSWAP LRP Master/slave mode DAC left/right swap DAC left/right phase IWL[1:0] FOR[1:0] Input bit length Data format X Reserved 0 = Slave 1 = Master 0 = Disabled 1 = Enabled 0 = Right channel on, LRCIN high 1 = Right channel on, LRCIN low DSP mode 1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge 0 = MSB is available on 1st BCLK rising edge after LRCIN rising edge 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit 11 = DSP format, frame sync followed by two data words 10 = I2S format, MSB first, left – 1 aligned 01 = MSB first, left aligned 00 = MSB first, right aligned NOTES: 1. In Master mode, the TLV320AIC23 supplies the BCLK, LRCOUT, and LRCIN. In Slave mode, BCLK, LRCOUT, and LRCIN are supplied to the TLV320AIC23. 2. In master mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate, BCLK = MCLK. Sample Rate Control (Address: 0001000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 1 0 0 0 0 0 CLKIN CLKOUT 3–4 Clock input divider Clock output divider 0 = MCLK 0 = MCLK 1 = MCLK/2 1 = MCLK/2 SR[3:0] BOSR Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2) Base oversampling rate USB mode: 0 = 250 fs 1 = 272 fs Normal mode: 0 = 256 fs 1 = 384 fs Clock mode select: 0 = Normal 1 = USB Reserved USB/Normal X Digital Interface Activation (Address: 0001001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X X ACT Default 0 0 0 0 0 0 0 0 1 ACT X Activate interface Reserved 0 = Inactive 1 = Active Reset Register (Address: 0001111) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RES RES RES RES RES RES RES RES RES Default 0 0 0 0 0 0 0 0 0 RES Write 000000000 to this register triggers reset 3.2 Analog Interface 3.2.1 Line Inputs The TLV320AIC23 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs have independently programmable volume controls and mutes. Active and passive filters for the two channels prevent high frequencies from folding back into the audio band. The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage AVDD. To avoid distortions, it is important not to exceed the full-scale range. The gain is independently programmable on both left and right line-inputs. To reduce the number of software write cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3). The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise might be heard when reactivating the inputs. For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown in Figure 3-3. Where: R1 = 5 kΩ R2 = 5 kΩ C1 = 47 pF C2 = 470 nF R1 C2 CDIN + LINEIN R 2 C1 AGND Figure 3–3. Analog Line Input Circuit R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the AIC23 inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal. 3.2.2 Microphone Input MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It has a programmable volume control and a mute function. Active and passive filters prevent high frequencies from folding back into the audio band. 3–5 The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 = 50 k/(10 k + RMIC). For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software programmable gain of 0 dB or 20 dB (see Section 3.1.3). 50 kΩ 10 kΩ MICIN To ADC VMID 0 dB/20 dB Figure 3–4. Microphone Input Circuit The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is kept biased to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be heard when reactivating the input. The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. The maximum source current capability is 3 mA. This limits the smallest value of external biasing resistors that safely can be used. The MICBIAS output is not active in standby mode. 3.2.3 Line Outputs The TLV320AIC23 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads with 10-kΩ and 50-pF impedances. The DAC full-scale output voltage is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the analog supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band components. No further external filtering is required in most applications. The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources can be switched off independently. For example, in bypass mode, the line inputs are routed to the line outputs, bypassing the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both line outputs via a four-step programmable attenuation circuit. The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass and sidetone paths (see Section 3.1.3). 3.2.4 Headphone Output The TLV320AIC23 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω headphones. The headphone output includes a high-quality volume control and mute function. The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks. A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the volume-control values are updated only when the input signal to the gain stage is close to the analog ground level. This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated. The gain is independently programmable on the left and right channels. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3). 3–6 3.2.5 Analog Bypass Mode The TLV320AIC23 includes a bypass mode in which the analog line inputs are directly routed to the analog line outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control register[see Section 3.1.3). For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater than 1.0Vrms at AVDD=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AVDD. 3.2.6 Sidetone Insertion The TLV320AIC23 has a sidetone insertion made where the microphone input is routed to the line and headphone outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to –6 dB, –9 dB, –12 dB, or –1 dB, by software selection (see Section 3.1.3). If this mode is used to sum the microphone input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping and distortion. 3.3 Digital Audio Interface 3.3.1 Digital Audio-Interface Modes The TLV320AIC23 supports four audio-interface modes. • • • • Right justified Left justified I2S mode DSP mode The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified mode, which does not support 32 bits). The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode. 3.3.1.1 Right-Justified Mode In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT (see Figure 3-5). 1/fs LRCIN/ LRCOUT BCLK Left Channel DIN/ 0 n n–1 Right Channel 1 0 n n–1 1 0 DOUT MSB LSB Figure 3–5. Right-Justified Mode Timing 3.3.1.2 Left-Justified Mode In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT (see Figure 3-6) 3–7 1/fs LRCIN/ LRCOUT BCLK Left Channel DIN/ n n–1 1 Right Channel 0 n n–1 1 0 n DOUT MSB LSB Figure 3–6. Left-Justified Mode Timing 3.3.1.3 I2S Mode In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT (see Figure 3-7). 1/fs LRCIN/ LRCOUT BCLK 1BCLK DIN/ DOUT Left Channel n n–1 1 MSB Right Channel 0 n n–1 1 0 LSB Figure 3–7. I2S Mode Timing 3.3.1.4 DSP Mode The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected to the Frame Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The left-channel data consists of the first data word, which is immediately followed by the right channel data word (see Figure 3-8). Input word length is defined by the IWL register. Figure 3–8 shows LRP = 1 (default LRP = 0). LRCIN/ LRCOUT BCLK Left Channel DIN/ DOUT n MSB n–1 1 Right Channel 0 n n–1 LSB MSB Figure 3–8. DSP Mode Timing 3–8 1 0 LSB 3.3.2 Audio Sampling Rates The TLV320AIC23 can operate in master or slave clock mode. In the master mode, the TLV320AIC23 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB specification. The TLV320AIC23 can be used directly in a USB system. In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control the TLV320AIC23 clock and sampling rates. The settings in the sample rate control register control the clock mode and sampling rates. Sample Rate Control (Address: 0001000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 0 0 0 0 0 0 CLKOUT CLKIN SR[3:0] BOSR USB/Normal X Clock output divider 0 = MCLK 1 = MCLK/2 Clock input divider 0 = MCLK 1 = MCLK/2 Sampling rate control (see Sections 3.3.2.1 and 3.3.2.2) Base oversampling rate USB mode: 0 = 250 fs 1 = 272 fs Normal mode: 0 = 256 fs 1 = 384 fs Clock mode select: 0 = Normal 1 = USB Reserved The clock circuit of the AIC23 has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. The following sampling-rate tables are based on CLKIN = MCLK. 3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz) In the USB mode, the following ADC and DAC sampling rates are available: SAMPLING RATE† ADC (kHz) SAMPLING-RATE SAMPLING RATE CONTROL SETTINGS DAC (kHz) FILTER TYPE SR3 SR2 SR1 SR0 BOSR 96 96 3 0 1 1 1 0 88.2 88.2 2 1 1 1 1 1 48 48 0 0 0 0 0 0 44.1 44.1 1 1 0 0 0 1 32 32 0 0 1 1 0 0 8.021 8.021 1 1 0 1 1 1 8 8 0 0 0 1 1 0 48 8 0 0 0 0 1 0 44.1 8.021 1 1 0 0 1 1 8 48 0 0 0 1 0 0 8.021 44.1 1 1 0 1 0 1 † The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-kHz, and 88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figures 3–17 through 3–34 for filter responses 3–9 3.3.2.2 Normal-Mode Sampling Rates In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available: MCLK = 12.288 MHz SAMPLING RATE SAMPLING-RATE SAMPLING RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE SR3 SR2 SR1 SR0 BOSR 96 96 2 0 1 1 1 0 48 48 1 0 0 0 0 0 32 32 1 0 1 1 0 0 8 8 1 0 0 1 1 0 48 8 1 0 0 0 1 0 8 48 1 0 0 1 0 0 MCLK = 11.2896 MHz SAMPLING RATE SAMPLING-RATE SAMPLING RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE 88.2 88.2 44.1 44.1 8.021 44.1 8.021 SR3 SR2 SR1 SR0 BOSR 2 1 1 1 1 0 1 1 0 0 0 0 8.021 1 1 0 1 1 0 8.021 1 1 0 0 1 0 44.1 1 1 0 1 0 0 MCLK = 18.432 MHz SAMPLING RATE SAMPLING-RATE SAMPLING RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE 96 96 48 48 32 8 SR3 SR2 SR1 SR0 BOSR 2 0 1 1 1 1 1 0 0 0 0 1 32 1 0 1 1 0 1 8 1 0 0 1 1 1 48 8 1 0 0 0 1 1 8 48 1 0 0 1 0 1 MCLK = 16.9344 MHz SAMPLING RATE 3–10 SAMPLING-RATE SAMPLING RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE 88.2 88.2 44.1 44.1 8.021 44.1 8.021 SR3 SR2 SR1 SR0 BOSR 2 1 1 1 1 1 1 1 0 0 0 1 8.021 1 1 0 1 1 1 8.021 1 1 0 0 1 1 44.1 1 1 0 1 0 1 3.3.3 Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Characteristics ( TI DSP 250 fs Mode Operation ) Passband ±0.05 dB Stopband –6 dB 0.416 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple f > 0.584 fs –60 dB dB ADC Filter Characteristics ( TI DSP 272 fs and Normal Mode Operation ) Passband ±0.05 dB Stopband –6 dB 0.4535 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple dB f > 0.5465 fs –60 dB –3 dB, fs = 44.1 kHz fs = 48 kHz 3.7 Hz 4.0 Hz –0.5 dB, fs = 44.1 kHz –0.5 dB, fs = 48 kHz 10.4 Hz 11.3 Hz –0.1 dB 21.6 Hz 23.5 Hz ADC High-Pass Filter Characteristics –3 dB, Corner frequency fs = 44.1 kHz –0.1 dB, fs = 48 kHz DAC Filter Characteristics (48-kHz Sampling Rate) Passband ±0.03 dB Stopband –6 dB 0.416 fs Hz 0.5 fs ±0.03 Passband ripple Stopband attenuation Hz f > 0.584 fs –50 dB dB DAC Filter Characteristics (44.1-kHz Sampling Rate) Passband ±0.03 dB Stopband –6 dB 0.4535 fs Hz 0.5 fs ±0.03 Passband ripple Stopband attenuation Hz f > 0.5465 fs –50 dB dB 3–11 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response – dB –2 –4 –6 –8 –10 0 0.1 0.2 0.3 0.4 0.5 Normalized Audio Sampling Frequency Figure 3–9. Digital De-Emphasis Filter Response – 44.1 kHz Sampling FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response – dB –2 –4 –6 –8 –10 0 0.10 0.20 0.30 0.40 0.50 Normalized Audio Sampling Frequency Figure 3–10. Digital De-Emphasis Filter Response – 48 kHz Sampling 3–12 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3–11. ADC Digital Filter Response I: TI DSP and Normal Modes (Group Delay = 12 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3–12. ADC Digital Filter Ripple I: TI DSP and Normal Modes (Group Delay = 20 Output Samples) 3–13 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 1.5 2.5 2 3 Normalized Audio Sampling Frequency Figure 3–13. ADC Digital Filter Response II: TI DSP Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Normalized Audio Sampling Frequency Figure 3–14. ADC Digital Filter Ripple II: TI DSP Mode Only 3–14 0.5 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3–15. ADC Digital Filter Response III: TI DSP and Normal Modes (Group Delay = 3 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3–16. ADC Digital Filter Ripple III: TI DSP and Normal Modes 3–15 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3–17. ADC Digital Filter Response IV: TI DSP Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Normalized Audio Sampling Frequency Figure 3–18. ADC Digital Filter Ripple IV: TI DSP Mode Only 3–16 0.50 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 1.5 2 Normalized Audio Sampling Frequency 2.5 3 Figure 3–19. DAC Digital Filter Response I: TI DSP and Normal Modes FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3–20. DAC Digital Filter Ripple I: TI DSP and Normal Modes 3–17 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3–21. DAC Digital Filter Response II: TI DSP Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Normalized Audio Sampling Frequency Figure 3–22. DAC Digital Filter Ripple II: TI DSP Mode Only 3–18 0.5 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3–23. DAC Digital Filter Response III: TI DSP and Normal Modes FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3–24. DAC Digital Filter Ripple III: TI DSP and Normal Modes 3–19 FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 10 –10 –30 –50 –70 –90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3–25. DAC Digital Filter Response IV: TI DSP Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response – dB 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Normalized Audio Sampling Frequency Figure 3–26. DAC Digital Filter Ripple IV: TI DSP Mode Only 3–20 0.5 Appendix A Mechanical Data GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. ∅ 0,05 M 0,21 0,11 0,08 4200461/C 10/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments. A–1 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. A–2 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153