MICREL SY10E445JZTR

4-BIT SERIAL-to-PARALLEL
CONVERTER
Micrel, Inc.
FEATURES
SY10E445
SY100E445
SY10E445
SY100E445
DESCRIPTION
■ On-chip clock ÷4 and ÷8
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0,
the second to Q1, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Qn to Qn-1 by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Qn to the Qn-1 output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the VBB pin is tied
to the inverting differential input and bypassed via a 0.01µF
capacitor. The VBB provides the switching reference for the
input differential amplifier. The VBB can also be used to AC
couple an input signal.
■ Extended 100E VEE range of –4.2V to –5.5V
■ 2.5Gb/s data rate capability
■ Differential clock and serial inputs
■ VBB output for single-ended use
■ Asynchronous data synchronization
■ Mode select to expand to 8 bits
■ Internal 75kΩ input pull-down resistors
■ Fully compatible with Motorola MC10E/100E445
■ Available in 28-pin PLCC package
PIN NAMES
Pin
Function
SINA, SINA
Differential Serial Data Input A
SINB, SINB
Differential Serial Data Input B
SEL
Serial Input Select Pin
SOUT, SOUT
Differential Serial Data Output
Q0–Q3
Parallel Data Outputs
CLK, CLK
Differential Clock Inputs
CL/4, CL/4
Differential ÷4 Clock Output
CL/8, CL/8
Differential ÷8 Clock Output
MODE
Conversion Mode 4-bit/8-bit
SYNC
Conversion Synchronizing Input
RESET
Input, Resets the Counters
VCCO
VCC to Output
M9999-032206
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Rev.: F
1
Amendment: /0
Issue Date: March 2006
SY10E445
SY100E445
Micrel, Inc.
RESET
Ordering Information(1)
MODE
NC
VCCO
SINA
SINA
SYNC
PACKAGE/ORDERING INFORMATION
25 24 23 22 21 20 19
SINB
SINB
SEL
26
18
SOUT
27
17
VEE
CLK
CLK
1
2
SOUT
VCC
Q0
Q1
VBB
4
28
16
TOP VIEW
PLCC
J28-1
15
14
3
13
12
9
10 11
VCCO
Q3
8
CL/4
7
VCCO
CL/4
6
CL/8
CL/8
5
VCCO
Q2
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY10E445JC
J28-1
Commercial
SY10E445JC
Sn-Pb
SY10E445JCTR(2)
J28-1
Commercial
SY10E445JC
Sn-Pb
SY100E445JC
J28-1
Commercial
SY100E445JC
Sn-Pb
SY100E445JCTR(2)
J28-1
Commercial
SY100E445JC
Sn-Pb
SY10E445JZ(3)
J28-1
Commercial
SY10E445JZ with
Pb-Free bar-line indicator
Matte-Sn
SY10E445JZTR(2, 3)
J28-1
Commercial
SY10E445JZ with
Pb-Free bar-line indicator
Matte-Sn
SY100E445JZ(3)
J28-1
Commercial
SY100E445JZ with
Pb-Free bar-line indicator
Matte-Sn
SY100E445JZTR(2, 3)
J28-1
Commercial
SY100E445JZ with
Pb-Free bar-line indicator
Matte-Sn
28-Pin PLCC (J28-1)
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
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SY10E445
SY100E445
Micrel, Inc.
BLOCK DIAGRAM
SINB
SINB
SINA
SINA
0
1
D
D
Q
D
Q
Q3
D
Q
D
Q
Q2
D
Q
D
Q
Q1
D
Q
D
Q
SEL
Q0
SOUT
SOUT
CLK
CLK
CL/4
÷4
R
CL/4
0
1
÷2
CL/8
R
CL/8
MODE
RESET
SYNC
VBB
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SY10E445
SY100E445
Micrel, Inc.
TRUTH
TABLES
LOGIC DIAGRAM
Mode
Conversion
SEL
Serial Input
L
4-Bit
H
A
H
8-Bit
L
B
DC
CHARACTERISTICS
LOGIC
DIAGRAM
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
TA = +25°C
TA = +85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
IIH
Input HIGH Current
VOH
Output HIGH Voltage
(SOUT only) 10E
(SOUT only) 100E
–1020
–1025
—
—
–790 –980
–830 –1025
—
—
–760 –910
–830 –1025
—
—
–670
–830
Output Reference Voltage
10E
100E
–1.38
–1.38
—
—
–1.27 –1.35
–1.26 –1.38
—
—
–1.25 –1.31
–1.26 –1.38
—
—
–1.19
–1.26
—
—
154
154
154
177
185
212
VBB
IEE
V
1
1
V
Power Supply Current
mA
10E
100E
185
185
—
—
154
154
185
185
—
—
—
Note:
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E
and 100E VOH levels.
AC
CHARACTERISTICS
LOGIC
DIAGRAM
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
TA = +25°C
TA = +85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
2.0
2.5
—
—
—
—
2.0
2.5
—
—
—
—
2.0
2.5
—
—
—
—
Gb/s
NRZ
1
2
ps
—
ps
—
fMAX
Max. Conversion Frequency
tPD
Propagation Delay to Output
CLK to Q
CLK to SOUT
CLK to CL/4
CLK to CL/8
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
Set-up Time
SINA, SINB
SEL
–100
0
–250
–200
—
—
–100
0
–250
–200
—
—
–100
0
–250
–200
—
—
tH
Hold Time, SINA, SINB, SEL
450
300
—
450
300
—
450
300
—
ps
—
tRR
Reset Recovery Time
500
300
—
500
300
—
500
300
—
ps
—
tPW
Minimum Pulse Width
CLK, MR
400
—
—
400
—
—
400
—
—
ps
—
tr
tf
Rise/Fall Times
20% to 80%
SOUT
Other
ps
—
tS
100
200
225
425
350
650
100
200
Notes:
1. Guaranteed for input clock amplitudes of 150mV to 800mV.
2. Guaranteed for input clock amplitudes of 150mV to 400mV.
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225
425
350
650
100
200
225
425
350
550
SY10E445
SY100E445
Micrel, Inc.
LOGIC DIAGRAMINFORMATION
APPLICATIONS
Clock
Clock
The SY10/100E are integrated 1:4 serial-to-parallel
converters. The chips are designed to work with the
E446 devices to provide both transmission and receiving
of a high-speed serial data path. The E445, under special
input conditions, can convert up to a 2.5Gb/s NRZ data
stream into 4-bit parallel data. The device also provides
a divide-by-four clock output to be used to synchronize
the parallel data with the rest of the system.
The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction
with the E446. Figure 1 illustrates the loop test
architecture. The architecture allows for the electrical
testing of the link without requiring actual transmission
over the serial data path medium. The SINA serial input
of the E445 has an extra buffer delay and, thus, should
be used as the loop back serial input.
E445a
Serial Input
Data
SIN
SIN
E445b
SOUT
SOUT
SIN
SIN
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Output Data
100ps
Clock
Tpd CLK
to SOUT
Parallel
Data
Parallel
Data
SOUT
SOUT
800ps
To Serial
Medium
1050ps
Figure 2. Cascaded 1:8 Converter Architecture
clock-to-serial-out would potentially cause a serial bit to
be swallowed (Figure 3). With a minimum delay of 800ps
on this output, the clock for the lower order E445 cannot
be delayed more than 800ps relative to the clock of the
first E445 without potentially missing a bit of information.
Because the set-up time on the serial input pin is
negative, coincident excursions on the data and clock
inputs of the E445 will result in correct operation.
SINA
SINA
SINB
SINB
From Serial
Medium
Figure 1. Loop Test Architecture
Clock a
The E445 features a differential serial output and a
divide-by-8 clock output to facilitate the cascading of two
devices to build a 1:8 demultiplexer. Figure 2 illustrates
the architecture of a 1:8 demultiplexer using two E445s.
The timing diagram for this configuration can be found
on the following page. Notice the serial outputs (SOUT)
of the lower order converter feed the serial inputs of the
higher order device. This feedthrough of the serial inputs
bounds the upper end of the frequency of operation. The
clock-to-serial output propagation delay, plus the set-up
time of the serial input pins, must fit into a single clock
period for the cascade architecture to function properly.
Using the worst case values for these two parameters
from the data sheet, tPD CLK to SOUT = 1150ps or a
clock frequency of 950MHz.
The clock frequency is significantly lower than that of
a single converter. To increase this frequency, some
games can be played with the clock input of the higher
order E445. By delaying the clock feeding the second
E445 relative to the clock of the first E445, the frequency
of operation can be increased. The delay between the
two clocks can be increased until the minimum delay of
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Clock b
Tpd CLK
to SOUT
800ps
1050ps
Figure 3. Cascade Frequency Limitation
Perhaps the easiest way to delay the second clock
relative to the first is to take advantage of the differential
clock inputs of the E445. By connecting the clock for the
second E445 to the complimentary clock input pin, the
device will clock a half a clock period after the first E445
(Figure 4). Utilizing this simple technique will raise the
potential conversion frequency up to 1.5GHz. The divideby-eight clock of the second E445 should be used to
synchronize the parallel data to the rest of the system as
the parallel data of the two E445s will no longer be
synchronized. This skew problem between the outputs
can be worked around as the parallel information will be
static for eight more clock pulses.
5
SY10E445
SY100E445
Micrel, Inc.
TIMING
LOGIC DIAGRAM
DIAGRAMS
CLK
SIN
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
RESET
Q0
Dn–4
Dn
Q1
Dn–3
Dn+1
Q2
Dn–2
Dn+2
Q3
Dn–1
Dn+3
SOUT
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
CL/8
CL/4
Timing Diagram A. 1:4 Serial to Parallel Conversion
CLK
SIN
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
RESET
SYNC
Q0
Dn–4
Dn+1
Q1
Dn–3
Dn+2
Q2
Dn–2
Dn+3
Q3
Dn–1
Dn+4
SOUT
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
CL/4
CL/8
Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse
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Dn+2
Dn+3
Dn+4
SY10E445
SY100E445
Micrel, Inc.
667ps
(1.5GHz)
Clock
Clock
E445a
Serial Input
Data
SIN
SIN
Clock a
E445b
SOUT
SOUT
Clock b
SIN
SIN
Q3 Q2 Q1 Q0
100ps
Tpd CLK
to SOUT
Q3 Q2 Q1 Q0
800ps
1050ps
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Output Data
Figure 4. Extended Frequency 1:8 Demultiplexer
CLK
SINa
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Q0
Dn–4
Q1
Dn–3
Q2
Dn–2
Q3
Dn–1
Q4 (Q0 a)
Dn
Q5 (Q1 a)
Dn+1
Q6 (Q2 a)
Dn+2
Q7 (Q3 a)
Dn+3
SOUTa
Dn–4
Dn–3
SOUTb
CL/4a
CL/4b
CL/8a
CL/8b
Timing Diagram
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PRODUCT
CODE
7
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
Dn–4
Dn–3
Dn–2
Dn–1
Dn
Dn+1
SY10E445
SY100E445
Micrel, Inc.
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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