5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP Micrel, Inc. Precision Edge® SY10EL34/L Precision Edge® SY100EL34/L SY10EL34/L SY100EL34/L FEATURES ■ ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors Precision Edge® DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The V BB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. ■ Available in 16-pin SOIC package PIN NAMES Pin Function CLK Differential Clock Inputs EN Synchronous Enable MR Master Reset VBB Reference Output Q0 Differential ÷2 Outputs Q1 Differential ÷4 Outputs Q2 Differential ÷8 Outputs Precision Edge is a registered trademark of Micrel, Inc. M9999-031006 [email protected] or (408) 955-1690 Rev.: H 1 Amendment: /0 Issue Date: March 2006 Precision Edge® SY10EL34/L SY100EL34/L Micrel, Inc. PACKAGE/ORDERING INFORMATION Ordering Information(1) Q0 1 Q0 2 16 VCC Q ÷2 R 15 EN 14 NC Q D VCC 3 R Q1 4 13 Q Q1 5 R VCC 6 Q2 7 Q2 8 12 11 Q CLK ÷4 CLK VBB 10 MR 9 VEE ÷8 R 16-Pin Narrow SOIC (Z16-2) Package Type Operating Range SY10EL34LZC Z16-2 Commercial SY10EL34LZC Sn-Pb SY10EL34LZCTR(2) Z16-2 Commercial SY10EL34LZC Sn-Pb SY100EL34LZC Z16-2 Commercial SY100EL34LZC Sn-Pb SY100EL34LZCTR(2) Z16-2 Commercial SY100EL34LZC Sn-Pb SY10EL34LZI Z16-2 Industrial SY10EL34LZI Sn-Pb Part Number Package Marking SY10EL34LZITR(2) Z16-2 Industrial SY10EL34LZI Sn-Pb SY100EL34LZI Z16-2 Industrial SY100EL34LZI Sn-Pb SY100EL34LZITR(2) Z16-2 Industrial SY100EL34LZI Sn-Pb SY10EL34LZG(3) Z16-2 Industrial SY10EL34LZG with Pb-Free bar-line indicator Pb-Free NiPdAu SY10EL34LZGTR(2, 3) Z16-2 Industrial SY10EL34LZG with Pb-Free bar-line indicator Pb-Free NiPdAu SY100EL34LZG(3) Z16-2 Industrial SY100EL34LZG with Pb-Free bar-line indicator Pb-Free NiPdAu SY100EL34LZGTR(2, 3) Z16-2 Industrial SY100EL34LZG with Pb-Free bar-line indicator Pb-Free NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. M9999-031006 [email protected] or (408) 955-1690 Lead Finish 2 Precision Edge® SY10EL34/L SY100EL34/L Micrel, Inc. TRUTH TABLE CLK EN MR Z L L Divide Function ZZ H L Hold Q0–2 X X H Reset Q0–2 NOTE: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter 10EL 100EL TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — — — — 49 49 — — — — 49 49 — — — — 49 49 — — — — 49 54 mA — — –1.19 –1.26 V — 150 µA IEE Power Supply Current VBB Output Reference 10EL –1.43 Voltage 100EL –1.38 — — IIH Input High Current — NOTE: 1. Parametric values specified at: TA = 0°C — –1.30 –1.38 –1.26 –1.38 150 5 volt Power Supply Range 3 volt Power Supply Range — — — –1.27 –1.35 –1.26 –1.38 — 150 100EL34 Series: 10EL34 Series 10/100EL34L Series: — — — — –1.25 –1.31 –1.26 –1.38 150 — -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol tPD TA = 0°C TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Propagation Delay to Output CLK MR 960 650 1100 800 1200 1010 960 650 1100 800 1200 1010 960 650 1100 800 1200 1010 960 650 1100 1200 800 1010 — — 50 — — 50 — — 50 — — 50 ps ps tskew Within-Device Skew(2) tS Set-up Time EN 400 — — 400 — — 400 — — 400 — — ps tH Hold Time EN 200 — — 200 — — 200 — — 200 — — ps Minimum Input Swing(3) 250 — — 250 — — 250 — — 250 — — mV VCMR Common Mode Range(4) –1.3 — –0.4 –1.4 — –0.4 –1.4 — –0.4 –1.4 — –0.4 V tr tf Output Rise/Fall Times Q (20% – 80%) 275 400 525 275 400 525 275 400 525 275 400 525 ps VPP NOTES: 1. Parametric values specified at: 5 volt Power Supply Range 100EL34 Series: 10EL34 Series 10/100EL34L Series: -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. 3 volt Power Supply Range 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I. M9999-031006 [email protected] or (408) 955-1690 3 Precision Edge® SY10EL34/L SY100EL34/L Micrel, Inc. TIMING DIAGRAM Internal Clock Disabled Internal Clock Enabled CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. M9999-031006 [email protected] or (408) 955-1690 4 Precision Edge® SY10EL34/L SY100EL34/L Micrel, Inc. 16-PIN SOIC .150" WIDE (Z16-2) Rev. 02 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-031006 [email protected] or (408) 955-1690 5