Micrel, Inc. SY100S351 HEX D FLIP-FLOP FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S351 DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 50% faster than Fairchild 300K Better than 20% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75KΩ pull-down resistors. BLOCK DIAGRAM D5 CPb CPa MR D4 D Q Q5 Q Q5 Q Q4 Q Q4 Q Q3 Q Q3 Q Q2 Q Q2 Q Q1 Q Q1 D Q Q0 E R Q Q0 E D E D3 M9999-032406 [email protected] or (408) 955-1690 R D E D0 R D E D1 R D E D2 R R Rev.: H 1 Amendment: /0 Issue Date: March 2006 SY100S351 Micrel, Inc. Q0 Ordering Information Q1 Q1 D0 Q0 VEES D1 PACKAGE/ORDERING INFORMATION D2 D3 VEE VEES 12 13 4 3 14 15 2 1 CPa 16 17 CPb 18 MR Top View PLCC J28-1 28 27 26 Q2 Q2 VCCA VCC VCC Q3 Commercial SY100S351FC Sn-Pb F24-1 Commercial SY100S351FC Sn-Pb SY100S351JC J28-1 Commercial SY100S351JC Sn-Pb J28-1 Commercial SY100S351JC Sn-Pb J28-1 Commercial SY100S351JZ with Pb-Free bar-line indicator Matte-Sn J28-1 Commercial SY100S351JZ with Pb-Free bar-line indicator Matte-Sn SY100S351JCTR SY100S351JZ (1) (2) D2 D3 D1 D5 Q5 Q5 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q2 Q2 Top View Flatpack F24-1 Q3 VCC VCCA F24-1 SY100S351FCTR(1) Q4 Q5 Q4 VEES D4 D5 Q5 CPa MR VEE CPb 24 23 22 21 20 19 18 Q3 SY100S351FC 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. 1 6 Lead Finish Notes: D4 Q4 Package Marking SY100S351JZTR(1, 2) 28-Pin PLCC (J28-1) 4 5 Operating Range Q3 19 20 21 22 23 24 25 Q4 Package Type Part Number 11 10 9 8 7 6 5 24-Pin Cerpack (F24-1) M9999-032406 [email protected] or (408) 955-1690 2 SY100S351 Micrel, Inc. PIN NAMES Pin Function D0 — D5 Data Inputs CPa, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q0 — Q5 Data Outputs Q0 — Q5 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs TRUTH TABLES Synchronous Operation(1) Asynchronous Operation(1) Inputs Inputs Outputs Outputs Dn CPa CPb MR Qn (t+1) Dn CPa CPb MR Qn (t+1) X X X H L L u L L L H u L L H L L u L L H L u L H X H u L Qn(t) X u H L Qn(t) X L L L Qn(t) Unit NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care t = Time before CP Positive Transition t+1 = Time after CP Positive Transition u = LOW-to-HIGH Transition DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current MR D0 – D5 CPa, CPb Power Supply Current M9999-032406 [email protected] or (408) 955-1690 Min. Typ. Max. — — — — — — 270 200 300 –98 –71 –49 3 Condition µA VIN = VIH (Max.) mA Inputs Open SY100S351 Micrel, Inc. AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fMAX Toggle Frequency 700 — 700 — 700 — MHz tPLH tPHL Propagation Delay CPa, CPb to Output — 1200 — 1200 — 1200 ps tPLH tPHL Propagation Delay MR to Output — 1200 — 1200 — 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time D0–D5 MR (Release Time) 500 1000 — — 500 1000 — — 500 1000 — — tH Hold Time, D0–D5 550 — 550 — 550 — ps tPW (H) Pulse Width HIGH CPa, CPb, MR 1000 — 1000 — 1000 — ps Condition ps PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fMAX Toggle Frequency 700 — 700 — 700 — MHz tPLH tPHL Propagation Delay CPa, CPb to Output — 1200 — 1200 — 1200 ps tPLH tPHL Propagation Delay MR to Output — 1200 — 1200 — 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time D0–D5 MR (Release Time) 500 1000 — — 500 1000 — — 500 1000 — — tH Hold Time, D0–D5 550 — 550 — 550 — ps tPW (H) Pulse Width HIGH CPa, CPb, MR 1000 — 1000 — 1000 — ps M9999-032406 [email protected] or (408) 955-1690 ps 4 Condition SY100S351 Micrel, Inc. TIMING DIAGRAMS DATA 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V 1/fmax tPHL tpw (H) tPLH OUTPUT 50% tPHL tPLH OUTPUT tTLH tTHL Propagation Delay (Clock) and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% MR –1.69V tS (RELEASE TIME) tpw (H) CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Resets) M9999-032406 [email protected] or (408) 955-1690 5 SY100S351 Micrel, Inc. TIMING DIAGRAMS –0.95V DATA 50% –1.69V tH tS –0.95V CLOCK 50% –1.69V Data Set-up and Hold Time Notes: 1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-032406 [email protected] or (408) 955-1690 6 SY100S351 Micrel, Inc. 24-PIN CERPACK (F24-1) Rev. 03 M9999-032406 [email protected] or (408) 955-1690 7 SY100S351 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-032406 [email protected] or (408) 955-1690 8