MICREL SY87724L_06

3.3V AnyRate® MUX/DEMUX
Up to 2.7GHz
Micrel, Inc.
FEATURES
SY87724L
SY87724L
DESCRIPTION
■ Protocol transparent MUX/DEMUX operation up to
2.7GHz
■ Programmable to 4, 5, 8, or 10 bit parallel interfaces
■ Differential clock and serial inputs/outputs
■ Easily controlled by framer logic
■ Synchronous frame boundary indication
■ HSPC (High Speed PECL Compatible) inputs and
outputs
■ 3.3V power supply
■ Available in 80-pin LQFP-PQ2 package
The SY87724L is a complete serial data multiplexer and
demultiplexer, capable of operating at up to 2.7GHz. The
device provides for muxing and demuxing to 4, 5, 8, or 10
bit wide buses.
The SY87724L can accept a synchronous code group or
octet boundary input, and uses this input for parallel data
alignment.
The SY87724L is manufactured in Micrel’s high
performance ASSET2™ silicon bipolar process.
Micrel provides a complete protocol transparent solution
with the AnyRate® SY87721L CDR/CMU SY87729L, and
the SY87724L integrated MUX/DEMUX.
APPLICATIONS
■
■
■
■
■
■
OC-3, OC-12, OC-48, ATM, InfiniBand
Gigabit Ethernet
Fibre Channel, 2X Fibre Channel
SMPTE-259 and 292
Proprietary optical transport
ITU G. 975 Solutions
SYSTEM BLOCK DIAGRAM
SY889x3
SY87721L
SY87724L
RDATA
FIBER
AnyRate™
PIN DIODE
TIA
POST AMP
4, 5, 8, 10 bits
RCLK
DEMUX
CDR
LOCK
TCLK
One
REF_XTAL
SY87729L
MUX
4, 5, 8, 10 bits
CMU
REF_CLK
AnyClock™
Fractional
Synthesizer
SEL CD
SY889x2
FIBER
LASER
DIODE
LASER
DIODE
DRIVER
AnyRate is a registered trademark of Micrel, Inc.
M9999-031506
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Rev.: D
1
Amendment: /0
Issue Date: March 2006
Micrel, Inc.
SY87724L
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY87724LHI
H80-1
Industrial
SY87724LHI
Sn-Pb
SY87724LHY(2)
H80-1
Industrial
SY87724LHY with
Pb-Free bar line indicator
Matte Tin
Pb-Free
DPOUTCK–
DP0+
DP0–
DPOUTCK+
GND
VCCO
MPF4+
MPF4–
VCC
MPF2+
MPF2–
MPF3+
MPF3–
MPF0+
MPF0–
MPF1+
MPF1–
GND
MTXCLK+
MTXCLK–
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Pb-Free package is recommended for new designs.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
GND
1
60
VCC
NC
NC
NC
2
59
3
58
DP1–
4
57
5
56
SIZ0
6
55
DP2+
DP2–
VCCO
SIZ1
SIZ2
MP0
7
54
8
53
MP1
MP2
10
9
11
DP3–
DP4+
50
DP4–
MP3
MP4
12
49
13
48
DP5
DP6
MP5
MP6
14
47
DP7
15
46
MP7
MP8
16
45
17
44
DP8
DP9
VCCO
MP9
18
43
VCC
VCCO
19
42
20
41
80-Pin EPAD TQFP (H80-1)
2
GND
VCC
VCC
GND
DSIN+
DSIN–
DFMIN–
VCCO
DFMIN+
MPINCK–
NC
NC
MPINCK+
VCC
LPBK
GND
MSOUT+
MSOUT–
NC
NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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VCCO
DP3+
51
52
80-PIN
LQFP-PQ2
VCC
DP1+
DCKIN–
DCKIN+
VCCO
Micrel, Inc.
SY87724L
FUNCTIONAL BLOCK DIAGRAM
DEMUX
DSIN±
Mux
MSOUT±
(From Mux)
Serial In
Parallel Out
Shift
Register
(5 bits)
5
Parallel In
Parallel Out
Register
(5 bits)
DCKIN±
Mux
MTKCLK±
(From Mux)
Primary Divider
(÷4 or ÷5)
DFMIN±
Mux
MSYNOUT±
(From Mux)
Demux
Strobe Generator
SIZ0
SIZ1
SIZ2
Demux
Internal Control
LPBK
5
Parallel In
Parallel Out
Register
(5 bits)
5
Parallel In
Parallel Out
Register
(5 bits)
5
Parallel In
Parallel Out
Register
(5 bits)
5
Parallel In
Parallel Out
Register
(5 bits)
5
Delay
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DP0–4±
DP5–9
DPOUTCK±
Micrel, Inc.
SY87724L
FUNCTIONAL BLOCK DIAGRAM
MUX
MTXCLK±
MP0–4±
MP0–4
5
Parallel In
Parallel Out
5
MPF0–4±
5
Parallel In
Parallel Out
Register
(5 bits)
Parallel In
Parallel Out
Register
(5 bits)
Mux
MP5–9
5
5
Parallel In
Parallel Out
Register
(5 bits)
Serial and
Parallel In
Serial Out
Shift
Register
(5 bits)
MSOUT±
SIZ0
MPINCK±
SIZ1
SIZ2
Mux Strobe
Generator
Load/Shift
MSYNOUT±
(to Demux)
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SY87724L
PIN NAMES
DP0± through DP4± – Differential PECL Output
These signals may be used as either differential, or singleended. When converting to 4 or 5 bits, speed issues may
encourage the use of these signals differentially. When
converting to wider than 5 bits, these signals are to be used
single-ended. Please refer to the applications section for
further details.
COMMON
LPBK – TTL Input
This pin defines whether a device exhibits local loopback
or not, as per the following table. Loopback internally
connects mux serial out to demux serial in, thus the user
may expect mux side parallel data to appear on the demux
parallel output pins.
LPBK
Functioning
0
Loopback
1
Normal
DP5 through DP9 – PECL Output
These are the rest of the parallel output bits, to be used
when converting to wider than 5 bits. Which bits are valid
depends on the values of SIZ0, SIZ1, and SIZ2. Please
refer to the table in the applications section for further details.
DPOUTCK± – Differential HSPC Output
This signal is used to strobe the DP0-9 data. It is used
differentially when converting to 4 or 5 bits, and is used
single-ended when converting to wider than 5 bits. The
clock rate of the line will be determined by the DCKIN
signal, and by the setting of the SIZ bits. This output always
provides valid differential logic levels.
SIZ0, SIZ1, SIZ2 – TTL Input
These three signals determine the width of the parallel
output, as well as the width of parallel input. The following
table describes the parallel width options.
Width
SIZ0
SIZ1
SIZ2(1)
4
5
8
10
Undefined
0
1
0
1
X
0
0
1
1
X
0
0
0
0
1
MUX
MP0-9 – PECL Input
These bits accept data for muxing wider than 5 bits.
MPINCK+, used single-ended, determines when this data
may change. Please refer to the table in the description for
which pins represent what bits for various widths.
Note:
1. Pin 8 (SIZ2) should always be tied to a TTL logic level LOW.
MPF0–4± – Differential PECL Input
These signals are used when muxing 4 or 5 bits of parallel
data. MPINCK± determines when this data may change.
Please refer to the Mux table in the description for which
pins represent what bits for various widths.
DEMUX
DSIN± – Differential HSPC Input
This is the serial input to the SY87724L demux. It accepts
the serial data and converts it to parallel data. It is ignored
during loopback.
MTXCLK± – Differential HSPC Input
This is the serial rate clock input to the mux. It determines
the rate at which serial data will be shifted out of the mux.
DCKIN± – Differential HSPC Input
This is the bit rate clock that feeds serial data into the
demux shift register. This signal also feeds the demux strobe
generator and primary divider, except during loopback.
MSOUT± – Differential PECL Output
This signal is the serialized data output.
MPINCK± – Differential PECL Output
This signal indicates when the next set of parallel bits
may be presented to the SY87724L for muxing. For muxing
wider than 5 bits, MPINCK+ is used single-ended. These
signals always provide valid differential clock signals
regardless of single-ended or differential data mode.
DFMIN± – Differential HSPC Input
This is the frame alignment input signal. This signal resets
the primary divider, as well as the strobe generator. This
effectively sets the alignment for the parallel data being
demuxed. Usually, DFMIN± asserts one DCKIN± before a
parallel word boundary, and continues to assert one clock
before every boundary. However, DFMIN± need only occur
once for proper operation. Should DFMIN± assert at other
than a previously set boundary, the DPOUTCK± signal will
always occur later than would be expected. That is, there
will never be a short DPOUTCK± pulse.
OTHER
VCC
VCCO
GND
NC
Supply Voltage
Output Supply Voltage
Ground
These pins are reserved and are to be left
unconnected.
Note:
1. All differential outputs always provide valid differential logic levels regardless
of differential or single-ended use.
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Micrel, Inc.
SY87724L
DESCRIPTION
General
The SY87724L MDM is designed to perform muxing and
demuxing at up to 2.7GHz speeds. The device can
simultaneously mux and demux up to 10 bits of full duplex
data. In addition, a full parallel-to-parallel loopback function
is implemented, such that parallel data out will loop back to
parallel data in, with the device internally connecting the
serial output to the serial input.
Narrow Demux
In this example, serial data is converted into 4 or 5 bit
wide data. Because this can result in very high data rates
on the parallel outputs, they are differential. The DFMIN±
input indicates, synchronously with DCKIN±, and one clock
ahead, the start of a 4 or 5 bit boundary.
DP0-4+
DCKIN±
MDM
DFMIN±
DPOUTCK+
Figure 2. Wide Demux
As in the narrow case, DPOUTCK± will never assert
twice in 8 or 10 DCKIN± cycles. Should a DFMIN± assertion
change the MDM’s 8 or 10 bit boundary, DPOUTCK±
assertion will be delayed and there will never be a short
assertion.
For 8 bit output, DP4± and DP9 are not used.
The following table summarizes the available bit widths.
The right column shows the parallel bits, in sequence from
first in serially, to last in.
DP0-4±
DSIN±
DCKIN±
DP5-9
DSIN±
MDM
DFMIN±
DPOUTCK±
Width
Figure 1. Narrow Demux
Every DFMIN± assertion will trigger a new 4 or 5 bit
boundary. Should only one DFMIN± assertion occur, then
DPOUTCK± will continue to assert every 4 or 5 DCKIN±
clocks. Should a subsequent DFMIN± assertion reset the 4
or 5 bit boundary, then DPOUTCK± will always result in a
longer assertion, not a shorter one.
For example, if a subsequent DFMIN± resets a 5 bit
boundary after the second bit in relation to a previous
boundary, then the next DPOUTCK± will always occur 7
DCKIN± later, never 2 DCKIN± later. For four bit output,
DP5± are not used.
Sequence
4
DP0±, DP1±, DP2±, DP3±
5
DP0±, DP1±, DP2±, DP3±, DP4±
8
DP0+, DP1+, DP2+, DP3+, DP5, DP6, DP7, DP8
10
DP0+, DP1+, DP2+, DP3+, DP4+, DP5, DP6, DP7,
DP8, DP9
Narrow Mux
In this scenario, 4 or 5 bit wide parallel data is converted
to a serial bit stream. Because this can result in very high
data rates on the parallel inputs, they are differential. In this
mode of operation, there is no external synchronization,
and the MPINCK± signal pair has arbitrary phase with
respect to the MTXCLK± clock, which clocks the mux output
shift register.
Wide Demux
The more typical case will be to convert the serial data
stream into 8 or 10 bit wide data. Because the worst case
parallel transfer rate is on the order of 250 to 340 Megatransfers per second, single ended parallel output is
preferred. Thus, only the single-ended side of the differential
outputs is used.
This example is much like the narrow demux, except
now DFMIN± indicates 8 or 10 bit boundaries.
MSOUT±
MTXCLK±
MPF0-4±
MDM
MPINCK±
Figure 4. Narrow Mux
MPINCK± indicates when MDM is ready to accept more
data. It is derived from MTXCLK±, with an arbitrary phase
relationship.
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Micrel, Inc.
SY87724L
Wide Mux
The more typical case will be to convert 8 or 10 bit wide
parallel data words into a serial bit stream. Because the
worst case parallel input rate is on the order of 250 to 340
Mega-transfers per second, single ended parallel inputs are
used.
This scenario is much like the narrow mux case, except
now MPINCK+ clocks slower, for 8 or 10 bit parallel words.
MSOUT±
MTXCLK±
MP0-9
Loopback
To ease system design, the SY87724L MDM has the
capability to loop parallel data in, through the mux, into the
demux, and back to parallel data out. This permits system
check-out through to the individual MDM device. Note that,
for a full check-out, some form of loopback further down the
serial stream is required.
Loopback is incorporated into MDM by modifying the
serial clock, data, and sync inputs to the demux stage.
During loopback, the source of serial information for the
demux is changed. The MSOUT±, MTXCLK± and
MSYNOUT± are internally muxed to the DSIN±, DCKIN±,
and DFMIN± nodes of the demux section. The MSYNOUT±
signal has the same characteristics as the DFMIN logic
expects.
This exercises the internal data path, both mux and
demux, for MDM, and also the control logic. The parallel
data presented to the parallel inputs will appear, some small
but unspecified time later, at the parallel outputs.
MDM
MPINCK+
Figure 5. Wide Mux
Note that the input data indication is now single ended,
and that completely different input pins are used, as
compared to the 4 or 5 bit case.
The following table summarizes the available bit widths.
The right column shows the parallel input bits, such as they
will appear in the serial output stream.
Width
MP*
DP*
MSOUT±
DSIN±
DCKIN±
DFMIN±
Sequence
4
MPF0±, MPF1±, MPF2±, MPF3±
5
MPF0±, MPF1±, MPF2±, MPF3±, MPF4±
8
MP5, MP6, MP7, MP8, MP0, MP1, MP2, MP3
10
MP5, MP6, MP7, MP8, MP9, MP0, MP1, MP2, MP3,
MP4
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* Number of wires depends on the SIZX bits.
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Micrel, Inc.
SY87724L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Power Supply Voltage
VI
Input Voltage
IOUT
ECL Output Current
Tstore
TA
Rating
Unit
–0.5 to +3.8
V
–0.5 to
—Continuous
—Surge
VCC(2)
V
50
100
mA
Storage Temperature Range
–65 to +150
°C
Operating Temperature Range
–40 to +85
°C
NOTES:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. The maximum value is specified at VCC up to VCC = +6V.
DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCA = 3.15V to 3.45V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Power Supply Voltage
3.15
3.3
3.45
V
ICC
Power Supply Current
—
650
750
mA
Condition
NOTE:
1. Operating temperature range from –40°C to +85°C.
HSPC DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCA = 3.15V to 3.45V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
VIH
Input HIGH Voltage
VCC – 1.165
—
VCC – 0.880
V
VIL
Input LOWVoltage
VCC – 1.810
—
VCC – 1.475
V
IIL
Input LOW Current
–0.5
—
—
µA
VIN = VIL(Min)
VOH
Output HIGH Voltage
VCC – 1.0
—
VCC – 0.75
V
50Ω to VCC –2V
VOL
Output LOW Voltage
VCC – 1.55
—
VCC – 1.25
V
50Ω to VCC –2V
VOSW
Output Voltage
Differential Swing
0.3
—
—
V
NOTE:
1. Operating temperature range from –40°C to +85°C.
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SY87724L
PECL DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCA = 3.15V to 3.45V
Symbol
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage
Parameter
VCC – 1.165
—
VCC – 0.880
V
Condition
VIL
Input LOW Voltage
VCC – 1.810
—
VCC – 1.475
V
IIL
Input LOW Current
–0.5
—
—
µA
VIN = VIL(Min)
VOH
Output HIGH Voltage
VCC – 1.075
—
VCC – 0.830
V
50Ω to VCC –2V
VOL
Output LOW Voltage
VCC – 1.860
—
VCC – 1.570
V
50Ω to VCC –2V
VOSW
Output Voltage
Differential Swing
0.6
—
—
V
NOTE:
1. Operating temperature range from –40°C to +85°C.
TTL DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCA = 3.15V to 3.45V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
VIH
Input HIGH Voltage
2.0
—
—
V
VIL
Input LOW Voltage
—
—
0.8
V
IIH
Input HIGH Current
—
—
—
—
+20
+100
µA
µA
VIN = 2.7V, VCC = Max.
VIN = VCC, VCC = Max.
IIL
Input LOW Current
—
—
300
µA
VIN = 0.5V, VCC = Max.
NOTE:
1. Operating temperature range from –40°C to +85°C.
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SY87724L
AC ELECTRICAL CHARACTERISTICS
VCC = VCCA = 3.15V to 3.45V
Symbol
Parameter
Min.
Typ.
Max.
Unit
fMAX
tDCKPWH,
tDCKPWH
Maximum Operating Frequency
2.7
—
—
GHz
Demux Clock Pulse Duty Cycle
45
—
55
%
tDSDS
Demux Serial Data Setup
200
—
—
ps
tDSDH
Demux Serial Data Hold
0
—
—
ps
tDSFS
Demux Serial Frame Setup
150
—
—
ps
tDSFH
Demux Serial Frame Hold
50
—
—
ps
tDPDP
Demux Parallel
Differential Propagation
+200
—
+800
ps
tDPSP
Demux Parallel
Single-Ended Propagation
+200
—
+1200
ps
tMCKPWH,
tMCKPWL
Mux Clock Pulse Duty Cycle
45
—
55
%
tMPDS
Mux Parallel Differential Setup(2)
Tcyc+650
—
—
ps
tMPDH
Mux Parallel Differential Hold(2)
–(Tcyc+250)
—
—
ps
tMPSS
Mux Parallel Single-Ended Setup(2)
Tcyc+850
—
—
ps
–(Tcyc+50)
—
—
ps
—
—
100
—
120
500
ps
Hold(2)
tMPSH
Mux Parallel Single-Ended
tr, tf
Output Rise/Fall Times
MCKOUT, MSOUT, MSYNOUT
All Others
NOTES:
1. Operating temperature range from –40°C to +85°C.
2. Tcyc = the period of the clock being fed into MTXCLK.
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Condition
50Ω to VCC – 2V
(20% to 80%)
Micrel, Inc.
SY87724L
TIMING WAVEFORMS
tDSDS
tDSDH
Valid
DSIN±
tDSFS
tDSFH
DCKIN±
Valid
DFMIN±
tDPDP
DPOUTCK±
DP0–4±
tDPSP
DPOUTCK+
DP0–4+
DP5–9
tMPDS
tMPDH
Valid
MPF0–4±
MPINCK±
tMPSS
tMPSH
Valid
MP0–9
MPINCK+
tDCKPWH
tDCKPWL
DCKIN±
tMCKPWL
tMCKPWH
MTXCLK±
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SY87724L
TIMING APPLICATION EXAMPLE
Valid
MPF0-4±
1750
1350
MPINCK±
y
x
MTXCLK±
Valid
MPF0-9±
1950
1150
MPINCK±
y
x
MTXCLK±
NOTES:
1. MTXCLK = 1Gbps
2. Time “x” is approximately equal to time “y.”
3. Setup and hold for MPF0-4± is conditioned on the MTXCLK± rising edge
just prior to the MTXCLK± rising edge that causes an MPINCK± rising
edge.
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Micrel, Inc.
SY87724L
80-PIN LQFP-PQ2 (DIE UP) (H80-1)
+0.05
–0.05
+0.002
–0.002
+0.5
–0.5
+0.020
–0.020
+0.15
–0.15
+0.006
–0.006
+0.5
–0.5
+0.020
–0.020
+0.06
–0.10
+0.002
–0.004
Package
Rev. 00
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
VEE
Heavy Copper Plane
PCB Thermal Consideration for 80-Pin EPAD-TQFP Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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