MICREL SY89465UMG

SY89465U
Precision LVDS 1:10 Fanout with 2:1 Runt
Pulse Eliminator MUX and Internal Termination
General Description
The SY89465U is a low jitter, 1:10 LVDS fanout
buffer with a 2:1 differential input multiplexer (MUX)
optimized for redundant source switchover
applications. Unlike standard multiplexers, the
SY89465Us 2:1 Runt Pulse Eliminator (RPE) MUX
prevents any short cycles or “runt” pulses during
switchover. In addition, a unique Fail-Safe Input
(FSI) protection prevents metastable conditions
when the selected input clock fails to a DC voltage
(voltage between the pins of the differential input
drops below 100mV).
The differential input includes Micrel’s, 3-pin internal
termination architecture that allows customers to
interface to any differential signal (AC- or DCcoupled) as small as 100mV (200mVPP) without any
level shifting or termination resistor networks in the
signal path. The outputs are LVDS-compatible with
fast rise/fall times guaranteed to be less than 220ps.
The SY89465U operates from a 2.5V ±5% supply
and is guaranteed over the full industrial
temperature range of –40°C to +85°C. The
SY89465U is part of Micrel’s high-speed, Precision
®
Edge product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
®
Precision Edge
Features
• Selects between two sources, and provides 10
precision LVDS copies
• Guaranteed AC performance over temperature and
supply voltage:
– Wide operating frequency: 1kHz to >1.5GHz
– < 1200ps In-to-Out tpd
– < 220ps tr/tf
• Unique, patent-pending input isolation design
minimizes adjacent channel crosstalk
• Fail-Safe Input prevents oscillations
• Ultra-low jitter design:
– <1psRMS random jitter
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
• Unique patented input termination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
• 325mV LVDS output swing
• 2.5V ±5% supply voltage
• -40°C to +85°C industrial temperature range
• Output enable
• Available in 44-pin (7mm x 7mm) MLF™ package
Applications
• Redundant clock switchover
• Fail-safe clock protection
Markets
•
•
•
•
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
December 2005
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SY89465U
Typical Application
Simplified Example Illustrating Runt Pulse Eliminator
(RPE) when Primary Clock Fails
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Ordering Information(1)
Part Number
Package
Type
Operating
Range
SY89465UMG
MLF-44
MLF-44
SY89465UMGTR
(2)
Package Marking
Lead
Finish
Industrial
SY89465U with
Pb-Free bar-line Indicator
NiPdAu
Pb-Free
Industrial
SY89465U with
Pb-Free bar-line Indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
44-Pin MLF™ (MLF-44)
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Pin Description
Pin Number
Pin Name
Pin Function
2, 5
7, 10
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each
pin of a pair internally terminates to a VT pin through 50Ω. Please refer to the “Input
Interface Applications” section for more details.
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC –1.2V. They are used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01µF low ESR capacitor to VCC. Due to the limited drive capability, the VREF-AC pin
is only intended to drive its respective VT pin. Maximum sink/source current is
±1.5mA. Please refer to the “Input Interface Applications” section for more details.
3, 8
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a
VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for
maximum interface flexibility. Please refer to the “Input Interface Applications” section
for more details.
13, 15, 22, 23
28, 33, 34, 41,
43, 44
VCC
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to
the VCC pins as possible.
39, 40
37, 38
35, 36
31, 32
29, 30
26, 27
24, 25
20, 21
18, 19
16, 17
/Q0, Q0
/Q1, Q1
/Q2, Q2
/Q3, Q3
/Q4, Q4
/Q5, Q5
/Q6, Q6
/Q7, Q7
/Q8, Q8
/Q9, Q9
Differential Outputs: These differential LVDS outputs are a logic function of the IN0,
IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
42
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state if left open. VTH = VCC/2.
1, 11, 6
GND,
Exposed Pad
4, 9
12
14
Ground: Ground and exposed pad must be connected to the same ground plane.
CAP
Power-On Reset (POR) initialization capacitor. When using the multiplexer with RPE
capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal
RPE logic starts up in a known state. See “Power-On Reset (POR) Description”
section for more details regarding capacitor selection. If this pin is tied directly to VCC,
the RPE function will be disabled and the multiplexer will function as a normal
multiplexer. The CAP pin should never be left open or tied directly to GND.
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9 outputs.
It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH
state if left open. When disabled, CLK output goes LOW and /CLK goes HIGH. EN
being synchronous, outputs will be enabled/disabled when they are in LOW state.
Thus, a runt pulse is avoided if the device is enabled/disabled by an asynchronous
control. VTH = VCC/2.
Truth Table
Inputs
December 2005
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................ –0.5V to +4.0V
Input Voltage (VIN) ....................................–0.5V to VCC
Input Current (IIN) ...........................................................
Source/Sink Current on IN, /IN................... ±50mA
Source/Sink Current on VT ....................... ±100mA
VREF-AC Current
Source/Sink Current on VREF-AC .................... ±2mA
Lead Temperature (soldering, 20 sec.)............ +260°C
Storage Temperature (Ts) ...................–65°C to 150°C
Supply Voltage (VCC) ....................+2.375V to +2.625V
Ambient Temperature (TA) .................. –40°C to +85°C
(3)
Package Thermal Resistance
MLF™ (θ JA)
Still-Air ..................................................... 24.4°C/W
MLF™ (ψ JB)
Junction-to-Board ..................................... 8.1°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
VCC
Power Supply
ICC
Power Supply Current
RIN
Input Resistance
(IN-to-VT)
RDIFF_IN
Condition
Min
Typ
Max
Units
2.375
2.5
2.625
V
250
325
mA
45
50
55
Ω
Differential Input Resistance
(IN-to-/IN)
90
100
110
Ω
VIH
Input High Voltage
(IN, /IN)
1.2
VCC
V
VIL
Input Low Voltage
(IN, /IN)
0
VIH–0.1
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 1a. Note 5.
0.1
2.5
V
VDIFF_IN
Differential Input Voltage Swing
|IN-/IN|
See Figure 1b.
0.2
VIN_FSI
Input Voltage Threshold that
Triggers FSI
VT_IN
IN-to-VT
(IN, /IN)
VREF-AC
Output Reference Voltage
No load, max VCC
V
30
VCC–1.3
VCC–1.2
100
mV
1.28
V
VCC–1.1
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ψJB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. VIN (max) is specified when VT is floating.
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LVDS Outputs DC Electrical Characteristics(6)
VCC = 2.5V ±5%; RL = 100Ω across output pair or equivalent; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
VOCM
Output Common Mode Voltage
Condition
Max
Units
1.125
Min
Typ
1.275
V
ΔVOCM
Change in VOCM between
complementing output states
–50
+50
mV
VOUT
Output Voltage Swing
See Figure 1a.
250
325
mV
VDIFF-OUT
Differential Output Voltage Swing
See Figure 1b.
500
650
mV
Min
Typ
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.5V ±5%; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
-125
IIL
Input LOW Current
-300
Max
2.0
Units
V
0.8
V
30
µA
µA
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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AC Electrical Characteristics(7)
VCC = 2.5V ±5%; RL = 100Ω across the output pair; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
fMAX
Maximum Operating Frequency
VOUT ≥ 200mV, Clock
1.5
2.0
tpd
Differential Propagation Delay
(8)
550
800
1200
ps
(8)
500
700
1100
ps
17
cycles
1200
ps
In-to-Q
100mV < VIN ≤ 200mV
In-to-Q
200mV < VIN ≤ 800mV
SEL-to-Q
RPE enabled, see Timing Diagram
SEL-to-Q
RPE disabled (VSEL = VCC/2)
600
tPD
Tempco
Differential Propagation Delay
Temperature Coefficient
tS EN
Set-up Time
EN-to-CLK
Note 9
0
tH EN
Hold Time
CLK-to-EN
Note 9
650
tSKEW
Output-to-Output Skew
Note 10
Part-to-Part Skew
tJITTER
tr, tf
Max
Units
GHz
o
500
fs/ C
ps
ps
5
25
ps
Note 11
300
ps
Random Jitter
Note 12
1
psRMS
Cycle-to-Cycle Jitter
Note 13
1
psRMS
Total Jitter
Note 14
10
psPP
0.7
psRMS
220
ps
Clock
Crosstalk-Induced Jitter
Note 15
Output Rise/Fall Time (20% to 80%)
At full output swing.
70
120
Notes:
7. High-frequency AC-parameters are guaranteed by design and characterization.
8. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%) and VIL ≥ 800mV. The propagation delay is function of the rise and
fall times at IN. See “Typical Operating Characteristics” for details.
9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
10. Output-to-Output skew is measured between two different outputs under identical transitions.
11. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
12. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
13. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
12
14. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more
than the specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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SY89465U
Functional Description
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI
functionality is described with the following four case
descriptions. All descriptions are related to the true
inputs and outputs. The primary (or selected) clock
is called CLK1; the secondary (or alternate) clock is
called CLK2. Due to the totally asynchronous
relation of the IN and SEL signals and an additional
internal protection against metastability, the number
of pulses required for the operations described in
cases 1-4 can vary within certain limits. Refer to
“Timing Diagrams” section for detailed information.
RPE MUX and Fail-Safe Input
The SY89465U is optimized for clock switchover
applications where switching from one clock to
another clock without runt pulses (short cycles) is
required. It features two unique circuits:
Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover
between two clocks and prevents any runt pulses
from occurring during the switchover transition. The
design of both clock inputs is identical (i.e., the
switchover sequence and protection is symmetrical
for both input pairs, IN0 or IN1. Thus, either input
pair may be defined as the primary input). If not
required, the RPE function can be permanently
disabled to allow the switchover between inputs to
occur immediately. If the CAP pin is tied directly to
VCC, the RPE function will be disabled and the
multiplexer will function as a normal multiplexer.
Case #1: Two Normal Clocks and RPE Enabled
In this case, the frequency difference between the
two running clocks, IN0 and IN1, must not be greater
than 1.5:1. For example, if the IN0 clock is 500MHz,
the IN1 clock must be within the range of 334MHz to
750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur
in three stages.
• Stage 1: The output will continue to follow CLK1
for a limited number of pulses.
• Stage 2: The output will remain LOW for a
limited number of pulses of CLK2.
• Stage 3: The output follows CLK2.
Fail-Safe Input (FSI) Circuit
The FSI function provides protection against a
selected input pair that drops below the minimum
amplitude requirement. If the selected input pair
drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV
differentially (VDIFF_IN), the output will latch to the last
valid clock state.
Timing Diagram 1
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Case #2: Input Clock Failure: Switching from a
selected clock stuck HIGH to a valid clock (RPE
enabled).
If CLK1 fails HIGH before the RPE MUX selects
CLK2 (using the SEL pin), the switchover will occur
in three stages.
• Stage 1: The output will remain HIGH for a
limited number of pulses of CLK2.
• Stage 2: The output will switch to LOW and then
remain LOW for a limited number of falling edges
of CLK2.
• Stage 3: The output will follow CLK2.
Timing Diagram 2
Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be
greater than 50% of the CLK2 period.
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Case #3: Input Clock Failure: Switching from a
selected clock stuck Low to a valid clock (RPEenabled).
If CLK1 fails LOW before the RPE MUX selects
CLK2 (using the SEL pin), the switchover will occur
in two stages.
• Stage 1: The output will remain LOW for a
limited number of falling edges of CLK2.
• Stage 2: The output will follow CLK2.
Timing Diagram 3
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Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE-enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend upon rise and fall time of the input signal
and on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
Timing Diagram 4
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Enable Output(s):
1. EN toggles from Low-to-High.
2. Output(s) follow the selected clock after next
HIGH-to-LOW transition of the selected
input. See “Timing Diagram 5.”
Enable Output (EN) Description
The enable function is synchronous so that the
outputs will be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt pulse when the device is
enabled/disabled as can happen with asynchronous
control.
Disable Output(s):
1. EN toggles from High-to-Low
2. Output(s) follow the selected Clock input
3. Output (CLK) goes to a logic LOW level
(/CLK goes to a logic HIGH), after next Highto-Low transition of the selected input. See
Timing Diagram 5.
Timing Diagram 5
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Power-On Reset (POR) Description
The following formula describes this relationship:
The SY89465U includes an internal power-on reset
(POR) function to ensure that the RPE logic startsup in a known logic state once the power-supply
voltage is stable. An external capacitor connected
between VCC and the CAP pin (pin 12) controls the
delay for the power-on reset function.
The required capacitor value calculation is based
upon the time the system power supply needs to
power up to a minimum of 2.3V. The time constant
for the internal power-on-reset must be greater than
the time required for the power supply to ramp up to
a minimum of 2.3V.
December 2005
As an example, if the time required for the system
power supply to power up past 2.3V is 12ms, then
the required capacitor value on pin 12 would be:
C(µF) ≥ 1µF
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Typical Operating Characteristics
VCC = 2.5V, GND = 0V, VIN ≥ 400mV, tr / tf ≤ 300ps, RL = 50Ω to VCC–2V; TA = 25°C, unless otherwise stated.
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Functional Characteristics
VCC = 2.5V, GND = 0V, VIN ≥ 400mVpk, tr/tf ≤ 300ps, RL = 100Ω across output pair; TA = 25°C, unless otherwise stated.
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Single-Ended and Differential Swings
Figure 1b. Differential Voltage Swing
Figure 1a. Single-Ended Voltage Swing
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
December 2005
Figure 2b. Simplified Differential Output Stage
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Input Interface Applications
Option: may connect VT to VCC
Figure 3a. LVPECL Interface
(DC-Coupled)
Figure 3b. LVPECL Interface
(AC-Coupled)
Figure 3d. CML Interface
(AC-Coupled)
Figure 3e. LVDS Interface
(DC-Coupled)
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Figure 3c. CML Interface
(DC-Coupled)
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variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as
a function of data input, is kept to a minimum, to
keep EMI low.
LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a
nominal 1.20V common mode above ground. The
common mode voltage has tight limits to permit large
Figure 4a. LVDS Differential Measurement
Figure 4b. LVDS Common Mode Measurement
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89464U
Precision LVPECL Runt Pulse Eliminator
2 :1 MUX with 1:10 Fanout Buffer and
Internal Termination
www.micrel.com/product-info/products/sy89464u.shtml.
TM
MLF
HBW Solutions
December 2005
Application Note
www.amkor.com/products/notes_papers/MLFAppNote.pdf
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
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SY89465U
44 Lead MicroLeadFrameTM (MLF-44)
Packages Notes:
1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended
for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a
significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a
Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Inc.
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