3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX Micrel, Inc. Precision Edge® SY89826L ® Precision Edge SY89826L FEATURES ■ High-performance, 1GHz LVDS fanout buffer/ translator ■ 22 differential LVDS output pairs ■ Guaranteed AC parameters over temperature and voltage: • > 1GHz fMAX • < 50ps within device skew • < 400ps tr / tf time ■ Low jitter performance • < 1ps (rms) cycle-to-cycle jitter • < 1ps (pk-pk) total jitter ■ 2:1 mux input accepts LVDS and LVPECL 3.3V supply voltage ■ LVDS input includes internal 100Ω termination ■ Output enable function ■ Available in a 64-Pin EPAD-TQFP Precision Edge® DESCRIPTION The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination. The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89826L features a low pin-to-pin skew of less than 50ps—performance previously unachievable in a standard product having such a high number of outputs. The SY89826L is available in a single space saving package, enabling a lower overall cost solution. APPLICATIONS ■ Enterprise networking ■ High-end servers ■ Communications TRUTH TABLE FUNCTIONAL BLOCK DIAGRAM 100Ω internal input termination 22 LVDS compatible outputs CLK_SEL LVDS_CLK 0 /LVDS_CLK 22 22 OE(1) CLK_SEL Q0 – Q21 /Q0 – /Q21 0 0 LOW HIGH 0 1 LOW HIGH 1 0 LVDS_CLK /LVDS_CLK 1 1 LVPECL_CLK /LVPECL_CLK Q0 - Q21 NOTE: 1. The OE (output enable) signal is synchronized with the low level of the LVDS_CLK and LVPECL_CLK signal. /Q0 - /Q21 LVPECL_CLK 1 LEN /LVPECL_CLK OE Q D Precision Edge is a registered trademark of Micrel, Inc. M9999-011907 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: January 2007 Precision Edge® SY89826L Micrel, Inc. VCCO Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 VCCO PACKAGE/ORDERING INFORMATION Ordering Information(1) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCCO GNDO NC VCCI LVDS_CLK /LVDS_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GNDI OE NC GNDO /Q21 Q21 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GNDO Q7 /Q7 Q8 /Q8 Q9 /Q9 Q10 /Q10 Q11 /Q11 Q12 /Q12 Q13 /Q13 GNDO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Part Number Package Type Operating Range Package Marking Lead Finish SY89826LHI H64-1 Industrial SY89826LHI Sn-Pb SY89826LHITR(2) H64-1 Industrial SY89826LHI Sn-Pb SY89826LHY(3) H64-1 Industrial SY89826LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89826LHYTR(2, 3) H64-1 Industrial SY89826LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn VCCO /Q20 Q20 /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 VCCO Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) PIN DESCRIPTIONS Pin Number Pin Name I/O 5, 6 LVDS_CLK /LVDS_CLK Input LVDS 3.3kΩ w/100Ω pull-up internal (Figure 2) terminator 8, 9 LVPECL_CLK /LVPECL_CLK Input LVPECL 7 CLK_SEL Input LVTTL/ CMOS 11 OE Input LVTTL/ 63, 61, 59, 57, 55, 53, 51, 47, 45, 43, 41, 39, 37, 35, 31, 29, 27, 25, 23, 21, 19, 15 Q0 – Q21 Output LVDS Differential LVDS clock outputs when OE = HIGH and static LOW when OE = LOW. Unused output pairs must be terminated with 100Ω across the differential pair to maintain low skew and jitter. 62, 60, 58, 56, 54, 52, 50, 46, 44, 42, 40, 38, 36, 34, 30, 28, 26, 24, 22, 20, 18, 14 /Q0 – /Q21 Output LVDS Differential clock outputs (complement) when OE = HIGH and static HIGH when OE = LOW. Unused output pairs must be terminated with 100Ω across the differential pair to maintain low skew and jitter. 4 VCCI Power Core VCC connect to 3.3V supply. Not connected to VCCO internally. Connect to VCCO on PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCC pins as possible. 1, 16, 17, 32, 49, 64 VCCO Power Output buffer VCC connects to 3.3V supply. Not connected to VCCI internally. Connect to VCCI on PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCC pins as possible. 10 GNDI Power Core ground not connected to GNDO internally. Connect to GNDO on PCB. 2, 13, 33, 48 GNDO Power Output buffer ground not connected to GNDI internally. Connect to GNDI on PCB. 3, 12 NC M9999-011907 [email protected] or (408) 955-1690 Type Internal Pull-up/ Pull-down Pin Function Differential LVDS clock input. Selected when CLKSEL = LOW (Can be left floating if CLKSEL = HIGH). This input pair includes internal termination, and is intended to interface directly to LVDS. Leave floating if not used. 75kΩ Differential LVPECL clock input. Selected when CLKSEL = pull-down HIGH (Can be left floating if CLKSEL = LOW). Requires (Figure 1) external termination. Leave floating if not used. 11kΩ to VCCI Selects LVDS_CLK when LOW and LVPECL_CLK when HIGH. Default condition is HIGH if left floating. Output enable/disable function. When LOW, Q outputs go LOW, /Q outputs go HIGH. Asynchronous input that is synchronized internally to prevent output glitches or runt pulses. No connect pins to be left open. 2 Precision Edge® SY89826L Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Power Supply Voltage (VCCI, VCCO) .............. –0.5 to +4.0V Input Voltage (VIN) ........................................... –0.5 to VCCI Output Current (IOUT) ............................................... ±10mA Lead Temperature (TLEAD, Soldering, 20sec.) .......... 260°C Storage Temperature (TS) ........................... –65 to +150°C ESD Rating, Note 3 .................................................... >1kV Supply Voltage (VCC to GND) ..................... +3.0V to +3.6V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance TQFP (θJA) Exposed pad soldered to GND Still-Air(multi-layer PCB) .................................. 23°C/W –200lfpm (multi-layer PCB) ............................. 18°C/W –500lfpm (multi-layer PCB) ............................. 15°C/W Exposed pad NOT soldered to GND (not recommened) Still-Air(multi-layer PCB) .................................. 44°C/W –200lfpm (multi-layer PCB) ............................. 36°C/W –500lfpm (multi-layer PCB) ............................. 30°C/W TQFP (θJC) ......................................................... 4.4°C/W Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Note 3. Devices are ESD sensitive. Handling precautions recommended. DC ELECTRICAL CHARACTERISTICS Power Supply: TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VCCI, VCCO VCC Core, VCC Output Note 4 3.0 3.3 3.6 V ICCI ICC Core Max. VCC 46 70 mA ICCO ICC Output No Load, Max. VCC 175 260 mA Note 4. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die. LVDS Input: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter VIN Input Voltage Range VID Differential Input Swing IIL Input LOW Current RIN LVDS Differential Input Resistance (LVDS_CLK to /LVDS_CLK) M9999-011907 [email protected] or (408) 955-1690 Condition Min Typ 0 Units 2.4 V 100 mV –1.25 mA 80 3 Max 100 120 Ω Precision Edge® SY89826L Micrel, Inc. DC ELECTRICAL CHARACTERISTICS LVPECL Input: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition VIH Input HIGH Voltage (Single-Ended) VIL Input LOW Voltage VPP Minimum Input Swing (LVPECL_CLK) VCMR Common Mode Range (LVPECL_CLK) Note 7 IIH Input HIGH Current IIL Input LOW Current Min Note 6 Typ Max Units VCC –1.165 VCC –0.880 V VCC –1.945 VCC –1.625 V 300 mV GNDI +1.8 VCCI –0.4 V 150 µA µA 0.5 Note 6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. Note 7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). VCMR range varies 1:1 with VCCI. VCMR (min) is fixed at GNDI +1.8V. CMOS/LVTTL Inputs: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current VIN = VCC IIL Input LOW Current VIN = 0.5V Min Typ Max 2.0 Units V 0.8 V 150 µA µA –600 LVDS Output: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VOD Differential Output Voltage Note 8, 9 250 350 400 mV VOH Output HIGH Voltage Note 8 1.474 V VOL Output LOW Voltage Note 8 0.925 VOCM Output Common Mode Voltage Note 9 1.125 1.375 V ∆VOCM Change in Common Mode Voltage –50 50 mV Note 8. Measured as per Figure 3, 100Ω across Q and /Q outputs. Note 9. Measured as per Figure 4. M9999-011907 [email protected] or (408) 955-1690 4 V Precision Edge® SY89826L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(1) VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Toggle Frequency Note 2 1.0 tPHL tPLH Differential Propagation Delay, Note 3 LVPECL Input: 150mV LVPECL Input: 800mV 0.750 0.6 1.0 0.850 1.250 1.10 ns ns LVDS Input: 100mV LVDS Input: 400mV 0.950 0.800 1.2 1.0 1.450 1.30 ns ns 1.4 1.7 ns GHz tSWITCHOVER Clock Input Switchover CLK_SEL-to-Valid Output tS(OE) Output Enable Set-Up Time Note 4 1.0 ns tH(OE) Output Enable Hold Time Note 4 0.5 ns tskew Within Device Skew Note 5 Part-to-Part Skew Note 6 Cycle-to-Cycle Total Jitter Note 7 Note 8 tJITTER tr, tf Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. 0°C to +85°C –40°C Output Rise/Fall Times (20% to 80%) 25 200 50 75 ps ps 400 ps <1 1 2 psRMS psPP 290 400 ps 100Ω termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane. Typicals are at nominal supply, TA = 25°C. fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Output swing is ≥ 200mV. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device with identical input transition, operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn–Tn+1 where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-topeak jitter value. M9999-011907 [email protected] or (408) 955-1690 5 Precision Edge® SY89826L Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS Output Amplitude vs. Frequency PROPAGATION DELAY (ps) 500 450 Nominal Propagation Delay vs. Temperature 400 350 300 250 200 150 100 50 0 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 FREQUENCY (MHz) Propagation Delay vs. Input Amplitude LVPECL INPUT 0 1000 800 600 400 200 0 -50 6 LVPECL Input -25 0 25 50 75 TEMPERATURE (°C) 100 CLK_SEL Switchover Time vs. Temperature 1600 1400 1200 1000 800 600 400 200 0 -50 200 400 600 800 1000 INPUT AMPLITUDE (mV) M9999-011907 [email protected] or (408) 955-1690 2000 LVDS IN = 350mV 1800 LVPECL IN = 750mV 1600 1400 LVDS Input 1200 1800 LVDS INPUT SWITCHOVER TIME (ns) PROPAGATION DELAY (ns) OUTPUT VOLTAGE (mV) VCC = 3.3V, VEE = GND, TA = 25°C, unless otherwise stated -25 0 25 50 75 TEMPERATURE (°C) 100 Precision Edge® SY89826L Micrel, Inc. FUNCTIONAL CHARACTERISTICS 155MHz Output 622MHz Output TA = 25°C VCC = 3.3V /Q Output Swing (50mV/div.) TA = 25°C VCC = 3.3V Output Swing (50mV/div.) /Q Q Q TIME (500ps/div.) TIME (200ps/div.) 1GHz Output TA = 25°C VCC = 3.3V Output Swing (50mV/div.) /Q Q TIME (100ps/div.) M9999-011907 [email protected] or (408) 955-1690 7 Precision Edge® SY89826L Micrel, Inc. LVPECL/LVDS INPUTS VCC VCC 1.9k LVPECL_CLK 1.9k 1.4k 75k 1.4k LVDS_CLK 75k 100Ω /LVDS_CLK /LVPECL_CLK GND GND Figure 2. Simplified LVDS Input Stage Figure 1. Simplified LVPECL Input Stage LVDS OUTPUTS LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low. 49.9Ω, ±1% vOD vOH, vOL 100Ω ±1% vOCM, ∆vOCM 49.9Ω, ±1% vOH, vOL GND GND Figure 4. LVDS Common Mode Measurement Figure 3. LVDS Differential Measurement QOUT QOUT 700mV QOUT — /QOU 350mV (typical) /QOUT /QOUT Figure 6. Output Driver Signal Levels (Differential) Figure 5. Output Driver Signal Levels (Single-Ended) M9999-011907 [email protected] or (408) 955-1690 8 Precision Edge® SY89826L Micrel, Inc. DETAILED DESCRIPTION CLK_SEL Input The CLK_SEL TTL Input is used to select either LVDS_CLK (CLK_SEL is LOW) or LVPECL_CLK (CLK_SEL is LOW),. OE The SY89826L's output enable function is designed to disable the outputs only when the outputs are LOW. This avoids the possibility of generating runt pulses. The OE input is an asynchronous input, but operates as a synchronous enable. For synchronous operation, please adhere to the specific setup and hold times. When disabled, the Q outputs are LOW and the /Q outputs are HIGH. LVDS Outputs The SY89826L's LVDS outputs swing typically 350mV around a 1.25V common mode voltage above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input is kept tight to keep EMI low. Each of the SY89826L's LVDS outputs should be terminated with a 100Ω termination resistor including any unused output pairs. This ensures the best jitter and skew performance of the device. The SY89826L is a precision 1:22 fanout buffer. It accepts either an LVPECL or LVDS input, selectable by an input mux, and outputs 22 LVDS output pairs. The device features a synchronous output enable. The SY89826L provides extremely low skew across its outputs. LVPECL_CLK The SY89826L allows one input with standard LVPECL voltage swing. This input may be adjusted per the data sheet characteristics regarding the CMR and minimum input swing. As the SY89826L contains no appropriate internal termination, upstream devices need to be properly terminated to provide the proper LVPECL input swing. If not being used (CLK_SEL is LOW), this input pair may be left floating, as it is internally terminated to ground via a 75kΩ pull-down resistor. LVDS_CLK The SY89826L allows one input with standard LVDS voltage swing. The SY89826L provides an appropriate internal 100Ω termination resistor. Hence, upstream LVDS devices do not require external termination to drive the SY89826L. If not being used (CLK_SEL is HIGH), this input pair may be left floating. RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY55855V Dual CML/PECL/LVPECL-to-LVDS Translator www.micrel.com/product-info/products/sy55855v.shtml SY89825U 2.5/3.3V 1:22 High-performance, Low-voltage PECL Bus Clock Driver & Translator w/ Internal Termination www.micrel.com/product-info/products/sy89825u.shtml SY89828L 3.3V 1GHz Dual 1:10 Precision LVDS Fanout Buffer with 2:1 Input Mux www.micrel.com/product-info/products/sy89828l.shtml SY89829U 2.5/3.3V High-performance, Dual 1:10 LVPECL Clock Driver w/ Internal Termination & Redundant Switchover www.micrel.com/product-info/products/sy89829u.shtml M-0317 HBW Solutions www.micrel.com/product-info/as/solutions.shtml Exposed Pad Amkor Exposed Pad Application Note www.amkor.com/products/notes_papers/epad.pdf M9999-011907 [email protected] or (408) 955-1690 9 Precision Edge® SY89826L Micrel, Inc. 64-PIN EPAD-TQFP (DIE UP) (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-011907 [email protected] or (408) 955-1690 10