SY89843U Precision LVPECL Runt Pulse Eliminator 2:1 MUX with 1:2 Fanout and Internal Termination General Description The SY89843U is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89843U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or “runt” pulses during switchover. In addition, a unique Fail-Safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV). The differential input includes Micrel’s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The output is 800mV, 100K compatible LVPECL with fast rise/fall times guaranteed to be less than 190ps. The SY89843U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89843U is ® part of Micrel’s high-speed, Precision Edge product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge ® Features • Selects between two sources, and provides a glitch-free, stable LVPECL output • Guaranteed AC performance over temperature and supply voltage: – Wide operating frequency: 1kHz to >1.5GHz – < 880ps In-to-Out tpd – < 190ps tr/tf • Unique patent-pending input isolation design minimizes crosstalk • Fail-Safe Input prevents oscillations • Ultra-low jitter design: – <1psRMS random jitter – <1psRMS cycle-to-cycle jitter – <10psPP total jitter (clock) – <0.7psRMS MUX crosstalk induced jitter • Unique patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) • 800mV LVPECL output swing • 2.5V ±5% or 3.3V ±10% supply voltage • –40°C to +85°C industrial temperature range • Available in 24-pin (4mm x 4mm) MLF™ package Applications • Redundant clock switchover • Failsafe clock protection Markets • • • • LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com March 2005 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Typical Application Simplified Example Illustrating RPE (Runt Pulse Elimination) Circuit when Primary Clock Fails March 2005 2 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free SY89843UMG MLF-24 Industrial SY89843U with bar-line Pb-Free indicator SY89843UMGTR(2) MLF-24 Industrial SY89843U with bar-line Pb-Free indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only. 2. Tape and Reel. Pin Configuration 24-Pin MLFTM (MLF-24) March 2005 3 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Pin Description Pin Number Pin Name Pin Function 5, 2 23, 20 IN0, /IN0, IN1, /IN1 Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of a pair internally terminates to a VT pin through 50Ω. Please refer to the “Input Interface Applications” section for more details. 4, 22 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. Please refer to the “Input Interface Applications” section for more details. 3, 21 VREF-AC0 VREF-AC1 Reference Voltage: These outputs bias to VCC–1.2V. They are used for ACcoupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please refer to the “Input Interface Applications” section for more details. 15 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. 1, 6, 9, 10, 13, 19, 24 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to VCC pins as possible. 7, 8 11, 12 Q0, /Q0 Q1, /Q1 14, 17, 18 GND Exposed Pad 16 CAP Differential Outputs: These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details. Ground: Ground pin and exposed pad must be connected to the same ground plane. Power-On Reset (POR) Initialization capacitor. When using the multiplexer with RPE capability, the pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See “Power-On Reset (POR) Description” section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open. Truth Table INPUTS March 2005 OUTPUTS IN0 /IN0 IN1 /IN1 SEL Q /Q 0 1 X X 0 0 1 1 0 X X 0 1 0 X X 0 1 1 0 1 X X 1 0 1 1 0 4 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .............................................. –0.5V to +4.0V Input Voltage (VIN) ......................................................–0.5V to VCC LVPECL Output Current (IOUT) Continuous .................................................................. ±50mA Surge ........................................................................ ±100mA Termination Current Source/Sink Current on VT ........................................ ±100mA Input Current Source/sink current on IN, /IN ..................................... ±50mA VREF-AC Current Source/sink current on VREF-AC ...................................... ±2mA Lead Temperature (soldering, 20 sec.) ..............................+260°C Storage Temperature (Ts).................................... –65°C to 150°C Supply Voltage (VCC) .............................+2.375V to +2.625V .............................................................. +3.0V to +3.6V Ambient Temperature (TA)........................... –40°C to +85°C (3) Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................... 50°C/W MLF™ (ΨJB) Junction-to-Board .............................................. 30°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C; unless otherwise stated. Symbol Parameter VCC Power Supply ICC Power Supply Current RIN Input Resistance (IN-to-VT) RDIFF_IN Condition Min Typ Max Units 2.375 3.0 2.5 3.3 2.625 3.6 V V 70 100 mA 45 50 55 Ω Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) 1.2 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. Note 5 0.1 VCC V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 1b. 0.2 VIN_FSI Input Voltage Threshold that triggers FSI VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage No load, max VCC. V 30 VCC–1.3 VCC–1.2 100 mV 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ΨJB values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIN (max) is specified when VT is floating. March 2005 5 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U LVPECL Outputs DC Electrical Characteristics(6) VCC = 2.5V ±5% or 3.3V ±10%, RL = 50Ω to VCC-2V; TA = -40°C to + 85°C, unless otherwise stated. Symbol Parameter VOH Output HIGH Voltage Q, /Q Condition VCC-1.145 Min Typ VCC–0.895 Max Units V VOL Output Low Voltage Q, /Q VCC-1.945 VCC–1.695 V VOUT Output Voltage Swing Q, /Q See Figure 1a. 550 800 mV VDIFF-OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 1100 1600 mV LVTTL/CMOS DC Electrical Characteristics(6) VCC = 2.5V ±5% or 3.3V ±10%; TA = -40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Typ Max 2.0 Units V 0.8 V 30 µA µA Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. March 2005 6 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U AC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%, RL = 50Ω to VCC–2V; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Operating Frequency VOUT ≥ 400mV 1.5 2.0 tpd Differential Propagation Delay In-to-Q 100mV < VIN ≤ 200mV(8, 9) 480 600 880 ps In-to-Q (8, 9) 430 575 780 ps 17 cycles 900 ps 200mV < VIN ≤ 800mV SEL-to-Q RPE enabled, see Timing Diagram SEL-to-Q RPE disabled (VSEL = VCC/2) Typ 550 Max Units GHz tpd Tempco Differential Propagation Delay Temperature Coefficient tSKEW Output-to-Output Skew Within device(10) 20 ps Part-to-Part Skew Note 11 200 ps Random Jitter Note 12 1 psRMS Cycle-to-Cycle Jitter Note 13 1 psRMS Total Jitter Note 14 10 psPP Crosstalk-induced Jitter Note 15 0.7 psRMS Output Rise/Fall Time (20% to 80%) At full output swing. 190 ps tJITTER tr, tf o fs/ C 410 Clock 70 Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%) and VIL ≥ 800mV. 9. Propagation delay is a function of the rise and fall times at IN. See “Typical Operating Characteristics” for details. 10. Output-to-output skew is measured between two different outputs under identical conditions. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 12 14. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 15. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. March 2005 7 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Functional Description RPE MUX and Fail-Safe Input The SY89843U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: Runt-Pulse Eliminator (RPE) Circuit: The RPE MUX provides a “glitchless” switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to VCC, then the RPE function will be disabled and the multiplexer will function as a normal multiplexer. Fail-Safe Input (FSI) Circuit: The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV differentially (VDIFF_IN), then the output will latch to the last valid clock state. RPE and FSI Functionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to “Timing Diagrams” for more detailed information. Case #1 Two Normal Clocks and RPE Enabled In this case, the frequency difference between the two running clocks IN0 and IN1 must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. If the SEL input changes state to select the alternate clock, then the switchover from CLK1 to CLK2 will occur in three stages. • Stage 1: The output will continue to follow CLK1 for a limited number of pulses. Stage 2: The output will remain LOW for a limited number of pulses of CLK2. Stage 3: The output follows CLK2. • • Timing Diagram 1 March 2005 8 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Case #2 Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled). If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), then the switchover will occur in three stages. • • • Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. Stage 3: The output will follow CLK2 Timing Diagram 2 Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period. March 2005 9 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Case #3 Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled). If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages. • • Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. Stage 2: The output will follow CLK2. Timing Diagram 3 March 2005 10 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Case #4 Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled). If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV (VIN) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1. If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for more detailed information. Timing Diagram 4 Power-On Reset (POR) Description The SY89843U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 16) controls the delay for the power-on reset function. Calculating the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V. The following equation describes this relationship: C(µF) ≥ t dPS ( ms ) 12( ms / µF ) As an example, if the time required for the system power supply to power up past 2.3V is 12ms, the required capacitor value on pin 16 would be: C(µF) ≥ 12ms 12( ms / µF ) C(µF) ≥ 1µF March 2005 11 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Typical Operating Characteristics VCC = 3.3V, GND = 0V, VIN ≥ 400mVpk, tr/tf ≤ 300ps, RL = 50Ω to VCC–2V, TA = 25°C, unless otherwise stated. March 2005 12 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Functional Characteristics VCC = 3.3V, GND = 0V, VIN ≥ 400mVpk, tr/tf ≤ 300ps, RL = 50Ω to VCC–2V, TA = 25°C, unless otherwise stated. March 2005 13 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Singled-Ended and Differential Swings Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing Input and Output Stages Figure 2a. Simplified Differential Input Stage March 2005 Figure 2b. Simplified LVPECL Output Stage 14 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Input Interface Applications Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface March 2005 15 Figure 3c. CML Interface (DC-Coupled) M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U LVPECL Output Interface Applications LVPECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced. Figure 4a. Parallel Termination-Thevenin Equivalent Figure 4b. Parallel Termination (3-Resistor) Related Product and Support Documentation Part Number Function Data Sheet Link SY89844U Precision LVDS Runt Pulse Eliminator 2:1 MUX with 1:2 Fanout and Internal Termination www.micrel.com/product-info/products/sy89844u.shtml SY89845U Precision CML Runt Pulse Eliminator 2:1 MUX with 2:1 Fanout and Internal Termination www.micrel.com/product-info/products/sy89845u.shtml MLFTM Application Note www.amkor.com/products/notes_papers/MLFAppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions March 2005 16 M9999-031505 [email protected] or (408) 955-1690 Micrel, Inc. SY89843U Product Information 24-Pin MLF™ (MLF-24) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. March 2005 17 M9999-031505 [email protected] or (408) 955-1690