MICREL SY89854UMG

SY89854U
Precision Low Power 1:4 LVPECL Fanout
Buffer/Translator with Internal Termination
General Description
The SY89854U is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer.
Optimized to provide four identical output copies
with less than 20ps of skew and less than 10ps(pp)
total jitter, the SY89854U can process clock signals
as fast as 2GHz.
The differential input includes Micrel’s unique, patent
pending 3-pin input termination architecture that
interfaces to any differential signal (AC or DCcoupled) as small as 100mV (200mVpp) without any
level shifting or termination resistor networks in the
signal path. For AC-coupled input interface
applications, an on-board output reference voltage
(VREF-AC) is provided to bias the center-tap (VT)
pin. The outputs are 800mV LVPECL, with fast
rise/fall times guaranteed to be less than 180ps.
The SY89854U operates from a 2.5V ±5% supply or
a 3.3V ±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C.
The SY89854U is part of Micrel’s high-speed,
®
Precision Edge product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Typical Applications
200MHz (Q - /Q)
®
Precision Edge
Features
• Precision 1:4, LVPECL fanout buffer
• Low power: 137mW (2.5V typ)
• Guaranteed AC performance over temperature
and supply voltage:
– DC- to > 2GHz Clock fMAX
– <340ps tpd
– <180ps tr/tf time
– <20ps max. skew
• Ultra-low jitter design:
– <1ps(rms) random jitter
– <10ps(pp) deterministic jitter
– <10ps(pp) total jitter (clock)
• Unique patent pending input termination and VT
pin accepts DC-coupled and AC-coupled inputs
(CML, PECL, LVDS)
• Typical 800mV (100k) LVPECL output swing
• Power supply 2.5V ±5% or 3.3V ±10%
• Industrial temperature range –40°C to +85°C
• Available in ultra-small (3mm x 3mm) 16-pin
MLF™ package
Applications
Output Swing
(200mV/div.)
• SONET and All GigE clock distribution
• Fibre Channel clock and data distribution
• Backplane distribution
TIME (600ps/div.)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
June 2005
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SY89854U
Ordering Information(1)
Part Number
Package Type
Operating
Range
Package Marking
Lead
Finish
SY89854UMG
MLF-16
Industrial
854U with Pb-free bar-line indicator
Pb-Free
NiPdAu
MLF-16
Industrial
854U with Pb-free bar-line indicator
Pb-Free
NiPdAu
SY89854UMGTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
16-Pin MLF™ (MLF-16)
Pin Description
Pin Number
Pin Function
IN, /IN
Differential Input: This input pair is the signal to be buffered. These inputs accept
AC- or DC-coupled differential signals as small as 100mV (200mVpp). Each pin
of this pair internally terminates to a VT pin through 50Ω. Note that this input will
default to an indeterminate state if left open. Please refer to the “Input Interface
Applications” section for more details.
2
VT
Input Termination Center-Tap: Each side of the differential input pair terminates
to this pin. The VT pin provides a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
8,13
VCC
Positive Power Supply. Bypass with 0.1µF⎪⎪0.01µF low ESR capacitors as close
to the VCC pin as possible.
15, 14
12, 11
10, 9
7, 6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Differential 100K LVPECL Output: These LVPECL outputs are the precision, low
skew copies of the input signal. Terminate with 50Ω to VCC–2V. Unused output
pairs may be left floating with no impact on jitter. See “Output Interface
Applications” section.
5, 16
GND,
Exposed Pad
Ground. Ground pin and exposed pad must be connected to the same ground
plane.
VREF-AC
Reference Voltage: This output biases to VCC–1.2V. It is used when AC coupling
the inputs (IN, /IN). Connect VREF-AC to the VT pin. Bypass VREF-AF pin with a
0.01µF low ESR capacitor to VCC. Maximum sink/source capability is 1.5mA. See
“Input Interface Applications” section for more details.
1, 4
3
June 2005
Pin Name
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SY89854U
Functional Block Diagram
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SY89854U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ..........................–0.5V to +4.0V
Input Voltage (VIN) ..................................–0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ................................................. 50mA
Surge........................................................ 100mA
Termination Current(3)
Source or sink current on VT .................... ±50mA
Input Current
Source or sink current on IN, /IN.............. ±50mA
VREF-AC Current(3)
Source or sink current ................................ ±2mA
Lead Temperature (soldering, 20sec.) ...........+260°C
Storage Temperature (Ts)..................–65°C to 150°C
Supply Voltage (VCC).................. +2.375V to +2.625V
......................................................+3.0V to +3.6V
Ambient Temperature (TA)................ –40°C to +85°C
Package Thermal Resistance(4)
MLF™ (θJA)
Still-Air ..................................................... 60°C/W
MLF™ (ψJB)
Junction-to-Board .................................... 38°C/W
DC Electrical Characteristics (5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VCC
Power Supply
ICC
Power Supply Current
RDIFF_IN
Differential Input Resistance
(IN, /IN)
RIN
Input Resistance
(IN-to-VT)
VIH
Input High Voltage
(IN, /IN)
VIL
Input Low Voltage
(IN, /IN)
VIN
Input Voltage Swing
(IN, /IN)
See Figure 1a.
VDIFF_IN
Differential Input Voltage Swing
(IN, /IN)
See Figure 1b.
VT_IN
IN-to-VT
Min
Typ
Max
Units
2.375
2.5
2.625
V
3.0
3.3
3.6
V
55
78
mA
90
100
110
Ω
45
50
55
Ω
VCC –1.6
VCC
V
0
VIH –0.1
V
0.1
1.7
V
No load, max. VCC
Note 6
0.2
V
1.28
V
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. This is a stress rating only and functional operation
is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to Absolute Maximum Ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ψJB are calculated based on a 4-layer board in still air, unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. VIH (min) not lower than 1.2V
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SY89854U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to + 85°C; RL = 50Ω to VCC –2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Q, /Q
VCC–1.145
VCC–0.895
V
VOL
Output LOW Voltage
Q, /Q
VCC–1.945
VCC–1.695
V
VOUT
Output Voltage Swing
Q, /Q
See Figure 1a.
550
800
mV
VDIFF-OUT
Differential Output Voltage Swing
Q,/Q
See Figure 1b.
1100
1600
mV
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY89854U
AC Electrical Characteristics(8)
VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC–2V, unless otherwise stated.
Symbol
Parameter
fMAX
Maximum Operating Frequency
Condition
Min
Clock, VOUT ≥ 400mV
2.0
NRZ Data
tpd
Propagation Delay (IN-to-Q)
tpd
Tempco
Differential Propagation Delay Temperature
Coefficient
tSKEW
Output-to-Output Skew
Note 9
tJitter
tr, tf
VIN ≥ 100mVpk
140
Typ
Max
Units
3.5
GHz
2.5
Gbps
220
340
fs/oC
100
4
ps
20
ps
Part-to-Part Skew
Note 10
150
ps
Random Jitter (RJ)
Note 11
1
ps(rms)
Deterministic Jitter (DJ)
Note 12
10
ps(pp)
Cycle-to-Cycle Jitter
Note 13
1
ps(rms)
Total Jitter
Note 14
10
ps(pp)
Output Rise/Fall Time (20% to 80%)
At full output swing.
180
ps
50
100
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Output-to-output skew is measured between outputs under identical conditions.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs. Part-to-part skew includes variation in tpd.
11. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps.
23
12. DJ is measured at 2.5Gbps, with both K28.5 and 2 – 1 PRBS pattern.
13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
12
14. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more
than the specified peak-to-peak jitter value.
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SY89854U
Typical Operating Characteristics
VCC = 2.5V, VIN = 100mVpk, TA = 25°C, unless otherwise stated.
100
200 1200 2200 3200 4200 5200 6200
FREQUENCY (MHz)
218
216
214
212
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (¡C)
216
214
212
210
208
206
1100
200
220
900
1000
300
222
218
800
400
224
220
600
700
500
222
400
500
600
226
300
700
PROPAGATION DELAY (ps)
AMPLITUDE (mV)
800
100
200
228
900
Propagation Delay
vs. Input Voltage
Propagation Delay
vs. Temperature
PROPAGATION DELAY (ps)
Amplitude
vs. Frequency
INPUT VOLTAGE (mV)
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SY89854U
Functional Characteristics
VCC = 2.5V, VIN = 100mV, TA = 25°C, unless otherwise stated.
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SY89854U
Single-Ended and Differential Swings
Figure 1a. Singled-Ended Voltage Swing
Figure1b. Differential Voltage Swing
Timing Diagrams
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SY89854U
Input and Output Stages
Figure 2b. Simplified LVPECL Output Stage
Figure 2a. Simplified Differential Input Stage
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SY89854U
Input Interface Applications
Option: may connect VT to VCC
3a. LVPECL Interface
(DC-Coupled)
3b. LVPECL Interface
(AC-Coupled)
3d. CML Interface
(AC-Coupled)
3e. LVDS Interface
June 2005
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3c. CML Interface
(DC-Coupled)
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SY89854U
Output Interface Applications
Note:
For +2.5V systems, Rb = 19Ω
For +3.3V systems, Rb = 50Ω
Note:
For +2.5V systems, R1 = 250Ω, R2 = 82.5Ω
Figure 4b. Parallel Termination
(3-Resistor)
Figure 4a. Parallel Thevenin-Equivalent
Termination
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY58021U
4GHz, 1:4 LVPECL Fanout
Buffer/Translator with Internal Termination
www.micrel.com/product-info/products/sy58021u.shtml
HBW Solutions
June 2005
MLFTM Application Note
www.amkor.com/products/notes_papers/MLF_AppNote.pdf
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
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SY89854U
16 Lead MicroLeadFrameTM (MLF-16)
Package Notes:
(1) Package meets Level 2 Moisture Sensitivity Classification.
(2) All parts are dry-packaged before shipment.
(3) Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended
for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a
significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a
Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
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