XICOR X25045

APPLICATION NOTES
A V A I L A B L E
X25043/45AN11 • AN21
X25043/45
4K
512 x 8 Bit
Programmable Watchdog Supervisory E2PROM
FEATURES
DESCRIPTION
•
•
•
•
•
The X25043/45 combines three popular functions,
Watchdog Timer, Voltage Supervision, and E2PROM in
a single package. This combination lowers the system
cost and reduces the board space requirements.
•
•
•
•
•
•
•
•
Programmable Watchdog Timer
Low VCC Detection
Reset Signal Valid to VCC = 1V
1MHz Clock Rate
512 X 8 Bits Serial E2PROM
—4 Byte Page Mode
Low Power CMOS
—50µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block LockTM
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Available Packages
—8-Lead PDlP
—8-Lead SOIC
—14-Lead TSSOP
X25043 = Active LOW RESET
X25045 = Active HIGH RESET
The Watchdog Timer provides an independent protection system for microcontrollers. During a system failure,
the X25043/45 watchdog will respond with a RESET/
RESET signal after a selectable time-out interval. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling the power.
The system is protected from low voltage conditions by
the X25043/45 low VCC detection circuits. When VCC
drops below the minimum VCC trip point, the system is
reset. Reset is asserted until VCC returns and stabilizes.
The memory portion of the X25043/45 is a CMOS 4096bit serial E2PROM, internally organized as 512 X 8. The
X25043/45 features a Serial Peripheral Interface (SPI)
and software protocol allowing operation on a simple
three-wire bus.
The X25043/45 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
DIE PHOTOGRAPH
RESET
CONTROL
LOGIC
SERIAL
INTERFACE
LOGIC
PROGRAMMABLE
VOLTAGE
SENSOR
4K BITS E22PROM
W
A T
T I
C M
H E
D R
O
G
HIGH
HIGH VOLTAGE
VOLTAGE GENERATOR
GENERATOR
AND
AND
CONTROL
CONTROL
3844 ILL F01
Direct Write™ is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3844-6.5 5/9/96 T4/C2/D2 NS
1
Characteristics subject to change without notice
X25043/45
PIN CONFIGURATION
PIN DESCRIPTIONS
Serial Output (SO)
X25043/45
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
8-LEAD DIP/SOIC
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input
on this pin. Data is latched by the rising edge of the serial
clock.
CS
1
8
VCC
SO
2
7
RESET/RESET
WP
3
6
SCK
VSS
4
5
SI
X25043/45
14-LEAD TSSOP
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X25043/45 will
be in the standby power mode. CS LOW enables the
X25043/45, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
CS
1
14
VCC
SO
2
13
RESET/RESET
NC
3
12
NC
NC
4
11
NC
NC
5
10
NC
WP
6
9
SCK
VSS
7
8
SI
3844 ILL F02.3
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
RESET/RESET
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25043/45
are disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25043/45. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Reset (RESET, RESET)
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
3844 PGM T01.1
X25043/45, RESET/RESET is an active LOW/HIGH,
open drain output which goes active whenever VCC
falls below the mimimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if
the Watchdog timer is enabled and CS remains either
HIGH or LOW longer than the Watchdog time-out
period. A falling edge of CS will reset the watchdog timer.
2
X25043/45
PRINCIPLES OF OPERATION
The Write-In-Process (WIP) bit indicates whether the
X25043/45 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The WIP bit is read-only.
E2PROM
The X25043/45 is a 512 x 8
designed to
interface directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller families.
The X25043/45 contains an 8-bit instruction register. It
is accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and WP input must
be HIGH during the entire operation. The X25043/45
monitors the bus and provides a RESET/RESET output
if there is no bus activity within the preset time period.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset. The WEL bit is readonly and is set by the WREN instruction and reset by
WRDI instruction or successful completion of a write
cycle.
Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first. Bit 3 of the Read and Write
instructions contain the higher order address bit, A8.
The Block Protect (BL0 and BL1) bits indicate the extent
of protection employed. These nonvolatile bits are set by
issuing the WRSR instruction and allows the user to
select one of four levels of protection and program the
watchdog timer. The X25043/45 is divided into four
1024-bit segments. One, two, or all four of the segments
may be locked. That is, the user may read the segments
but will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below with the state of BL1 and BL0.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations.
Write Enable Latch
The X25043/45 contains a “write enable” latch. This
latch must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle. The latch is also reset if WP is
brought LOW.
Status Register Bits
BL1
BL0
0
0
1
1
0
1
0
1
Status Register
6
5
4
X WD1 WD0
None
$180–$1FF
$100–$1FF
$000–$1FF
3844 PGM T04
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is formatted as follows:
7
X
Array Addresses
Protected
3
BL1
2
BL0
1
WEL
The Watchdog Timer (WD0 and WD1) bits allow setting
of the watchdog time-out function as shown in the table
below. These nonvolatile bits are set by issuing the
WRSR instruction.
0
WIP
Status Register Bits
WD1
WD0
3844 PGM T02
0
0
1
1
When issuing, WREN, WRDI and RDSR commands, it
is not necessary to send a byte address or data.
0
1
0
1
Watchdog Time-out
(Typical)
1.4 Seconds
600 Milliseconds
200 Milliseconds
Disabled
3844 PGM T03
3
X25043/45
transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction the write operation
will be ignored.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. Bit 3 of the Write
instruction contains address A8. This bit is used to select
the upper or lower half of the device. This is minimally a
twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25043/45. The only restriction is the four bytes must
reside on the same page. A page address begins with
address X XXXX XX00 and ends with X XXXX XX11. If
the byte address counter reaches X XXXX XX11 and the
clock continues the counter will roll back to the first
address of the page and overwrite any data that may
have been written.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25043/45, followed by
the 8-bit byte address. Bit 3 of the Read instruction
contains address A8. This bit is used to select the upper
or lower half of the device. After the read opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
read sequentially by continuing to provide clock pulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($1FF) the
address counter rolls over to address $000, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read E2PROM Array operation sequence illustrated in
Figure 1.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after the
twenty-fourth, thirty-second, fortieth, or forty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 and 5
below for a detailed illustration of the write sequences.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register is shifted out on
the SO line as shown in Figure 2.
While the write is in progress, following a status register
or E2PROM write sequence the status register may be
read to check the WIP bit. During this time the WIP bit will
be HIGH and all other bits in the status register will be
undefined.
Write Sequence
Prior to any attempt to write data into the X25043/45 the
“write enable” latch must first be set by issuing
the WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25043/45. After all eight bits of the instruction are
RESET/RESET Operation
The RESET (X25043) output is designed to go LOW
whenever VCC has dropped below the minimum trip
point and/or the Watchdog timer has reached its programmable time-out limit.
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RDSR
WRSR
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
READ
0000 A8011
WRITE
0000 A8010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Block Lock Bits)
Read Data from Memory Array beginning at selected
address
Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)
3844 PGM T05.1
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
4
X25043/45
The RESET (X25045) output is designed to go HIGH
whenever VCC has dropped below the minimum trip
point and/or the watchdog timer has reached its programmable time-out limit.
Data Protection
Operational Notes
• A WREN instruction must be issued to set the “write
enable” latch.
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
The X25043/45 powers-up in the following state:
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
The “write enable” latch is reset when WP is brought
LOW.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
INSTRUCTION
BYTE ADDRESS
8
SI
7
6
5
4
3
2
1
0
9TH BIT OF ADDRESS
DATA OUT
HIGH IMPEDANCE
7
SO
6
5
4
3
2
1
0
MSB
3844 FHD F04
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
SO
MSB
5
6
5
4
3
2
1
0
3844 ILL F15
X25043/45
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3844 FHD F05
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
7
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
8
SI
DATA BYTE
BYTE ADDRESS
5
4
3
2
1
0
7
6
5
4
3
2
1
0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
3844 FHD F06
SYMBOL TABLE
WAVEFORM
6
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X25043/45
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
SI
DATA BYTE 1
BYTE ADDRESS
7
8
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
9TH BIT OF ADDRESS
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
DATA BYTE 2
SI
7
6
5
4
3
2
DATA BYTE 3
1
0
7
6
5
4
3
2
DATA BYTE 4
1
0
7
6
5
4
3
2
1
0
3844 FHD F07
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
7
6
10 11 12 13 14 15
SCK
DATA BYTE
INSTRUCTION
SI
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3844 ILL F08
7
X25043/45
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with Respect to VSS ...... –1.0V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
–40°C
Supply Voltage
X25043/45
X25043/45-2.7
Max.
70°C
+85°C
Limits
5V ±10%
2.7 to 5.5V
3844 PGM T07.3
3844 PGM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
ICC
VCC Supply Current (Active)
Min.
Max.
3
Units
mA
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,
SO = Open
ISB1
VCC Standby Current
50
µA
CS = VCC, VIN = VSS or VCC, VCC = 5.5
ISB2
VCC Standby Current
20
µA
CS = VCC, VIN = VSS or VCC, VCC = 2.7V
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VIL(1)
VIH(1)
Input LOW Voltage
VCC x 0.3
V
VCC x 0.7 VCC + 0.5
V
VOL
Output LOW Voltage
VOH1
Output HIGH Voltage
VOH2
Output HIGH Voltage
Input HIGH Voltage
–0.5
0.4
V
IOL = 2mA
VCC–0.8
V
IOH = –1.6mA, VCC = 4.5V
VCC–0.4
V
IOH = –.4mA, VCC = 2.7V
V
IOL = 1mA
VOLRS Reset Output LOW Voltage
0.4
3844 PGM T08.3
POWER-UP TIMING
Symbol
tPUR(2)
Parameter
Power-up to Read Operation
tPUW(2)
Power-up to Write Operation
Min.
Max.
1
Units
ms
5
ms
3844 PGM T09
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.
Symbol
COUT
(2)
CIN(2)
Notes:
Test
Max.
Units
Conditions
Output Capacitance (SO, RESET, RESET)
8
pF
VOUT = 0V
Input Capacitance (SCK, SI, CS, WP)
6
pF
VIN = 0V
(1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
8
3844 PGM T10.2
X25043/45
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
5V
5V
4.6KΩ
OUTPUT
3844 PGM T11
RESET/RESET
100pF
100pF
3844 FHD F12.2
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
tSU
tH
tRI(3)
tFI(3)
tCS
tWC(4)
Parameter
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
Min.
Max.
Units
0
1000
500
500
500
400
100
100
1
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ms
2
2
500
10
3844 PGM T12.2
Data Output Timing
Symbol
fSCK
tDIS
tV
tHO
tRO(3)
tFO(3)
Parameter
Min.
Max.
Units
Clock Frequency
Output Disable Time
Output Valid from Clock LOW
Output Hold Time
Output Rise Time
Output Fall Time
0
1
500
400
MHz
ns
ns
ns
ns
ns
0
300
300
3844 PGM T13.1
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
9
X25043/45
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
tHO
MSB OUT
tWL
tDIS
MSB–1 OUT
LSB OUT
ADDR
LSB IN
3844 FHD F09
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
SI
tH
tRI
MSB IN
tFI
LSB IN
HIGH IMPEDANCE
SO
3844 FHD F10
10
X25043/45
Power-Up and Power-Down Timing
VTRIP
VCC
VTRIP
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X25043)
RESET (X25045)
3844 FHD F13.1
RESET Output Timing
Symbol
VTRIP
tPURST
tRPD(5)
tF(5)
tR(5)
VRVALID
Parameter
Min.
Reset Trip Point Voltage, 5V Device
Reset Trip Point Voltage, 2.7V Device
Power-up Reset Timeout
VCC Detect to Reset/Output
VCC Fall Time
VCC Rise Time
Reset Valid VCC
Typ.
4.25
2.55
100
Max.
Units
4.5
2.7
400
500
V
V
ms
ns
µs
ns
V
10
0
1
3844 PGM T14.3
Notes: (5) This parameter is periodically sampled and not 100% tested.
CS vs RESET/RESET Timing
CS
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET
3844 FHD F14.1
RESET/RESET Output Timing
Symbol
tWDO
tCST
tRST
Parameter
Watchdog Timeout Period,
WD1=1,WD0=0
WD1=0,WD0=1
WD1=0,WD0=0
CS Pulse Width to Reset the Watchdog
Reset Timeout
Min.
Typ.
Max.
Units
100
450
1
400
100
200
600
1.4
300
800
2
ms
ms
sec
ns
ms
400
3844 PGM T15.3
11
X25043/45
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.020 (0.51)
0.016 (0.41)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.060 (1.52)
0.020 (0.51)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X25043/45
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" TYPICAL
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
0.030"
TYPICAL
8 PLACES
X25043/45
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
14
X25043/45
ORDERING INFORMATION
X25043/45
P
T
-V
VCC Limits
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
Part Mark Convention
X25043/45
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
V = 14-Lead TSSOP
X
X
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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