SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999 D D High-Current 3-State Outputs Interface Directly With System Bus or Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN54HC126 . . . J OR W PACKAGE SN74HC126 . . . D, DB, OR N PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND description These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. OUTPUT Y H H H H L L L X Z 13 3 12 4 11 5 10 6 9 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A A 2 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A FUNCTION TABLE (each buffer) OE 14 SN54HC126 . . . FK PACKAGE (TOP VIEW) The SN54HC126 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC126 is characterized for operation from –40°C to 85°C. INPUTS 1 NC – No internal connection logic symbol† 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 3 EN 2 4 6 5 10 8 9 13 11 12 1Y 2Y 3Y 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, and W packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 3A 4 5 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, and W packages. absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54HC126 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V SN74HC126 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 VIL Low-level input voltage 0 1.8 0 1.8 VI VO Input voltage 0 0 Output voltage 0 VCC VCC 0 VCC VCC 1000 0 1000 Input transition (rise and fall) time VCC = 2 V VCC = 4.5 V 0 tt 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –20 µA VOH VI = VIH or VIL IOH = –6 mA IOH = –7.8 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ VI = VCC or 0 VO = VCC or 0 ICC Ci VI = VCC or 0, IO = 0 MIN TA = 25°C TYP MAX SN54HC126 MIN MAX SN74HC126 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF 6V 2 V to 6 V 3 V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C MIN TYP MAX SN54HC126 SN74HC126 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 47 120 180 150 tpd A Y 4.5 V 14 24 36 30 ten tdis tt OE OE Y Y Any MIN MAX MIN MAX 6V 11 20 31 26 2V 57 120 180 150 4.5 V 16 24 36 30 6V 12 20 31 26 2V 35 120 180 150 4.5 V 17 24 36 30 6V 15 20 31 26 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns 3 SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten FROM (INPUT) TO (OUTPUT) A Y OE Y tt Any VCC MIN TA = 25°C TYP MAX SN54HC126 MIN MAX SN74HC126 MIN MAX 2V 67 150 225 188 4.5 V 19 30 45 38 6V 15 25 39 33 2V 100 135 202 169 4.5 V 20 27 40 36 6V 17 23 36 30 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 45 UNIT pF SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 tPZH ten RL CL (see Note A) 1 kΩ tPZL tPHZ tdis S2 RL 1 kΩ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ tpd or tt –– LOAD CIRCUIT 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL 90% VOH 50% 10% V OL tf 90% tr tPHL Out-of-Phase Output 90% tPLH 50% 10% 50% 10% 90% VOH VOL tf tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Control VCC 50% 50% 0V tPZL Output Waveform 1 (See Note B) tPLZ ≈ VCC 50% 10% VOL tPZH Input 50% 10% 90% VCC 90% 50% 10% 0 V tr Output Waveform 2 (See Note B) 90% VOH ≈0V tPHZ tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 50% VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. 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