Order this document by MC34115/D CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR Providing a simplified approach to digital speech encoding/decoding, the MC34115 CVSD is designed for speech synthesis and commercial telephone applications. A single IC provides both encoding and decoding functions. • Encode and Decode Functions Selectable with a Digital Input • Utilization of Compatible I2L – Linear Bipolar Technology • • • SEMICONDUCTOR TECHNICAL DATA CMOS Compatible Digital Output Digital Input Threshold Selectable (VCC/2 Reference Provided On–Chip) 3–Bit Algorithm 16 1 P SUFFIX PLASTIC PACKAGE CASE 648 16 CVSD Block Diagram Encode/Decode Analog Input Analog Feedback 1 14 16 – 2 + PIN CONNECTIONS Digital 13 Data Input – 3–Bit Shift Register + Digital 12 Threshold Q Q Q Q Q Q Vth VCC/2 Output 14 Clock Syllabic Filter 3 9 10 16 VCC 15 Encode/Decode Analog Input (–) 1 Analog Feedback (+) 2 11 Coincidence Output Logic Digital Output DW SUFFIX PLASTIC PACKAGE CASE 751G (SO–16L) VCC Clock 15 1 VCC/2 Ref V/I Converter Integrator Amplifier Slope Polarity Switch – IRef IO 7 Analog Output + IInt 5 Ref Input (+) 6 Filter Input (–) 3 4 Gain Control 4 13 Digital Data Input (–) Ref Input (+) 5 12 Digital Threshold Filter Input (–) 6 Analog Output 7 VEE 8 Syllabic Filter Gain Control 10 VCC/2 Output 9 Digital Output (Top View) IGC 8 VEE ORDERING INFORMATION Device MC34115P This device contains 144 active transistors. MC34115DW Operating Temperature Range TA = 0° to +70°C Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA 11 Coincidence Output Package Plastic DIP SO–16L Rev 1 1 MC34115 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MAXIMUM RATINGS (All voltages referenced to VEE, TA = 25°C, unless otherwise noted.) (Note 2) Rating Symbol Value Unit Power Supply Voltage VCC –0.4 to +18 Vdc Differential Analog Input Voltage VID ±5.0 Vdc Digital Threshold Voltage Vth –0.4 to VCC Vdc VLogic –0.4 to +18 Vdc Logic Input Voltage (Clock, Digital Data, Encode/Decode) Coincidence Output Voltage VO(Con) –0.4 to +18 Vdc Syllabic Filter Input Voltage VI(Syl) –0.4 to VCC Vdc Gain Control Input Voltage VI(GC) –0.4 to VCC Vdc Reference Input Voltage VI(ref) VCC/2 – 1.0 to VCC Vdc VCC/2 Output Current Iref –25 mA Operating Ambient Temperature Range TA 0 to +70 °C TJ +150 °C Tstg –55 to +125 °C Operating Junction Temperature Storage Temperature Range NOTE: ESD data available upon request. ELECTRICAL CHARACTERISTICS (VCC = 12 V, VEE = Gnd, TA = 0° to 70°C, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Power Supply Voltage Range (Figure 1) VCC 4.75 12 16.5 Vdc Power Supply Current (Figure 1) (Idle Channel) VCC = 5.0 V VCC = 15 V ICC Clock Rate mA – – 4.6 7.0 7.5 12 SR – 16 k – Samples/s IGCR 0.002 – 3.0 mA Analog Comparator Input Range (Pins 1 and 2) 4.75 V ≤ VCC ≤ 16.5 V VI 1.3 – VCC – 1.3 Vdc Analog Output Range (Pin 7) 4.75 V ≤ VCC ≤ 16.5 V, IO = ±5.0 mA VO 1.3 – VCC – 1.3 Vdc Input Bias Currents (Figure 3) Comparator in Active Region Analog Input (I1) Analog Feedback (I2) Syllabic Filter Input (I3) Reference Input (I5) IIB Input Offset Current Comparator in Active Region Analog Input/Analog Feedback I1 – I2 (Figure 3) Integrator Amplifier I5 – I6 (Figure 4) IIO Input Offset Voltage V/I Converter (Pins 3 and 4) (Figure 5) VIO Transconductance V/I Converter, 0 to 3.0 mA Integrator Amplifier, 0 to +5.0 mA Load gm Gain Control Current Range (Figure 2) µA – – – – 0.5 0.5 0.06 –0.06 2.5 2.5 0.5 –0.5 µA – 0.15 0.8 – 0.02 0.2 – 2.0 10 0.1 1.0 0.3 10 – – mV mA/mV NOTES: 1. All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock. 2. Devices should not be operated at these values. The “Electrical Characteristics” provide conditions for actual device operation. 3. Dynamic total loop offset (ΣVoffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch current mismatch appears as an average voltage across the 10 k integrator resistor. The clock frequency is 16 kHz. Idle channel performance is guaranteed if this dynamic total loop offset is less than one–half of the change in integrator output voltage during one clock cycle (ramp step size). 2 MOTOROLA ANALOG IC DEVICE DATA MC34115 ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V, VEE = Gnd, TA = 0° to 70°C, unless otherwise noted.) Characteristic Symbol Min Typ Max tPLH tPHL tPLH tPHL – – – – 1.0 0.8 1.0 0.8 3.0 3.0 3.5 2.5 Coincidence Output Voltage – Low Logic Stage (IOL(Con) = 3.0 mA) VOL(Con) – 0.12 0.25 Coincidence Output Leakage Current – High Logic State (VOH = 15 V) Propagation Delay Times (Note 1) Clock Trigger to Digital Output CL = 25 pF to Gnd Clock Trigger to Coincidence Output CL = 25 pF to Gnd, RL = 4.0 kΩ to VCC Unit µs Vdc IOH(Con) – 0.01 0.5 µA Applied Digital Threshold Voltage Range (Pin 12) Vth 1.2 – VCC – 2.0 Vdc Digital Threshold Input Current 1.2 V ≤ Vth ≤ VCC – 2.0 V VIL Applied to Pins 13, 14 and 15 VIH Applied to Pins 13, 14 and 15 II(th) µA – – – –10 5.0 –50 Maximum Integrator Amplifier Output Current IO ±5.0 – – mA VCC/2 Generator Maximum Output Current (Source Only) Iref –10 – – mA VCC/2 Generator Output Impedance (0 to –10 mA) zref – 3.0 6.0 Ω εr – – ±3.5 % VIL VIH VEE Vth + 0.4 – – Vth – 0.4 16.5 VCC/2 Generator Tolerance (4.75 V ≤ VCC ≤ 16.5 V) Logic Input Voltage (Pins 13, 14 and 15) Low Logic State High Logic State Dynamic Total Loop Offset Voltage (Note 3) (Figures 3, 4 and 5) IGC = 33 µA, VCC = 12 V TA = 25°C 0°C ≤ TA ≤ +70°C IGC = 33 µA, VCC = 5.0 V TA = 25°C 0°C ≤ TA ≤ +70°C Digital Output Voltage (Pin 9) IOL = 3.6 mA IOH = –0.35 mA Syllabic Filter Applied Voltage (Pin 3) (Figure 2) Integrating Current (Figure 2) IGC = 12 µA IGC = 1.5 mA IGC = 3.0 mA Dynamic Integrating Current Match (Figure 6) (IGC = 1.5 mA) Vdc ΣVoffset mV – – ±2.5 ±3.0 ±7.0 ±10 – – ±4.0 ±4.5 ±8.0 ±12 VOL VOH – VCC – 1.0 0.1 VCC – 0.2 0.4 – VI(Syl) 3.2 – VCC Vdc 8.0 1.4 2.75 10 1.5 3.0 12 1.6 3.25 µA mA mA – ±100 ±300 mV – – – – – – 5.0 5.0 5.0 –10 –360 –36 –72 – – – – – – – – Vdc IInt VO(Ave) Input Current – High Logic State (VIH = 16.5 V) Digital Data Input Clock Input Encode/Decode Input IIH Input Current – Low Logic State (VIL = 0 V) Digital Data Input Clock Input Encode/Decode Input Clock Input, VIL = 0.4 V IIL µA µA NOTES: 1. All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock. 2. Devices should not be operated at these values. The “Electrical Characteristics” provide conditions for actual device operation. 3. Dynamic total loop offset (ΣVoffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch current mismatch appears as an average voltage across the 10 k integrator resistor. The clock frequency is 16 kHz. Idle channel performance is guaranteed if this dynamic total loop offset is less than one–half of the change in integrator output voltage during one clock cycle (ramp step size). MOTOROLA ANALOG IC DEVICE DATA 3 MC34115 DEFINITION AND FUNCTION OF PINS Pin 1 – Analog Input This is the analog comparator inverting input where the voice signal is applied. It may be ac or dc coupled depending on the application. If the voice signal is to be level shifted to the internal reference voltage, then a bias resistor between Pins 1 and 10 is used. The resistor is used to establish the reference as the new dc average of the ac coupled signal. The analog comparator was designed for low hysteresis (typically less than 0.1 mV) and high gain (typically 70 dB). Pin 7 – Analog Output This is the integrator op amp output. It is capable of driving a 600 Ω load referenced to VCC/2 to +6.0 dBm and can otherwise be treated as an op amp output. Pins 5, 6 and 7 provide full access to the integrator op amp for designing integration filter networks. The slew rate of the internally compensated integrator op amp is typically 0.5 V/µs. Pin 7 output is current limited for both polarities of current flow at typically 30 mA. Pin 2 – Analog Feedback This is the noninverting input to the analog signal comparator. In an encoder application it should be connected to the analog output of the encoder circuit. This may be Pin 7 or a low pass filter output connected to Pin 7. In a decode circuit, Pin 2 is not used and may be tied to VCC/2 at Pin 10 or ground. The analog input comparator has bias currents of 2.5 µA max, thus the driving impedances of Pins 1 and 2 should be equal to avoid disturbing the idle channel characteristics of the encoder. Pin 8 – VEE The circuit is designed to work in either single or dual power supply applications. Pin 8 is always connected to the most negative supply. Pin 3 – Syllabic Filter This is the point at which the syllabic filter voltage is returned to the IC in order to control the integrator step size. It is an NPN input to an op amp. The syllabic filter consists of an RC network between Pins 11 and 3. Typical time constant values of 6.0 ms to 50 ms are used in voice codecs. Pin 4 – Gain Control Input The syllabic filter voltage appears across CS of the syllabic filter and is the voltage between VCC and Pin 3. The active voltage to current (V–I) converter drives Pin 4 to the same voltage at a slew rate of typically 0.5 V/µs. Thus the current injected into Pin 4 (IGC) is the syllabic filter voltage divided by the Rx resistance. Figure 7 shows the relationship between IGC (x–axis) and the integrating current, IInt (y–axis). The discrepancy, which is most significant at very low currents, is due to circuitry within the slope polarity switch which enables trimming to a low total loop offset. The Rx resistor is then varied to adjust the loop gain of the codec, but should be no larger than 5.0 kΩ to maintain stability. Pin 5 – Reference Input This pin is the noninverting input of the integrator amplifier. It is used to reference the dc level of the output signal. In an encoder circuit, it must reference the same voltage as Pin 1 and is tied to Pin 10. Pin 6 – Filter Input This inverting op amp input is used to connect the integrator external components. The integrating current (IInt) flows into Pin 6 when the analog input (Pin 1) is high with respect to the analog feedback (Pin 2) in the encode mode or when the digital data input (Pin 13) is high in the decode mode. For the opposite states, IInt flows out of Pin 6. Single integration systems require a capacitor and resistor between Pins 6 and 7. Multipole configurations will have different circuitry. The resistance between Pins 6 and 7 should typically be between 8.0 kΩ and 13 kΩ to maintain good idle channel characteristics. 4 Pin 9 – Digital Output The digital output provides the results of the delta modulator’s conversion. It swings between VCC and VEE and is CMOS or TTL compatible. Pin 9 is inverting with respect to Pin 1 and noninverting with respect to Pin 2. It is clocked on the falling edge of Pin 14. The typical 10% to 90% rise and fall times are 250 ns and 50 ns respectively for VCC = 12 V and CL = 25 pF to ground. Pin 10 – VCC/2 Output An internal low impedance mid–supply reference is provided for use in single supply applications. The internal regulator is a current source and must be loaded with a resistor to ensure its sinking capability. If a +6.0 dBmo signal is expected across a 600 Ω input bias resistor, then Pin 10 must sink 2.2 V/600 Ω = 3.66 mA. This is possible only if Pin 10 sources 3.66 mA into a resistor normally and will source the difference under peak load. The reference load resistor is chosen accordingly. A 0.1 µF bypass capacitor from Pin 10 to VEE is also recommended. The VCC/2 reference is capable of sourcing 10 mA and can be used as a reference elsewhere in the system circuitry. Pin 11 – Coincidence Output The coincidence output will be low whenever the content of the internal 3–bit shift register is all 1s or all 0s. Pin 11 is an open collector NPN device and requires a pull–up resistor. If the syllabic filter is to have equal charge and discharge time constants, the value of RP should be much less than RS. In systems requiring different charge and discharge constants, the charging constant is RSCS while the decay constant is (RS + RP)CS. Thus, longer decays are easily achievable. The NPN device should not be required to sink more than 3.0 mA. The typical 10% to 90% rise and fall times are 200 ns and 100 ns respectively for RL = 4.0 kΩ to 12 V and CL = 25 pF to ground. Pin 12 – Digital Threshold This input sets the switching threshold for Pins 13, 14 and 15. It is intended to aid in interfacing different logic families without external parts. Typically it is connected to the VCC/2 reference for CMOS interface or can be biased two diode drops above VEE for TTL interface. MOTOROLA ANALOG IC DEVICE DATA MC34115 Pin 13 – Digital Data Input In a decode application, the digital data stream is applied to Pin 13. In an encoder it may be unused or may be used to transmit a signaling message under the control of Pin 15. It is an inverting input with respect to Pin 9. When Pins 9 and 13 are connected, a toggle flip–flop is formed and a forced idle channel pattern can be transmitted. The digital data input level should be maintained for 0.5 µs before and after the clock trigger for proper clocking. minimum high time for the clock input is 300 ns and minimum low time is 900 ns. Pin 15 – Encode/Decode This pin controls the connection of the analog input comparator and the digital input comparator to the internal shift register. If high, the result of the analog comparison will be clocked into the register on the falling edge at Pin 14. If low, the digital input state will be entered. This allows use of the IC as an encoder/decoder or simplex codec without external parts. Furthermore, it allows non–voice patterns to be forced onto the transmission line through Pin 13 in an encoder. Pin 14 – Clock Input The clock input determines the data rate of the codec circuit. A 16 k bit rate requires a 16 kHz clock. The switching threshold of the clock input is set by Pin 12. The shift register circuit toggles on the falling edge of the clock input. The Pin 16 – VCC The power supply range is from 4.75 to 16.5 V between Pin VCC and VEE. Figure 2. IGCR – Gain Control Range and IInt – Integrating Current Figure 1. Power Supply Current VCC VCC ICC 1.0 k 10 µF 10 µF 0.1 0.1 1 16 1 16 2 15 2 15 3 14 3 14 Clock (Note 2) 4 13 13 Digital Data Input 1.0 k 60 mV + – + Clock 5.0 k 0.1 5 CVSD MC34115 VB – Rx IGC 4 0.1 12 5 10 k CVSD MC34115 12 + VRBx R x v 5.0 k 10 k I 10 k 6 11 6 A 0.05 7 10 8 9 I Int 11 GC 0.05 7 10 8 9 Digital Output (Note 1) 0.1 0.1 NOTES: 1. Digital Output = Digital Data Input 2. For static testing, the clock is only necessary for preconditioning to obtain proper state for a given input. MOTOROLA ANALOG IC DEVICE DATA 5 MC34115 Figure 3. Input Bias Currents, Analog Comparator Offset Voltage and Current VCC VIO(Comparator) I1 I2 1.0 k – VCC 10 µF 1.0 k + Figure 4. Integrator Amplifier Offset Voltage and Current 100 mV 0.1 10 µF 1 16 1 16 2 15 2 15 3 14 0.1 I3 3 14 Clock 0.1 100 k 0.1 I5 4 CVSD MC34115 13 4 0.1 I5 10 k I6 12 5 10 k 6 11 0.05 10 k 7 10 8 9 0.1 13 CVSD MC34115 5 12 6 11 0.05 + (Integrator Amplifier Offset Voltage) – 7 10 8 9 NOTE: The analog comparator offset voltage is tested under dynamic conditions and therefore must be measured with appropriate filtering. Figure 5. V/I Converter Offset Voltage, VIO and VIOX 0.1 Figure 6. Dynamic Integrating Current Match VCC VCC 10 µF 60 mV + – 10 µF 0.1 1 16 1 16 2 15 2 15 3 14 3 14 4 13 4.5 V + – Clock (16 kHz) IGC 5.0 k 0.1 5 CVSD MC34115 4 12 CVSD MC34115 13 5 12 6 11 10 k 6 10 k 11 0.05 7 10 k + 10 0.05 7 10 0.1 VIOX (Notes 1 and 2) – Clock (16 kHz) 3.0 k 0.1 10 k + 0.1 8 9 0.1 VO(AV) (Note 1) 8 9 – NOTES: 1. Integrator amplifier offset voltage plus slope polarity switch mismatch. 2. VIOX is the average voltage of the triangular waveform observed at the measurement points. 6 NOTES: 1. VO(AV), Dynamic Integrating Current Match, is the average voltage of the triangular waveform observed at the measurement points, across 10 kΩ resistor with IGC = 1.5 mA. 2. See Note 3 in the Electrical Characteristics table. 3. See Figures 8 and 9. MOTOROLA ANALOG IC DEVICE DATA MC34115 TYPICAL PERFORMANCE CURVES ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ Figure 8. Normalized Dynamic Integrating Current Match versus VCC Figure 7. Typical IInt versus IGC (Mean ±2 σ) 30 20 10 7.0 5.0 3.0 VCC = 12 V TA = 25°C 2.0 1.0 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 80 VO(AV), NORMALIZED DYNAMIC INTEGRATING CURRENT MATCH (mV) IInt , INTEGRATING CURRENT (µ A) – PIN 6 100 70 50 TA = 25°C fCLK = 16 kHz (See Figure 6, Normalized to 10 kΩ @ IGC = 1.5 mA) 60 40 20 0 –20 –40 –60 –80 5.0 6.0 7.0 IGC, GAIN CONTROL CURRENT (µA) – PIN 4 VO(AV) , NORMALIZED DYNAMIC INTEGRATING CURRENT MATCH (mV) 50 25 0 –25 TA = 25°C VCC = 12 V (See Figure 6, Normalized to 10 kΩ @ IGC = 1.5 mA) –50 –75 –100 10 20 30 40 50 70 100 13 14 15 Figure 10. Dynamic Total Loop Offset versus Clock Frequency 200 ∑ Voffset, DYNAMIC TOTAL LOOP OFFSET (mV) Figure 9. Normalized Dynamic Integrating Current Match versus Clock Frequency 8.0 9.0 10 11 12 VCC, SUPPLY VOLTAGE (V) 1.0 0 IGC = 33 µA –1.0 –2.0 VCC = 12 V TA = 25°C (See Note 3 in Electrical Characteristics Table) 10 fCLK, CLOCK FREQUENCY (kHz) 20 30 40 50 70 100 200 fCLK, CLOCK FREQUENCY (kHz) Figure 11. Block Diagram of the CVSD Encoder Clock ε(t) Audio In Comparator Sampler Digital Out Level Detect Algorithm Integrator MOTOROLA ANALOG IC DEVICE DATA Slope Polarity Switch Slope Magnitude Control 7 MC34115 Figure 12. CVSD Waveforms Integrator Output (Reconstructed Audio) Input Audio Digital Output Figure 13. Block Diagram of the CVSD Decoder Clock Audio Out 8 Level Detect Algorithm Sampler Digital In Integrator Slope Magnitude Control Slope Polarity Switch MOTOROLA ANALOG IC DEVICE DATA MOTOROLA ANALOG IC DEVICE DATA Analog 7 Output Encode/ 15 Decode 50 µA 200 µA 50 µA D 50 µA — Q 25 k 25 k C Q 100 µ A – Clock 20 k + 14 Digital 12 Threshold Digital 13 Data Input Analog 1 Input Analog 2 Feedback 20 k VCC 16 D — Q 10 VCC /2 Output C Q 5.0 µA Ref Input 5 12 k D C 50 µA — Q Q Figure 14. CVSD Circuit Schematic 6 Filter Input 8 VEE 50 µA 7.0 µA Filter 3 Syllabic 4 Gain Control Output 11 Coincidence 9 Digital Output MC34115 9 MC34115 CIRCUIT DESCRIPTION The continuously variable slope delta modulator (CVSD) is a simple alternative to more complex conventional conversion techniques in systems requiring digital communication of analog signals. The human voice is analog, but digital transmission of any signal over great distance is attractive. Signal/noise ratios do not vary with distance in digital transmission and multiplexing, switching and repeating hardware is more economical and easier to design. However, instrumentation A–D converters do not meet the communications requirements. The CVSD A–D is well suited to the requirements of digital communications and is an economically efficient means of digitizing analog inputs for transmission. The Delta Modulator The innermost control loop of a CVSD converter is a simple delta modulator. A block diagram CVSD Encoder is shown in Figure 11. A delta modulator consists of a comparator in the forward path and an integrator in the feedback path of a simple control loop. The inputs to the comparator are the input analog signal and the integrator output. The comparator output reflects the sign of the difference between the input voltage and the integrator output. That sign bit is the digital output and also controls the direction of ramp in the integrator. The comparator is normally clocked so as to produce a synchronous and band–limited digital bit stream. If the clocked serial bit stream is transmitted, received, and delivered to a similar integrator at a remote point, the remote integrator output is a copy of the transmitting control loop integrator output. To the extent that the integrator at the transmitting locations tracks the input signal, the remote receiver reproduces the input signal. Low pass filtering at the receiver output will eliminate most of the quantizing noise, if the clock rate of the bit stream is an octave or more above the bandwidth of the input signal. Voice bandwidth is 4.0 kHz and clock rates from 8.0 k and up are possible. Thus, the delta modulator digitizes and transmits the analog input to a remote receiver. The serial, unframed nature of the data is ideal for communications networks. With no input at the transmitter, a continuous one zero alternation is transmitted. If the two integrators are made leaky, then during any loss of contact the receiver output decays to zero and receive restart begins without framing when the receiver reacquires. Similarly, a delta modulator is tolerant of sporadic bit errors. Figure 12 shows the delta modulator waveforms while Figure 13 shows the corresponding CVSD decoder block diagram. The Companding Algorithm The fundamental advantages of the delta modulator are its simplicity and the serial format of its output. Its limitations are its ability to accurately convert the input within a limited digital 10 bit rate. The analog input must be band limited and amplitude limited. The frequency limitations are governed by the nyquist rate while the amplitude capabilities are set by the gain of the integrator. The frequency limits are bounded on the upper end; that is, for any input bandwidth there exists a clock frequency larger than that bandwidth which will transmit the signal with a specific noise level. However, the amplitude limits are bounded on both upper and lower ends. For a signal level, one specific gain will achieve an optimum noise level. Unfortunately, the basic delta modulator has a small dynamic range over which the noise level is constant. The continuously variable slope circuitry provides increased dynamic range by adjusting the gain of the integrator. For a given clock frequency and input bandwidth the additional circuitry increases the delta modulator’s dynamic range. External to the basic delta modulator is an algorithm which monitors the past few outputs of the delta modulator in a simple shift register. The register is 3–bits long. The accepted CVSD algorithm simply monitors the contents of the shift register and indicates if it contains all 1s or 0s. This condition is called coincidence. When it occurs, it indicates that the gain of the integrator is too small. The coincidence output charges a single–pole low pass filter. The voltage output of this syllabic filter controls the integrator gain through a pulse amplitude modulator whose other input is the sign bit or up/down control. The simplicity of the all 1s, all 0s algorithm should not be taken lightly. Many other control algorithms using the shift register have been tried. The key to the accepted algorithm is that it provides a measure of the average power or level of the input signal. Other techniques provide more instantaneous information about the shape of the input curve. The purpose of the algorithm is to control the gain of the integrator and to increase the dynamic range. Thus, a measure of the average input level is what is needed. The algorithm is repeated in the receiver and thus the level data is recovered in the receiver. Because the algorithm operates only on the past serial data, it changes the nature of the bit stream without changing the channel bit rate. The effect of the algorithm is to compand the input signal. If a CVSD encoder is played into a basic delta modulator, the output of the delta modulator will reflect the shape of the input signal but all of the output will be at an equal level. Thus, the algorithm at the output is needed to restore the level variations. The bit stream in the channel is as if it were from a standard delta modulator with a constant level input. The delta modulator encoder with the CVSD algorithm provides an efficient method for digitizing a voice input in a manner which is especially convenient for digital communications requirements. MOTOROLA ANALOG IC DEVICE DATA MC34115 Figure 15. 16 kHz Simplex Voice Codec (Using MC34115, Single–Pole Companding and Single Integration) Digital Input Digital Output Clock 16 kHz 5.0 Push To Talk Key (Norm Open) 5.0 10 k Encode/Decode 15 Analog Input + 1 4.0 µF 2 600 – 12 Analog Output 10 k Shift Register + 10 0.1 VCC/2 Ref 11 Ref Input 7 Syl In + – Analog Out R1 Coin Out Logic 5 C1 14 VCC 16 + Vth 1.0 k 9 Clock Comp – 13 600 Digital Out Filter 6 Ref VEE RS 18 k CS 0.33 2.4 M Rmin 3 GC Slope Polarity Switch 4 0.1 3.3 k RP 1.3 k Rx 8 10 k VS APPLICATIONS INFORMATION CVSD DESIGN CONSIDERATIONS A simple CVSD encoder using the MC34115 is shown in Figure 15. This IC is a general purpose CVSD building block which allows the system designer to tailor the encoder’s transmission characteristics to the application. Thus, the achievable transmission capabilities are constrained by the fundamental limitations of delta modulation and the design of encoder parameters. The performance is not dictated by the internal configuration of the MC34115. There are six design considerations involved in designing these basic CVSD building blocks into a specific codec application. These are listed below: 1. 2. 3. 4. 5. 6. Selection of clock rate Selection of loop gain Selection of minimum step size Design of integration filter transfer function Design of syllabic filter transfer function Design of low pass filter at the receiver The circuit in Figure 15 is the most basic CVSD circuit possible. For many applications in secure radio or other intelligible voice channel requirements, it is entirely sufficient. MOTOROLA ANALOG IC DEVICE DATA In this circuit, items 4 and 5 are reduced to their simplest form. The syllabic and integration filters are both single–pole networks. The selection of items 1 through 3 govern the codec performance. Layout Considerations Care should be exercised to isolate all digital signal paths (Pins 9, 11, 13 and 14) from analog signal paths (Pins 1 to 7 and 10) in order to achieve proper idle channel performance. Clock Rate With minor modifications, the circuit in Figure 15 may be operated anywhere from 9.6 to 64 kHz clock rates. Obviously the higher the clock rate the higher the S/N performance. The circuit in Figure 15 typically produces the S/N performance shown in Figure 16. The selection of clock rate is usually dictated by the bandwidth of the transmission medium. Voice bandwidth systems will require no higher than 9600 Hz. Some radio systems will allow 12 kHz. Private 4–wire telephone systems are often operated at 16 kHz and commercial telephone performance can be achieved at 32 k bits and above. 11 MC34115 Figure 16. Signal–to–Noise Performance with Single Integration, Single–Pole and Companding at 16 k Bits (Typical) + S/N (dB) 15 Clock Rate = 16 kHz Test Tone = 1.0 kHz Sine Wave Noise Weighting C Message 10 5.0 –40 –30 –20 –10 0 10 INPUT LEVEL (dB) RELATIVE TO SLOPE OVERLOAD Selection of Loop Gain The gain of the circuit in Figure 15 is set by resistor Rx. Rx must be selected to provide the proper integrator step size for high level signals such that the companding ratio does not exceed about 25%. The companding ratio is the active low duty cycle of the coincidence output on Pin 11 of the codec circuit. Thus, the system gain is dependent on: 1. The maximum level and frequency of the input signal. 2. The transfer function of the integration filter. For voice codecs the typical input signal is taken to be a sine wave at 1.0 kHz of 0 dBmo level. In practice, the useful dynamic range extends about 6.0 dB above the design level. In any system the companding ratio should not exceed 30%. To calculate the required step size current, we must describe the transfer characteristics of the integration filter. In the basic circuit of Figure 15, a single–pole of 160 Hz is used. R1 10 kΩ, C1 0.1 µF + V O+ I i + 5 S )K wo ǒ) Ǔ 1 C S 1 RC wo + 2 πf 3 10 + w o + 2 f + 159.2 Hz πf + + ) Minimum Step Size The final parameter to be selected for the simple codec in Figure 15 is idle channel step size. With no input signal, the digital output becomes a one–zero alternating pattern and the analog output becomes a small triangle wave. Mismatches of internal currents and offsets limit the minimum step size which will produce a perfect idle channel pattern. The MC34115 is tested to ensure that a 20 mVpp minimum step size at 16 kHz will attain a proper idle channel. The idle channel step size must be twice the specified total loop offset if a one–zero idle pattern is desired. In some applications a much smaller minimum step size (e.g., 0.1 mV) can produce quiet performance without providing a 1 – 0 pattern. To set the idle channel step size, the value of Rmin must be selected. With no input signal, the slope control algorithm is inactive. A long series of ones or zeros never occurs. Thus, the voltage across the syllabic filter capacitor (CS) would decay to zero. However, the voltage divider of RS and Rmin (see Figure 15) sets the minimum allowed voltage across the syllabic filter capacitor. That voltage must produce the desired ramps at the analog output. Again we write the filter input current equation: V dV O I C O i R dt For values of VO near VCC/2 the VO/R term is negligible; thus: DVO I C i S DT + ) + where ∆T is the clock period and ∆VO is the desired peak–to–peak value of the idle output. For a 16 k bit system using the circuit in Figure 15: 0.1 µF 20 mV I 32 µA i 62.5 µs The voltage on CS which produces a 32 µA current is determined by the value of Rx. I R x V min; for 32 µA, V min 41.6 mV i S S In Figure 15 RS is 18 kΩ. That selection is discussed with the syllabic filter considerations. The voltage divider of RS and Rmin must produce an output of 41.6 mV. R S V min R 2.4 MΩ V min S CC R R min S Having established these three parameters – clock rate, loop gain and minimum step size – the encoder circuit in Figure 15 will function at near optimum performance for input levels around 0 dBm. + Note that the integration filter produces a single–pole response from 300 to 3.0 kHz. The current required to move the integrator output a specific voltage from zero is simply: dV V O C O I i dt R Now a 0 dBmo sine wave has a peak value of 1.0954 V. In 1/8 of a cycle of a sine wave centered around the zero crossing, the sine wave changes by approximately its peak value. The CVSD step should trace that change. The required current for a 0 dBm 1.0 kHz sine wave is: 0.1 µF (1.1) 1.1 V I 0.935 mA i 0.125 ms * 2 (10 kΩ) 12 * The maximum voltage across R when maximum slew is required is: 1.1 V 2 Now the voltage range of the syllabic filter is the power supply voltage, thus: 1 Rx 0.25 (V ) CC 0.935 mA A similar procedure can be followed to establish the proper gain for any input level and integration filter type. ) + + + + ) + ] MOTOROLA ANALOG IC DEVICE DATA MC34115 INCREASING CVSD PERFORMANCE Integration Filter Design The circuit in Figure 15 uses a single–pole integration network formed with a 0.1 µF capacitor and a 10 kΩ resistor. It is possible to improve the performance of the circuit in Figure 15 by 1.0 or 2.0 dB by using a two–pole integration network. The improved circuit is shown in Figure 17. The first pole is still placed below 300 Hz to provide the 1/S voice content curve and a second pole is placed somewhere above the 1.0 kHz frequency. For telephony circuits, the second pole can be placed above 1.8 kHz to exceed the 1633 touchtone frequency. In other communication systems, values as low as 1.0 kHz may be selected. In general, the lower in frequency the second pole is placed, the greater the noise improvement. Then, to ensure the encoder loop stability, a zero is added to keep the phase shift less than 180°. This zero should be placed slightly above the low–pass output filter break frequency so as not to reduce the effectiveness of the second pole. A network of 235 Hz, 2.0 kHz and 5.2 kHz is typical for telephone applications while 160 Hz, 1.2 kHz and 2.8 kHz might be used in voice only channels. (Voice only channels can use an output low–pass filter which breaks at about 2.5 kHz.) The two–pole network in Figure 17 has a transfer function of: V O I i ǒ ǒ) Ǔ 1 R1C1 R0R1 S + R2C2(R0 ) R1) S Ǔ ) ǒR0)1R1ǓC1 S ) ǒ Ǔ 1 R2C2 Figure 17. Improved Filter Configuration 5 R2 Analog Output 7 The calculation of desired gain resistor Rx then proceeds exactly as previously described. Syllabic Filter Design The syllabic filter in Figure 15 is a simple single–pole network of 18 kΩ and 0.33 µF. This produces a 6.0 ms time constant for the averaging of the coincidence output signal. The voltage across the capacitor determines the integrator current which in turn establishes the step size. The integrator current and the resulting step size determine the companding ratio and the S/N performance. The companding ratio is defined as the voltage across CS/VCC. The S/N performance may be improved by modifying the voltage to current transformation produced by Rx. If different portions of the total Rx are shunted by diodes, the integrator current can be other than (V CC – VS)/Rx. These breakpoint curves must be designed experimentally for the particular system application. In general, one would wish that the current would double with input level. To design the desired curve, supply current to Pin 4 of the codec from an external source. Input a signal level and adjust the current until the S/N performance is optimum. Then record the syllabic filter voltage and the current. Repeat this for all desired signal levels. Then derive the resistor diode network which produces that curve on a curve tracer. Once the network is designed with the curve tracer, it is then inserted in place of Rx in the circuit and the forced optimum noise performance will be achieved from the active syllabic algorithm. Diode breakpoint networks may be very simple or moderately complex and can improve the usable dynamic range of any codec. In the past they have been used in high performance telephone codecs. Typical resistor–diode networks are shown in Figure 18. Figure 18. Resistor–Diode Networks 600 C2 0.15 R1 MC34115 C1 R0 0.1 D1 R1 NOTE: These component values are for the telephone channel circuit poles described in the text. The R2, C2 product can be provided with different values of R and C. R2 should be chosen to be equal to the termination resistor on Pin 1. Thus, the two poles and the zero can be selected arbitrarily as long as the zero is at a higher frequency than the first pole. The values in Figure 17 represent one implementation of the telephony filter requirement. The selection of the two–pole filter network affects the selection of the loop gain value and the minimum step size resistor. The required integrator current for a given change in voltage now becomes: V DVO O R2C2 R1C1 C1 I i R0 DT R0 R0 ǒ ) ǒ R2C2C1 ) ) ) R1C1R2C2 R0 Ǔ R3 6 R1 600 13 k + R2 Ǔ D2 D3 R2 D1 Output Low Pass Filter A low pass filter is required at the receiving circuit output to eliminate quantizing noise. In general, the lower the bit rate, the better the filter must be. The filter in Figure 19 provides excellent performance for 12 kHz to 40 kHz systems. ) DVO 2 DT 2 MOTOROLA ANALOG IC DEVICE DATA 13 MC34115 Figure 19. High Performance Elliptic Filter for CVSD Output C1 R7 1000 R1 R2 87.6 k 175 k C3 157 C4 78 1.0 k R6 – 600 k 212 k + R4 1.11 M R3 247 k Designed for 0.28 dB ripple in the pass band ωn = 3.0 kHz ωs = ≅ 6.0 kHz AdB at ωs and above 29.5 dB R5 MC1741 C5 380 C2 220 Figure 20. Full Duplex/16 k Bit CVSD Voice Codec Digital Output Force Idle Channel C2 C1 R2 1 R3 13 9 5 11 – C3 R1 5.0 V 16 2 + Analog Output 15 12 CS1 MC34115 10 0.1 R12 CI1 R I1 RP1 3 7 4 6 8 RS1 RM1 RX1 14 Clock 14 5.0 V 16 12 Analog Output 5 – 11 C9 R11 R7 R6 + R10 C7 R9 C6 R8 R5 R4 MC34115 CI2 R S2 R I2 + CS2 3 7 + – C8 Digital 9 Test C5 RP2 RM2 RX2 4 6 8 15 13 Digital Input C4 Codec Components Input Filter Specifications Filter Components RX1, RX2 – 3.3 kΩ RP1, RP2 – 3.3 kΩ RS1, RS2 – 100 kΩ RI1, RI2 – 20 kΩ R12 – 1.0 kΩ RM1, RM2 – 10 MΩ Minimum step size = 20 mV 12 dB/Octave Rolloff above 3.3 kHz 6.0 dB/Octave Rolloff below 50 Hz R1 – 965 Ω R2 – 72 kΩ R3 – 72 kΩ R4 – 63.46 kΩ R5 – 127 kΩ R6 – 365.5 kΩ R7 – 1.645 MΩ R8 – 72 kΩ R9 – 72 kΩ R10 – 29.5 Ω R11 – 72 kΩ CS1, CS2 – 0.05 µF CI1, CI2 – 0.05 µF 2 MC34115 1 MC3403 (or MC3406) NOTE: All Res. 5% All Cap. 5% 14 Output Filter Specifications Break Frequency – 3.3 kHz Stop Band – 9.0 kHz Stop Band Atten. – 50 dB Rolloff – > 40 dB/Octave C1 – 3.3 µF C2 – 837 pF C3 – 536 pF C4 – 1000 pF C5 – 222 pF C6 – 77 pF C7 – 38 pF C8 – 837 pF C9 – 536 pF NOTE: All Res. 0.1% to 1% All Cap. 1% MOTOROLA ANALOG IC DEVICE DATA MC34115 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M –A– MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 8X P 0.010 (0.25) 1 M B M 8 J D 0.010 (0.25) M T A S B S F R X 45 _ C –T– 14X INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 DW SUFFIX PLASTIC PACKAGE CASE 751G–02 (SO–16L) ISSUE A 16 16X DIM A B C D F G H J K L M S G K SEATING PLANE MOTOROLA ANALOG IC DEVICE DATA M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 15 MC34115 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 16 ◊ *MC34115/D* MOTOROLA ANALOG IC DEVICE DATA MC34115/D