MC74F194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The MC74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The F194 is similar in operation to the S195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation. • • • • 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER FAST SCHOTTKY TTL Typical Shift Frequency of 150 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers J SUFFIX CERAMIC CASE 620-09 FUNCTIONAL DESCRIPTION 16 The F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Function Table. Signals on the Select, Parallel data (P0 – P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. 1 N SUFFIX PLASTIC CASE 648-08 16 1 CONNECTION DIAGRAM VCC Q0 Q1 Q2 Q3 CP S1 S0 16 15 14 13 12 11 10 9 D SUFFIX SOIC CASE 751B-03 16 1 ORDERING INFORMATION 1 MR 2 DSR 3 P0 4 P1 5 P2 MC74FXXXJ MC74FXXXN MC74FXXXD 8 7 DSL GND 6 P3 LOGIC SYMBOL FUNCTION TABLE Operating Mode Reset Ceramic Plastic SOIC Inputs MR L S1 X S0 X Outputs DSR DSL X X Pn X Hold H I I X X X Shift Left H H h h I I X X I h Shift Right H H I I h h I h Parallel Load H h h X 11 10 9 Q0 Q1 Q2 Q3 L L L L 1 X X q0 q1 q1 q1 q2 q2 q2 q3 q3 q3 L H 15 X X X X L H q0 q0 q1 q1 q2 q2 13 X pn p0 p1 p2 p3 I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. pn, qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 4-101 14 12 CP S1 S0 DSR MR P0 Q0 P1 Q1 P2 Q2 P3 DSL Q3 VCC = PIN 16 GND = PIN 8 2 3 4 5 6 7 MC74F194 LOGIC DIAGRAM P0 P1 P2 P3 S1 S0 DSR DSR S Q0 S CP R CLEAR Q1 S CP R CLEAR Q2 S CP R CLEAR Q3 CP R CLEAR CP MR Q0 Q1 Q2 Q3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 – 1.0 mA IOL Output Current — Low 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Power Supply Current Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage – 1.2 V IIN = –18 mA VCC = MIN 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.5 V 74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 0.35 – 60 33 20 µA VIN = 2.7 V 100 µA VIN = 7.0 V – 0.6 mA VIN = 0.5 V VCC = MAX –150 mA VOUT = 0 V VCC = MAX mA Sn, MR, DSR, DSL = 4.5 V Pn = Gnd, CP = VCC = MAX 46 NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-102 VCC = MAX MC74F194 AC CHARACTERISTICS Symbol Parameter 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0 to +70°C VCC = 5.0 V ±10% CL = 50 pF Min Max Min Max 90 Unit fmax Maximum Shift Frequency 105 MHz tPLH tPHL Propagation Delay CP to Qn 3.0 3.5 7.0 7.5 3.5 3.5 8.0 8.0 ns tPHL Propagation Delay MR to Qn 4.5 12 4.5 14 ns AC OPERATING REQUIREMENTS Symbol Parameter ts(H) ts(L) Set up Time, HIGH or LOW Pn or DSR or DSL to CP th(H) th(L) Hold Time, HIGH or LOW Pn or DSR or DSL to CP ts(H) ts(L) Set up Time, HIGH or LOW Sn to CP th(H) th(L) Hold Time, HIGH or LOW Sn to CP tw(H) 74F 74F TA = +25°C VCC = +5.0 V TA = 0 to +70°C VCC = 5.0 V ±10% Min Max Min Max Unit 4.0 4.0 4.0 4.0 0 0 1.0 1.0 8.0 8.0 9.0 8.0 0 0 0 0 CP Pulse Width HIGH 5.0 5.5 ns tw(L) MR Pulse Width LOW 5.0 5.0 ns trec Recovery Time MR to CP 7.0 8.0 ns ns ns FAST AND LS TTL DATA 4-103