SEMICONDUCTOR TECHNICAL DATA
The MC88LV915T Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance PC’s
and workstations.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88LV915T to multiply
a low frequency input clock and distribute it locally at a higher (2X) system
frequency. Multiple 88LV915’s can lock onto a single reference clock, which
is ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see Figure 4 on Page 9).
Order Number: MC88LV915T/D
Rev 3, 08/2001
LOW SKEW CMOS
PLL CLOCK DRIVER
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 2 detail
the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz).
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing
(see detailed description on page 11).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the
OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go
low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees
a SYNC signal and full 5V VCC.
Features
• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t PD
specification, which defines the part–to–part skew)
• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
• Input frequency range from 5MHz – 2X_Q FMAX spec.
• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL–level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge
• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3–state) for board test purposes
• Lock Indicator (LOCK) accuracy indicates a phase–locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
Motorola, Inc. 2001
Pinout: 28–Lead PLCC (Top View)
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PLASTIC PLCC
CASE 776–02
PIN SUMMARY
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MOTOROLA
MC88LV915T BLOCK DIAGRAM
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3
MAXIMUM RATINGS*
Symbol
Parameter
Limits
Unit
VCC, AVCC
DC Supply Voltage Referenced to GND
–0.5 to 7.0
V
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Iin
DC Input Current, Per Pin
±20
mA
Iout
DC Output Sink/Source Current, Per Pin
±50
mA
ICC
DC VCC or GND Current Per Output Pin
±50
mA
Tstg
Storage Temperature
–65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Limits
Unit
VCC
Supply Voltage
3.3 ±0.3
V
Vin
DC Input Voltage
0 to VCC
V
Vout
DC Output Voltage
0 to VCC
V
TA
Ambient Operating Temperature
0 to 70
°C
ESD
Static Discharge Voltage
> 1000
V
DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)
Symbol
Parameter
VCC
Guaranteed Limits
Unit
Condition
VIH
Minimum High Level Input Voltage
3.0
3.3
2.0
2.0
V
VOUT = 0.1V or
VCC – 0.1V
VIL
Minimum Low Level Input Voltage
3.0
3.3
0.8
0.8
V
VOUT = 0.1V or
VCC – 0.1V
VOH
Minimum High Level Output Voltage
3.0
3.3
2.4
2.7
V
VIN = VIH or VIL
IOH= –24mA
VOL
Minimum Low Level Output Voltage
3.0
3.3
0.44
0.44
V
VIN = VIH or VIL
IOH= 24mA
IIN
Maximum Input Leakage Current
3.6
±1.0
µA
VI = VCC, GND
ICCT
Maximum ICC/Input
3.6
2.0
mA
VI = VCC – 2.1V
IOLD
Dynamic3
3.6
+50
mA
VOLD = 1.25V
3.6
–50
mA
VOHD =2.35V
3.6
TBD
µA
VI = VCC, GND
Minimum
Output Current
IOHD
ICC
Maximum Quiescent Supply Current
1. IOL is +12mA for the RST_OUT output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
tRISE/FALL
SYNC Input
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
tCYCLE,
SYNC Input
Input Clock Period
SYNC Input
Duty Cycle
Duty Cycle, SYNC Input
4
Minimum
Maximum
Unit
—
5.0
ns
1
f2X_Q4
100
ns
50% ± 25%
MOTOROLA
FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)
Symbol
Parameter
Guaranteed Minimum
Unit
Fmax (2X_Q)
Maximum Operating Frequency, 2X_Q Output
100
MHz
Fmax (‘Q’)
Maximum Operating Frequency,
Q0–Q3 Outputs
50
MHz
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50Ω Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
0.5
2.0
ns
Into a 50Ω Load
Terminated to VCC/2
tPULSE WIDTH
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5 1
0.5tCYCLE + 0.5 1
ns
Into a 50Ω Load
Terminated to VCC/2
tPULSE WIDTH
(2X_Q Output)
Output Pulse Width:
2X_Q @ 1.5V
40MHz
66MHz
80MHz
100MHz
0.5tCYCLE – 1.5
0.5tCYCLE – 1.0
0.5tCYCLE – 1.0
0.5tCYCLE – 1.0
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
ns
Into a 50Ω Load
Terminated to VCC/2
tCYCLE
(2x_Q Output)
Cycle–to–Cycle Variation
2x_Q @ VCC/2
40MHz
66MHz
80MHz
100MHz
tCYCLE – 600ps
tCYCLE – 300ps
tCYCLE – 300ps
tCYCLE – 400ps
tCYCLE + 600ps
tCYCLE + 300ps
tCYCLE + 300ps
tCYCLE + 400ps
tPD2
SYNC Feedback
F db k
(With 1MΩ from RC1 to An VCC)
Condition
ns
SYNC Input to Feedback Delay 66MHz
(Measured at SYNC0 or 1 and
80MHz
FEEDBACK Input Pins)
100MHz
–1.65
–1.45
–1.25
–1.05
–0.85
–0.65
tSKEWr3
(Rising) See Note 4
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
—
500
ps
All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
tSKEWf3
(Falling)
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
—
750
ps
All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
tSKEWall3
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
—
750
ps
All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
tLOCK4
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL5
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
tPHZ,tPLZ5
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
1.
2.
3.
4.
TCYCLE in this spec is 1/Frequency at which the particular output is running.
The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
Under equally loaded conditions and at a fixed temperature and voltage.
With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with
C1 = 0.01µF.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
MOTOROLA
5
Applications Information for All Versions
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Figure 1. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook–up configuration of Figure 2a on page 7)
Timing Notes:
• The MC88LV915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input
does not require a 50% duty cycle.
• All skew specs are measured between the VCC/2 crossing point of the appropriate output edges.All skews
are specified as ‘windows’, not as a ± deviation around a center point.
• If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency
would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the
Q/2 output would run at half the SYNC frequency.
6
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MOTOROLA
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Figure 3. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 3 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
of the bypass filtering scheme shown in Figure 3 is to give
the 88LV915T additional protection from the power supply
and ground plane transients that can occur in a high
frequency, high speed digital system.
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1c.There are no special requirements set forth for the loop
filter resistors (1MΩ and 330Ω). The loop filter capacitor
(0.1µF) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1b.The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will minimize the
88LV915T’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This filter will
typically ensure that a 100mV step deviation on the digital
VCC supply will cause no more than a 100pS phase
deviation on the 88LV915T outputs. A 250mV step
deviation on VCC using the recommended filter values
should cause no more than a 250pS phase deviation; if a
25µF bypass capacitor is used (instead of 10µF) a 250mV
VCC step should cause no more than a 100pS phase
deviation.
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1MΩ
resistor provides the correct amount of current injection
into the charge pump (2–3µA). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5MΩ reference
resistor should be used (instead of 1MΩ).
If good bypass techniques are used on a board design
near components which may cause digital VCC and ground
noise, the above described VCC step deviations should not
occur at the 88LV915T’s digital VCC supply. The purpose
8
2. In addition to the bypass capacitors used in the analog filter
of Figure 3, there should be a 0.1µF bypass capacitor
between each of the other (digital) four VCC pins and the
board ground plane. This will reduce output switching
noise caused by the 88LV915T outputs, in addition to
reducing potential for noise in the ‘analog’ section of the
chip. These bypass capacitors should also be tied as close
to the 88LV915T package as possible.
MOTOROLA
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Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88LV915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The
2X_Q output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–
down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high
impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It
will take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
MOTOROLA
9
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
ISSUE D
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MOTOROLA
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MOTOROLA
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their
respective owners. Motorola, Inc. 2001.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334
Technical Information Center: 1–800–521–6274
HOME PAGE: http://www.motorola.com/semiconductors/
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